KR102031234B1

KR102031234B1 - Gate driving circuit and organic light emitting display device including the same

Info

Publication number: KR102031234B1
Application number: KR1020160026258A
Authority: KR
Inventors: 변춘원; 양종헌; 윤성민; 조경익; 황치선
Original assignee: 한국전자통신연구원; 경희대학교 산학협력단
Priority date: 2015-07-28
Filing date: 2016-03-04
Publication date: 2019-10-14
Also published as: KR20170015098A

Abstract

The gate driving circuit according to an embodiment of the present invention includes an i-th modulation circuit (where i is a natural number of 2 or more) and an i-th line selection circuit. The i-th modulation circuit outputs the i-th modulation voltage to the i-th line selection circuit based on the received first to third control signals. The i-th line select circuit includes a memory transistor that is turned on or off depending on the level of the received i-th modulation voltage.

Description

GATE DRIVING CIRCUIT AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display, and more particularly, to an organic light emitting display including a gate driving circuit and a gate driving circuit that consume an improved degree of integration and low power.

Various displays have been developed for use in multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, game machines, and the like. One type of display device is an organic light emitting display (OLED). The organic light emitting display device is a self-luminous display device, and has an advantage of wide viewing angle, excellent contrast, and fast response speed.

The organic light emitting diode display includes a plurality of pixels. Each of the plurality of pixels includes an organic light emitting diode and a circuit unit for controlling the organic light emitting diode. The circuit portion includes at least a switching transistor, a driving transistor, and a storage capacitor. The organic light emitting diode includes an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode. The organic light emitting diode emits light when a voltage equal to or higher than the threshold voltage of the organic light emitting layer is applied between the anode and the cathode.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting display including a gate driving circuit and a gate driving circuit that consume less power while increasing the degree of integration of the circuit.

An organic light emitting diode display according to an exemplary embodiment includes a gate driving circuit, a data driving circuit, and an organic light emitting display panel. The gate driving circuit provides the gate signals to the gate lines and the light emission control signals to the light emitting lines. The gate driving circuit includes the i-th modulation circuit, i-th (where i is a natural number of 2 or more), an i-th modulation circuit connected to an i + 1 th gate line, an i-th gate line, and an i-th line connected to an i-th light emitting line It includes a selection circuit. The i-th modulation circuit outputs the i-th modulation voltage to the i-th line selection circuit based on the received first to third control signals, and the i-th line selection circuit is turned on according to the level of the received i-th modulation voltage. Memory transistors that are turned on or off. The data driver circuit provides data signals to the data lines. The organic light emitting display panels include a plurality of pixels.

The organic light emitting display device including the driving circuit and the driving circuit according to the embodiment of the present invention as described above has a fast operation for the memory transistor by modulating the magnitude of the read voltage of the memory transistor having a non-volatile property. It can operate suitably also in this required operating environment. Furthermore, the organic light emitting diode display including the driving circuit and the driving circuit according to an exemplary embodiment of the present invention may operate based on fewer transistors than the number of transistors included in the conventional gate driving circuit. Therefore, the organic light emitting display device including the driving circuit and the driving circuit according to the embodiment of the present invention may be advantageous in miniaturization of the device. In addition, the organic light emitting display device including the driving circuit and the driving circuit according to the embodiment consumes less power than when using the conventional gate driving circuit.

1 is a block diagram of an organic light emitting display device according to an exemplary embodiment.
2 is an equivalent circuit of a pixel included in an organic light emitting display panel according to an exemplary embodiment of the present invention.
3 is a block diagram illustrating a gate driving circuit according to an exemplary embodiment of the present invention.
4 is a circuit diagram illustrating in detail a gate driving circuit according to an exemplary embodiment of the present invention.
5 is a diagram relating to operating characteristics of a memory transistor.
6 is a timing diagram for describing an operation of a driving circuit according to an exemplary embodiment of the present invention.
FIG. 7 is a circuit diagram illustrating an operation of a gate driving circuit in a section T1-T2 of FIG. 6.
FIG. 8 is a circuit diagram illustrating an operation of a gate driving circuit in a section T3-T4 of FIG. 6.
FIG. 9 is a circuit diagram illustrating an operation of a gate driving circuit in a section T4-T5 of FIG. 6.
FIG. 10 is a circuit diagram illustrating an operation of a gate driving circuit in a section T5-T6 of FIG. 6.

The foregoing characteristics and the following detailed description are all illustrative for ease of explanation and understanding of the invention. That is, the present invention is not limited to this embodiment and may be embodied in other forms. The following embodiments are merely examples to fully disclose the present invention, and are descriptions for conveying the present invention to those skilled in the art to which the present invention pertains. Thus, where there are several methods for implementing the components of the present invention, it is necessary to clarify that the implementation of the present invention is possible in any of these methods or any of the same.

In the present specification, when there is a statement that a configuration includes specific elements, or when a process includes specific steps, it means that other elements or other steps may be further included. That is, the terms used in the present specification are only for describing specific embodiments and are not intended to limit the concept of the present invention. Furthermore, the described examples to aid the understanding of the invention also include their complementary embodiments.

The terms used in the present specification have the meanings that are commonly understood by those skilled in the art. Terms commonly used should be interpreted in a consistent sense in the context of the present specification. In addition, terms used in the present specification should not be interpreted in an idealistic or formal sense unless the meaning is clearly defined. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of an organic light emitting display device according to an embodiment of the present invention. Referring to FIG. 1, the organic light emitting diode display 1000 includes a timing control circuit 100, a gate driving circuit 200, a data driving circuit 300, and an organic light emitting display panel DP.

The timing control circuit 100 receives input image signals (not shown). The timing control circuit 100 converts the data format of the input image signals to meet the interface specification with the data driving circuit 300 based on the received input image signals (not shown) to generate the image data. Can be. Next, the timing control circuit 100 may output image data Data, various control signals DCS, CTRL_1, CTRL_2, and CTRL_3 and first and second power voltages EL_H and EL_L.

The gate driving circuit 200 receives the gate control signal SCS, the first to third control signals CTRL_1, CTRL_2, and CTRL_3 and the first and second power voltages EL_H and EL_L from the timing control circuit 100. Receive. The gate control signal SCS may include a vertical start signal for starting the operation of the gate driving circuit 200, a clock signal for determining an output timing of the signals, and the like. The gate driving circuit 200 may generate a plurality of gate signals and sequentially output the plurality of gate signals to the plurality of gate lines GL1 to GLn described later.

In addition, the gate driving circuit 200 emits light based on the gate control signal SCS, the first to third control signals CTRL_1, CTRL_2, and CTRL_3 and the first and second power voltages EL_H and EL_L. Generate control signals. The gate driving circuit 200 outputs a plurality of light emission control signals to a plurality of light emitting lines EL1 to ELn described later.

Although FIG. 1 illustrates that a plurality of gate signals and a plurality of emission control signals are output from one gate driving circuit 200, the present invention is not limited thereto. According to an embodiment of the present disclosure, the plurality of gate driving circuits may divide and output the plurality of gate signals and may output the plurality of emission control signals. In addition, in an embodiment of the present disclosure, a driving circuit for generating and outputting a plurality of gate signals and a driving circuit for generating and outputting a plurality of emission control signals may be separately classified.

The data driving circuit 300 receives the data control signal DCS and the image data Data from the timing control circuit 100. The data driving circuit 300 converts the image data Data into data signals and outputs the data signals to the plurality of data lines DL1 to DLm described later. The data signals are analog voltages corresponding to grayscale values of the image data Data.

The organic light emitting display panel DP includes a plurality of gate lines GL1 to GLn, a plurality of light emitting lines EL1 to ELn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX. do. The plurality of gate lines GL1 to GLn extend in the first direction DR1 and are arranged in the second direction DR2 orthogonal to the first direction DR1. Each of the plurality of light emitting lines EL1 to ELn may be arranged in parallel with a corresponding gate line among the plurality of gate lines GL1 to GLn. The plurality of data lines DL1 to DLm intersect with the plurality of gate lines GL1 to GLn insulated.

Each of the plurality of pixels PX includes a corresponding gate line among the plurality of gate lines GL1 to GLn, a corresponding light emitting line among the plurality of light emitting lines EL1 to ELn, and a plurality of data lines DL1 to DLm. Are connected to the corresponding data lines. Each of the plurality of pixels PX receives a first pixel voltage EL_VDD and a second pixel voltage EL_VSS at a level lower than that of the first pixel voltage EL_VDD. Each of the plurality of pixels PX is connected to a power line PL to which the first pixel voltage EL_VDD is applied. Each of the plurality of pixels PX is connected to an initialization line RL that receives an initialization voltage Vint. Although briefly illustrated in FIG. 1, each of the plurality of pixels PX may be connected to a plurality of gate lines among the plurality of gate lines GL1 to GLn.

According to an embodiment of the present disclosure, light emission signals applied to light emission lines may be generated based on gate signals applied to gate lines. Therefore, according to the embodiment of the present invention, it is possible to cut off the unnecessary power supply and reduce the clocking power. In other words, power consumption is reduced by reducing the number of clocks required for circuit operation, as compared with the conventional technique of generating gate signals using a plurality of clocks. In addition, since the number of elements used for generating the clock can be reduced, it is advantageous in terms of miniaturization of the area of the device.

2 is an equivalent circuit of a pixel included in an organic light emitting display panel according to an exemplary embodiment of the present invention. Referring to FIG. 2, the pixels PX include an organic light emitting diode OLED and a circuit unit for controlling the organic light emitting diode OLED.

The circuit unit may include a first transistor TR1, a second transistor TR2, a third transistor TR3, and a capacitor CAP.

The first transistor TR1 includes a first control electrode, a first input electrode and a first output electrode. For example, the first control electrode is connected to the gate line GL. For example, the first input electrode is connected to the data line DL. For example, the first output electrode is connected to the first electrode of the capacitor CAP to be described later and the control electrode of the second transistor TR2.

The capacitor CAP includes a first electrode connected to the first output electrode of the first transistor TR1 and a second electrode receiving the first pixel voltage EL_VDD. The capacitor CAP charges a voltage corresponding to the data signal received from the first transistor TR1.

The second transistor TR2 includes a second control electrode, a second input electrode and a second output electrode. For example, the second control electrode is connected to the first output electrode of the first transistor TR1. For example, the second input electrode receives the first pixel voltage EL_VDD. For example, the second output electrode is connected to the third input electrode of the third transistor TR3 described later.

The third transistor TR3 includes a third control electrode, a third input electrode and a third output electrode. For example, the third control electrode may be connected to the emission line EL to receive a plurality of emission control signals. For example, the third input electrode is connected to the second output electrode of the second transistor TR2. For example, the third output electrode is connected to the organic light emitting diode OLED. The third transistor TR3 performs an on / off operation according to the emission control signal received through the emission line EL. Accordingly, the third transistor TR3 may control the current corresponding to the voltage stored in the capacitor CAP to flow to the organic light emitting diode OLED.

The organic light emitting diode OLED includes an anode connected to an output electrode of the third transistor TR3 and receiving a first pixel voltage EL_VDD and a cathode receiving a second pixel voltage EL_VSS. In addition, the organic light emitting diode OLED includes a light emitting layer disposed between the anode and the cathode. The organic light emitting diode OLED may emit light during the turn-on period of the third transistor TR3.

According to an embodiment of the present disclosure, light emission signals applied to light emission lines may be generated based on gate signals applied to gate lines. For example, when the gate signal is a high level signal, the light emission signal may be a low level signal. In contrast, when the gate signal is a low level signal, the light emission signal may be a high level signal. The equivalent circuit of the pixels PX is not limited to FIG. 2 but may be modified.

3 is a block diagram illustrating a gate driving circuit according to an exemplary embodiment of the present invention. 1 to 3, the gate driving circuit 200 includes a plurality of modulation circuits corresponding to each of a plurality of gate lines GL_n-1, GL_n, GL_n + 1, and n is defined as two or more natural numbers. (M_n-1, M_n, M_n + 1) and a plurality of line select circuits LS_n-1, LS_n, LS_n + 1.

Each of the plurality of modulation circuits M_n-1, M_n, and M_n + 1 of FIG. 3 may be connected to one gate line. For example, the n-th modulation circuit M_n-1 is connected to the n-th gate line GL_n-2. For example, the n-th modulation circuit M_n is connected to the n-th gate line GL_n-1. The n + 1th modulation circuit M_n + 1 is connected to the nth control line GL_n.

Each of the plurality of modulation circuits M_n-1, M_n, and M_n + 1 of FIG. 3 is connected to a ground voltage VSS. In exemplary embodiments, the ground voltage VSS may be used to initialize voltages of the plurality of modulation circuits M_n-1, M_n, and M_n + 1.

Each of the plurality of modulation circuits M_n-1, M_n, and M_n + 1 receives the first to third control signals CTRL1, CTRL2, and CTRL3 received from the timing control circuit 100. FIG. Each of the plurality of modulation circuits M_n-1, M_n, and M_n + 1 has a plurality of modulation voltages VM_n-1, VM_n, and VM_n + based on the first to third control signals CTRL1, CTRL2, and CTRL3. 1) can be output respectively. For example, the n-th modulation circuit M_n-1 outputs the n-th modulation voltage VM_n-1 based on the first to third control signals CTRL1, CTRL2, and CTRL3. For example, the n-th modulation circuit M_n-1 outputs the n-th modulation voltage VM_n-1 based on the first to third control signals CTRL1, CTRL2, and CTRL3. For example, the n th modulation circuit M_n outputs an n th modulation voltage VM_n based on the first to third control signals CTRL1, CTRL2, and CTRL3. For example, the n + 1th modulation circuit M_n + 1 outputs an n + 1th modulation voltage VM_n + 1 based on the first to third control signals CTRL1, CTRL2, and CTRL3. The first to third control signals are described in more detail in the figures below.

Each of the plurality of line selection circuits LS_n-1, LS_n, and LS_n + 1 may be connected to the plurality of modulation circuits M_n-1, M_n, and M_n + 1, respectively. For example, the n-th line selection circuit LS_n-1 may be connected to the n-th modulation circuit M_n-1 to receive the n-th modulation voltage VM_n-1. For example, the n-th line selection circuit LS_n may be connected to the n-th modulation circuit M_n to receive the n-th modulation voltage VM_n. For example, the n + 1th line selection circuit LS_n + 1 may be connected to the n + 1th modulation circuit M_n + 1 to receive the n + 1th modulation voltage VM_n + 1.

Each of the plurality of line selection circuits LS_n-1, LS_n, and LS_n + 1 may be connected to the first power voltage EL_H and the second power voltage EL_L received from the timing control circuit 100. FIG. Each of the plurality of line selection circuits LS_n-1, LS_n, and LS_n + 1 is connected to the corresponding gate lines GL_n-1, GL_n, and GL_n + 1. For example, the n-th line selection circuit LS_n-1 is connected to the n-th gate line GL_n-1. For example, the n-th line select circuit LS_n is connected to the n-th gate line GL_n. For example, the n + 1 th line selection circuit LS_n + 1 is connected to the n + 1 th gate line GL_n + 1.

In addition, each of the plurality of line selection circuits LS_n-1, LS_n, and LS_n + 1 may receive the plurality of received modulation voltages VM_n-1, VM_n, VM_n + 1, and the plurality of gate signals GL_n-1, The first power source voltage EL_H or the second power source voltage EL_L may be selected based on GL_n and GL_n + 1 and output as the plurality of emission control signals EL_n-1, EL_n, and EL_n + 1.

4 is a circuit diagram illustrating in detail a gate driving circuit according to an exemplary embodiment of the present invention. 1 to 4, each of the plurality of modulation circuits M_n-1, M_n, and M_n + 1 may include five transistors and two capacitors.

For example, the n-th modulation circuit M_n includes first to fifth transistors T1_n-1 to T5_n-1 and first to second capacitors C1_n-1 and C2_n-1. . The nth modulation circuit M_n includes first to fifth transistors T1_n to T5_n and first to second capacitors C1_n and C2_n. The n + 1th modulation circuit M_n + 1 includes first to fifth transistors T1_n + 1 to T5_n + 1 and first to second capacitors C1_n + 1 and C2_n + 1.

Each of the plurality of line selection circuits LS_n-1, LS_n, and LS_n + 1 may include one memory transistor and one transistor. For example, the n-th line selection circuit LS_n-1 includes the n-th memory transistor MT_n-1 and the sixth transistor T6_n-1. For example, the n-th line select circuit LS_n includes an n-th memory transistor MT_n and a sixth transistor T6_n. For example, the n-th line select circuit LS_n includes an n-th memory transistor MT_n and a sixth transistor T6_n. For example, the n + 1th line selection circuit LS_n + 1 includes an nth + 1th memory transistor MT_n + 1 and a sixth transistor T6_n + 1.

For simplicity, the internal structure of the nth modulation circuit M_n and the internal structure of the nth line selection circuit LS_n will be described.

The nth modulation circuit M_n of FIG. 4 includes first to fifth transistors T1_n to T5_n and first to second capacitors C1_n and C2_n. For example, the first to fifth transistors T1_n to T5_n may be oxide thin film transistors (OTFTs). The oxide thin film transistor (OTFT) has a much smaller amount of leakage current (off current) than a general thin film transistor. Therefore, when the oxide thin film transistor (OTFT) is used, power consumption due to leakage current can be reduced. In addition, when the oxide thin film transistor (OTFT) is used, malfunction of the device due to leakage current may be reduced, thereby improving reliability of the device.

The control electrode of the first transistor T1_n receives the first control signal CTRL_1. Therefore, when the first control signal CTRL_1 is at the high level, the first transistor T1_n is turned on. The input electrode of the first transistor T1_n receives the second control signal CTRL_2. The output electrode of the first transistor T1_n is connected to the input electrode of the second transistor T2_n and the first capacitor C1_n.

The control electrode of the second transistor T2_n is connected to the n-th gate line GL_n-1. Therefore, the second transistor T2_n is turned on when the gate signal of the n-th gate line GL_n-1 is at a high level. The input electrode of the second transistor T2_n is connected to the output electrode of the first transistor T1_n and the first capacitor C1_n. The output electrode of the second transistor T2_n is connected to the input electrode of the third transistor T3_n and the second capacitor C2_n.

The control electrode of the third transistor T3_n receives the first control signal CTRL_1. Therefore, when the first control signal CTRL_1 is at the high level, the third transistor T3_n is turned on. The input electrode of the third transistor T3_n receives the third control signal CTRL_3. The output electrode of the third transistor T3_n is connected to the output electrode of the second transistor T2_n and the second capacitor C2_n.

The control electrode of the fourth transistor T4_n receives the first control signal CTRL_1. Therefore, when the first control signal CTRL_1 is at the high level, the fourth transistor T4_n is turned on. The input electrode of the fourth transistor T4_n receives the ground voltage signal VSS. The output electrode of the fourth transistor T4_n is connected to the output electrode of the fifth transistor T5_n, the first capacitor C1_n, and the second capacitor C2_n.

The control electrode of the fifth transistor T5_n is connected to the n + 1 th gate line GL_n + 1. Therefore, the fifth transistor T5_n corresponding to the nth gate line GL_n is turned on when the gate signal of the n + 1th gate line GL_n + 1 is at a high level. The input electrode of the fifth transistor T5_n receives the second control signal CTRL_2. The output electrode of the fifth transistor T5_n is connected to the output electrode of the fourth transistor T4_n, the first capacitor C1_n, and the second capacitor C2_n.

The first node N1_n may be an intersection point between the output electrode of the first transistor T1_n and the input electrode of the second transistor T2_n. The second node N2_n may be an intersection point between the output electrode of the second transistor T2_n and the output electrode of the third transistor T3_n. The third node N3_n may be an intersection point between the output electrode of the fourth transistor T4_n and the output electrode of the fifth transistor T5_n.

The first capacitor C1_n is connected between the first node N1_n and the third node N3_n. The second capacitor C2_n is connected between the second node N2_n and the third node N3_n. In addition, the magnitude of the capacitance C1 of the first capacitor C1_n may be smaller than the magnitude of the capacitance C2 of the second capacitor. When the capacitance C2 of the second capacitor is large, the amount of change in the value of the voltage stored in the first capacitor C1_n may be increased. As a result, accuracy of turn-on and turn-off operations of the memory transistor, which will be described later, may be improved.

The nth line selection circuit LS_n may include a memory transistor MT_n and a sixth transistor T6_n.

The memory transistor MT_n is a nonvolatile device that maintains programmed data characteristics regardless of whether a power source is present. The control electrode of the memory transistor MT_n is connected to the first node N1_n. Operation characteristics of the memory transistor MT_n are determined according to whether a program is performed and a level of a voltage applied to the first node N1_n. Operation characteristics of the memory transistor MT_n will be described in more detail with reference to the accompanying drawings. The input electrode of the memory transistor MT_n receives the first power voltage EL_H. The output electrode of the memory transistor MT_n is connected to the nth light-emitting line EL_n.

The sixth transistor T6_n may be an oxide thin film transistor (OTFT). As mentioned above, the oxide thin film transistor (OTFT) has a very small size of the off current. Therefore, when using an oxide thin film transistor (OTFT), the effect of reducing power consumption and the reliability of the device can be obtained. The control electrode of the sixth transistor T6_n is connected to the nth gate line GL_n. Therefore, the sixth transistor T6_n corresponding to the nth gate line is turned on when the gate signal of the nth gate line GL_n is at a high level. The input electrode of the sixth transistor T6_n receives the second power supply voltage EL_L. The output electrode of the sixth transistor T6_n is connected to the nth light-emitting line EL_n.

The internal structure of the nth modulation circuit M_n and the internal structure of the nth line selection circuit LS_n corresponding to the nth gate line GL_n of FIG. 4 have been described so far. Based on the description, the internal structure of the n-th modulation circuit M_n-1 corresponding to the n-th gate line GL_n-1 shown in FIG. 4 and the n-th line selection circuit LS_n The internal structure of -1), the internal structure of the n + 1 modulation circuit M_n + 1 corresponding to the n + 1th gate line GL_n + 1, and the internal structure of the n + 1th line selection circuit LS_n + 1 The structure may be understood.

5 is a diagram relating to operating characteristics of a memory transistor. 4 and 5, the memory transistor MT may have either a program state or an erase state. 5 represents the magnitude of the gate voltage VGS applied to the control electrode of the memory transistor MT, and the vertical axis of FIG. 5 represents the magnitude of the drain current IDS flowing through the channel of the memory transistor MT. do.

The state of the programmed memory transistor MT may indicate the first state S1. For example, when the first read voltage VRO_1 is applied to the gate voltage VGS of the memory transistor MT, the drain current IDS of the memory transistor MT in the first state S1 is turned on. It may be a current I_ON. In addition, when the second read voltage VRO_2 is applied to the gate voltage VGS of the memory transistor MT, the drain current IDS of the memory transistor MT in the first state S1 is turned off first. It may be a current I1_OFF. When the third read voltage VRO_3 is applied to the gate voltage VGS of the memory transistor MT, the drain current IDS of the memory transistor MT in the first state S1 is turned on. I_ON).

In addition, the state of the erased memory transistor MT may indicate the second state S2. For example, when the first read voltage VRO_1 is applied to the gate voltage VGS of the memory transistor MT, the drain current IDS of the memory transistor MT in the second state S2 is turned to the second turn. It may be an off current I2_OFF. Similarly, when the second read voltage VRO_2 is applied to the gate voltage VGS of the memory transistor MT, the drain current IDS of the memory transistor MT in the second state S2 is turned off. It may be the current I2_OFF. When the third read voltage VRO_3 is applied to the gate voltage VGS of the memory transistor MT, the drain current IDS of the memory transistor MT in the second state S2 is turned on. I_ON).

In the drawing of FIG. 5, the first off current I1_OFF and the second off current I2_OFF are represented as having different current levels, but this is exemplary, and the embodiment of the present invention is the first off current I1_OFF and the second. It will be appreciated that the off current I2_OFF may further include various embodiments having the same current level or the same level.

According to an embodiment of the present invention in which the memory transistor MT is integrated in the gate driving circuit, the magnitude of the drain current of the memory transistor MT having the same state (program state or erase state) by dynamically adjusting the magnitude of the read voltage. Can be adjusted. For example, when the first read voltage VRO_1 is applied to the gate voltage VGS of the memory transistor MT in the first state S1, the drain current IDS may be a turn-on current I_ON. . In this case, since the magnitude of the turn-on current I_ON is about 10 ^ 7 times larger than the magnitude of the first turn-off current I1_OFF or the second turn-off current I2_OFF, the first state S1 The memory transistor MT is turned on by the first read voltage VRO_1.

On the contrary, when the second read voltage VRO_2 that modulates the voltage magnitude of the first read voltage VRO_1 is applied to the gate voltage VGS of the memory transistor MT in the first state S1, the drain is applied. The first turn-off current I1_OFF may flow through the current IDS. In this case, since the magnitude of the first turn-off current I1_OFF is about 10 ^ -7 times smaller than the magnitude of the turn-on current I_ON, the memory transistor MT of the first state S1 reads the second. It is turned off by the voltage VRO_2. According to an embodiment of the present invention, as shown in FIG. 5, the level of the first read voltage VRO_1 is modulated to the level of the second read voltage VRO_2, or the level of the second read voltage VRO_2 is changed. Modulation can be performed at the level of the first read voltage VRO_1.

The present invention performs the turn-on or turn-off operation of the memory transistor MT based on the difference in the magnitude of the drain current according to the modulation of the read voltage level applied to the gate of the memory transistor MT. That is, when the gate voltage VGS of the existing constant voltage level is applied, a program operation or an erase operation for distinguishing the turn-on or turn-off operation of the memory transistor MT is not required. Therefore, a separate program time or erase time required for a program operation or an erase operation to distinguish the turn-on or turn-off operation of the conventional memory transistor MT is not required.

Therefore, the present invention can be applied even in an operating environment that requires a fast operation of the memory transistor MT (for example, an operation of turning on from a turn-on or switching from a turn-off to a turn-on).

6 is a timing diagram illustrating an operation of a gate driving circuit according to an exemplary embodiment of the present invention. 1 to 6, a driving circuit according to an exemplary embodiment of the present invention may include a plurality of gate lines GL_n-1, GL_n, and GL_n + 1 and a plurality of emission control lines EL_n-1, EL_n, and EL_n. Suppose you include +1).

The horizontal axes of FIG. 6 mean time, and are composed of first periods T0 to T1 to eighth periods T7 to T8. The vertical axes represent the level of the corresponding signal. In exemplary embodiments, one frame may include second to seventh periods T2 to T7. 6 illustrates the operation of the gate driving circuit in one frame, and it will be understood that the description may be omitted since the description is repeated for the next frame.

For reference, the first section T0 to T1 of FIG. 6 may indicate a section in which the gate signal of the last gate line (not shown) of the previous frame has a high level. In the third period T2 to T3 of FIG. 6, the gate signal having the high level of the first gate line GL_1 (not shown) is the gate having the high level of the n-2th gate line GL_n-2 (not shown). It may mean a section to which a signal is applied. In addition, the seventh periods T6 to T7 of FIG. 6 include the high level of the last gate line (not shown) of one frame from the gate signal having the high level of the n + 2th gate line GL_n + 2 (not shown). It may mean a section in which the gate signal having the same is applied.

The frame signal FR of FIG. 6 is at the high level FH in the first period T0 to T1. The frame signal FR is at the low level FL in the second period T1 to T2. As described later, a program operation is performed on the plurality of memory transistors MT in the first period T0 to T1 having the frame signal FR having the low level FL. That is, while the gate signals having the high level are sequentially applied from the first gate line GL_1 to the nth gate line GL_n, the frame signal FR maintains the high level FH. The frame signal FR of FIG. 6 has a high level FH in the remaining sections T2 to T7 in one frame.

The n-th gate line GL_n-1 of FIG. 6 has a high level GH in the fourth sections T3 to T4 and a low level GL in the remaining sections in one frame T1 to T7. It is a signal.

The n-th gate line GL_n of FIG. 6 is a signal having a high level GH in the fifth sections T4 to T5 and a low level in the remaining sections of one frame T1 to T7.

The n + 1 th gate line GL_n + 1 of FIG. 6 has a high level GH in the sixth section T5 to T6, and has a low level GL in the remaining sections of one frame T1 to T7. It is a signal.

The first control signal CTRL_1 of FIG. 6 is high only in the periods T1 to T2 (meaning the second period described above) in which the levels of the plurality of gate lines GL_n-1, GL_n, and GL_n + 1 are all low level. It may be a signal having a level CH and having a low level CL in the remaining sections of one frame T1 to T7.

The second control signal CTRL_2 of FIG. 6 rises to the program voltage V_PGM level for programming the memory transistor MT to be described later in the second period T1 to T2, and then the memory transistor MT. It has a boost voltage (V_BST) level after falling to the read-out voltage (V_RO) level for turning on. The second control signal CTRL_2 maintains the boost voltage V_BST level in the remaining sections T2 to T7 of one frame T1 to T7.

The third control signal CTRL_3 of FIG. 6 is a signal having a low level V_IL in the second sections T1 to T2 and a high level V_IH in the remaining sections of one frame T1 to T7. . In detail, the voltage level of the third control signal CTRL_3 in the second period T1 to T2 may charge the capacitor, which will be described later, to a negative voltage level.

It is assumed that the first node N1_n, the second node N2_n, the third node N3_n, and the nth emission line EL_n of FIG. 6 correspond to the nth gate line GL_n. After the voltage level of the first node N1_n of FIG. 6 rises to the program voltage V_PGM level for programming the memory transistor MT, which will be described later, in the second period T1 to T2, the memory transistor ( MT) is lowered to the readout voltage V_RO level for turning on. Subsequently, the voltage level of the first node N1_n may maintain the readout voltage V_RO level for the third period T2 to T3. Subsequently, the voltage level of the first node N1_n may maintain the modulation voltage V_RoM level during the fourth period T3 to T4 and the fifth period T4 to T5. Subsequently, the voltage level of the first node N1_n may maintain the readout voltage V_RO level during the sixth period T5 to T6 and the seventh period T6 to T7.

The voltage level of the second node N2_n in FIG. 6 drops to the low level V_IL in response to the control signal CTRL_3 in the second period T1 to T2. The low level V_IL means a negative voltage level. Subsequently, the voltage level of the second node N2_n may maintain the low level V_IL for the third period T2 to T3. Subsequently, the voltage level of the second node N2_n may maintain the modulation voltage V_RoM level during the fourth period T3 to T4 and the fifth period T4 to T5. Subsequently, the voltage level of the second node N2_n maintains the readout voltage V_RO level during the sixth period T5 to T6 and the seventh period T6 to T7.

The voltage level of the third node N3_n of FIG. 6 maintains the low level V_BL during the second period T1 to T2 to the fifth period T4 to T5. Subsequently, the voltage level of the third node N3_n may maintain the high level V_BH during the sixth period T5 to T6 and the seventh period T6 to T7.

The n-th emission line EL_n of FIG. 6 may output the first power voltage EL_H during the first period T0 to T1 to the third period T2 to T3. Subsequently, the n th emission line EL_n outputs a second power voltage EL_L during the fourth period T3 to T4 and the fifth period T4 to T5. Subsequently, the n th emission line EL_n may output the first power voltage EL_H during the sixth period T5 to T6 and the seventh period T6 to T7.

FIG. 7 is a circuit diagram illustrating an operation of a gate driving circuit in a section T1-T2 of FIG. 6. 1 to 7, the second period T1-T2 is a period in which the frame signal FR is at a low level FL, and a plurality of gate lines GL_n-1 and GL_n constituting a frame at the same time. , GL_n + 1) means a period in which all of the gate signals are at the low level CL. When the second section T1-T2 of FIG. 7 is described, lines indicated by dark lines indicate that signals having a high level are applied. In addition, the devices indicated by the dark lines represent the devices activated in the second section T1 -T2.

In the second period T1-T2, the first control signal CTRL_1 has a high level CH. Accordingly, the first transistor T1_n-1, the third transistor T3_n-1, and the fourth transistor T4_n-1 corresponding to the n-th gate line GL_n-1 are turned on. The second transistor T2_n-1 corresponding to the n-th gate line GL_n-1 and the fifth transistor T5_n-1 corresponding to the n-th gate line GL_n-1 are turned on. Is off.

In addition, the first transistor T1_n, the third transistor T3_n, and the fourth transistor T4_n corresponding to the nth gate line GL_n are turned on. The second transistor T2_n corresponding to the nth gate line GL_n and the fifth transistor T5_n corresponding to the nth gate line GL_n are turned off.

Similarly, the first transistor T1_n + 1, the third transistor T3_n + 1, and the fourth transistor T4_n + 1 corresponding to the n + 1 th gate line GL_n + 1 are turned on. The second transistor T2_n + 1 corresponding to the n + 1th gate line GL_n + 1 and the fifth transistor T5_n + 1 corresponding to the n + 1th gate line GL_n + 1 are turned on. -Off.

In the second period T1-T2, simultaneously programming the plurality of memory transistors MT_n-1, MT_n, MT_n + 1 corresponding to each of the plurality of gate lines GL_n-1, GL_n, GL_n + 1. A plurality of modulation voltages VM_n-1, VM_n, VM_n + 1 are respectively applied to the gates of the memory transistors. For example, the plurality of modulation voltages VM_n-1, VM_n, and VM_n + 1 have a first voltage level V_PGM.

In the second period T1-T2, when the plurality of memory transistors MT_n-1, MT_n, MT_n + 1 are programmed, the gates of the plurality of memory transistors MT_n-1, MT_n, MT_n + 1 − The drain characteristic VGS-IDS becomes the first state S1 in the second state S2 of FIG. 5.

In the second period T1-T2, after the memory transistors MT_n-1, MT_n, MT_n + 1 are programmed, the levels of the plurality of modulation voltages VM_n-1, VM_n, and VM_n + 1 are adjusted. The second voltage level V_RO is maintained at the first voltage level V_PGM. In this case, the first capacitors C1_n-1, C1_n, and C1_n + 1 corresponding to the plurality of gate lines GL_n-1, GL_n, and GL_n + 1 are charged to the second voltage level V_RO. For example, the second voltage level V_RO is lower than the first voltage level V_PGM and is a voltage that turns on the plurality of memory transistors MT_n-1, MT_n, MT_n + 1.

In the second period T1 -T2, the second capacitors C2_n-1, C2_n, and C2_n + 1 corresponding to each of the plurality of gate lines GL_n-1, GL_n, and GL_n + 1 have a third voltage level. It is charged to (V_IL). For example, the third voltage level V_IL may be lower than the second voltage level V_RO and may be a negative voltage level.

In the second period T1 -T2, the fourth transistors T4_n-1, T4_n, and T4_n + 1 corresponding to each of the plurality of gate lines GL_n-1, GL_n, and GL_n + 1 are connected to the ground voltage VSS. ) May be used to initialize the third nodes N3_n-1, N3_n, and N3_n + 1 corresponding to the plurality of gate lines GL_n-1, GL_n, and GL_n + 1.

In the second period T1-T2, the plurality of memory transistors MT_n-1, MT_n, MT_n + 1 are turned on at gates of the memory transistors MT_n-1, MT_n, MT_n + 1. A plurality of modulation voltages VM_n-1, VM_n, and VM_n + 1 having a second voltage level V_RO are applied. Accordingly, the plurality of emission control lines EL_n-1, EL_n, and EL_n + 1 output the first power voltage EL_H as emission control signals.

In the following drawings, for simplicity, the first to sixth transistors T1_n to T6_n, the first and second capacitors C1_n and C2_n, and the memory transistor MT_n corresponding to the nth gate line GL_n will be described. Next, a process of outputting the emission control signal to the nth emission line will be described.

FIG. 8 is a circuit diagram illustrating an operation of a gate driving circuit in a section T3-T4 of FIG. 6. When the fourth section T3-T4 of FIG. 8 is described, lines indicated by dark lines indicate that signals having a high level are applied. In addition, the devices indicated by the dark lines represent the devices activated in the fourth section T3-T4.

1 to 8, in the fourth period T3-T4, the gate signal of the n−1 th gate line GL_n−1 has a high level. Thus, the second transistor T2_n is turned on. When the second transistor T2_n is turned on, the remaining transistors are turned off.

Therefore, in the fourth period T3-T4, the first capacitor C1_n, the second capacitor C2_n, and the second transistor T2_n constitute one closed circuit. According to the law of charge conservation, the second voltage level V_R0 of the nth modulation voltage VM_n corresponding to the first capacitor C1_n is modulated to the fourth voltage level V_RoM. Similarly, the third voltage level V_IL corresponding to the second capacitor C2_n is modulated to the fourth voltage level V_RoM. In this case, the fourth voltage level V_RoM is lower than the second voltage level V_R0 and has a level higher than the third voltage level V_IL. Therefore, in the fourth period T3-T4, the memory transistor MT_n is turned off. Similarly, since the sixth transistor T6_n is also turned off, the emission control signal of the nth emission line EL_n may have a floating value that is not defined in the fourth period T3-T4. However, the fourth section T3-T4 corresponds to a very short time compared to the time of one frame, and the undefined light emission control signal of the section does not significantly affect the screen quality of the entire display device.

FIG. 9 is a circuit diagram illustrating an operation of a gate driving circuit in a section T4-T5 of FIG. 6. When the fifth section T4-T5 of FIG. 9 is described, the lines marked with dark lines indicate that signals having a high level are applied. In addition, the devices indicated by the dark lines represent the devices activated in the fifth section T4-T5.

1 to 9, the gate signal of the nth gate line GL_n has a high level in the fifth section T4-T5. Thus, the sixth transistor T6_n is turned on. In this case, since the n-th modulation voltage VM_n maintains the fourth voltage level V_RoM, the memory transistor MT_n maintains a turn-off state. Therefore, the sixth transistor T6_n may output the second power voltage EL_L as an emission control signal of the nth emission line EL_n.

FIG. 10 is a circuit diagram illustrating an operation of a gate driving circuit in a section T5-T6 of FIG. 6. When the sixth periods T5 to T6 of FIG. 10 are described, lines indicated by dark lines indicate that signals having a high level are applied. In addition, the devices indicated by the dark lines represent the devices activated in the sixth periods T5 to T6.

1 to 10, in the sixth period T5 to T6, the gate signal of the n + 1 th gate line GL_n + 1 has a high level.

As described above, when the first capacitor C1_n is charged to the second voltage level V_R0, the voltage level of the second control signal CTRL_2 maintains the boost level V_BST.

When the high level gate signal is applied to the n + 1 th gate line GL_n + 1 as shown in FIG. 10, the fifth transistor T5_n is turned on and has a second control signal having a boost level V_BST. CTRL_2 is applied to the third node N3_n. Accordingly, the charging voltage of the first capacitor C1_n and the second capacitor C2_n is increased by the second control signal CTRL_2 having the boost level V_BST. Therefore, the n th modulation voltage VM_n may be adjusted to be the voltage level to have the second voltage level V_RO again at the fourth voltage level V_RoM.

In the sixth period T5 to T6, the nth modulation voltage VM_n again has a second voltage level V_RO. Thus, the memory transistor MT_n is turned on. Therefore, the memory transistor MT_n may again output the first power voltage EL_H as an emission control signal of the nth emission line EL_n.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims of the present invention.

100: timing control circuit 200 gate driving circuit
300: data driving circuit 1000: organic light emitting display device

Claims

a gate including an i-th (where i is a natural number of 2 or more) gate line and an i-th modulation circuit connected to an i + 1 th gate line, an i-th gate line, and an i-th line selection circuit connected to an i-th light emitting line In the driving circuit,
The i-th modulation circuit outputs an i-th modulation voltage to the i-th line selection circuit based on the received first to third control signals, and includes first to fifth transistors and first and second capacitors. ,
And the i-th line select circuit includes a memory transistor that is turned on or off according to the level of the received i-th modulation voltage.

The method of claim 1,
The i-th modulation circuit,
The intersection of the other end of the first transistor and one end of the second transistor is a first node,
The intersection of the other end of the second transistor and the other end of the third transistor is a second node,
The intersection of the other end of the fourth transistor and the other end of the fifth transistor is a third node,
The first capacitor is connected between the first node and the third node,
And the second capacitor is connected between the second node and the third node.

The method of claim 2,
A gate of the first transistor receives the first control signal, one end receives the second control signal, and the other end is connected to the first node,
A gate of the second transistor is connected with the i-th gate line, one end is connected with the first node, and the other end is connected with the second node,
A gate of the third transistor receives the first control signal, one end receives the third control signal, and the other end is connected to the second node,
A gate of the fourth transistor receives the first control signal, one end of which is connected to a ground voltage, the other end of which is connected to the third node,
And a gate of the fifth transistor is connected to the i + 1 th gate line, one end of which receives the second control signal, and the other end of which is connected to the third node.

The method of claim 3, wherein
And the first to fifth transistors are oxide thin-film transistors, and the capacitance of the second capacitor is greater than the capacitance of the first capacitor.

The method of claim 2,
The i-th line select circuit
Further comprising a sixth transistor,
A gate of the memory transistor receives the i-th modulation voltage, one end thereof is connected to a first power supply voltage, and the other end thereof is connected to the i-th light emitting line,
And a gate of the sixth transistor is connected to the i-th gate line, one end of which is connected to a second power supply voltage having a level lower than the first power supply voltage, and the other end of the sixth transistor is connected to the i-th light emitting line.

The method of claim 5,
And the memory transistor has a non-volatile data retention characteristic, and the sixth transistor is an oxide thin film transistor.

The method of claim 5,
While the first control signal maintains a high level,
And a second control signal having a first voltage level for programming said memory transistor is applied to a gate of said memory transistor at said i < th > modulation voltage.

The method of claim 7, wherein
After the memory transistor is programmed, the level of the i-th modulation voltage is maintained at a second voltage level,
The first capacitor is charged to the second voltage level,
The second voltage level is lower than the first voltage level, and turns on the memory transistor.

The method of claim 8,
The second capacitor is charged by a third control signal having a third voltage level,
And the third voltage level is lower than the second voltage level and is a negative voltage level.

The method of claim 9,
When the high level gate signal is transmitted to the i-1 th gate line, the second transistor is turned on.
The level of the voltage of the first capacitor and the level of the voltage of the second capacitor are adjusted to have a fourth voltage level,
The fourth voltage level is lower than the second voltage level, has a level higher than the third voltage level, and turns off the memory transistor.

The method of claim 10,
When the high level gate signal is transmitted to the i-th gate line, the sixth transistor is turned on,
And the sixth transistor outputs the second power supply voltage to the i-th light emitting line.

The method of claim 11,
After the level of the voltage of the first capacitor is adjusted to the second voltage level, the voltage level of the second control signal is maintained at the boost level,
The fifth transistor is turned on while the high level gate signal is applied to the i + 1th gate line, and the second control signal having the boost level is applied to the third node.

The method of claim 12,
And by the second control signal having the boost level, the level of the voltage of the first capacitor and the level of the voltage of the second capacitor are adjusted to have the second voltage level.

The method of claim 10,
And the level of the voltage of the first capacitor and the level of the voltage of the second capacitor are adjusted to have the fourth voltage level through charge sharing.

A gate driving circuit providing gate signals to the gate lines and providing emission control signals to the light emitting lines;
A data driver circuit for providing data signals to data lines; And
An organic light emitting display panel including a plurality of pixels;
The gate driving circuit includes an i-th modulation circuit (i, wherein i is a natural number of two or more) and an i-th modulation circuit connected to an i + 1 th gate line, an i-th gate line, and an i-th line connected to an i-th light emitting line. Including circuits,
The i-th modulation circuit outputs an i-th modulation voltage to the i-th line selection circuit based on the received first to third control signals,
And the i-th line selection circuit includes a memory transistor turned on or off according to the received level of the i-th modulation voltage.

Programming the plurality of memory transistors by providing modulation voltages having a first voltage level to gates of the plurality of memory transistors;
Turning on the plurality of memory transistors by adjusting the modulation voltages to a second voltage level lower than the first voltage level;
When a high level gate signal is applied to the i-1 < th > (where i is a natural number of 2 or more), turning the i < th > memory transistors by adjusting the i < th > modulation voltage to a third voltage level lower than the second voltage level. -Off; And
When the high level gate signal is applied to the i + 1 th gate line, the i th memory transistor is adjusted by adjusting the i th modulation voltage to the second voltage level based on a voltage level of the i + 1 th gate line. And turning on the gate driving circuit.

The method of claim 16,
The programming of the plurality of memory transistors may include:
Turning on the plurality of first transistors based on the first control signal; And
Input signals of the plurality of first transistors include receiving a second control signal,
Gates of the plurality of memory transistors are connected to output electrodes of the plurality of first transistors, the output electrode of the first transistor is connected to an input electrode of a second transistor, and the i-th gate line is an i-th gate. A method of driving a gate driving circuit connected to the gate of a second transistor.

The method of claim 17,
Turning on the plurality of memory transistors,
Adjusting a level of a first capacitor to the second voltage level based on the first and second control signals; And
Adjusting the level of the second capacitor to a negative voltage level based on the first control signal and the third control signal,
One end of the first capacitor is connected to the input electrode of the second transistor, one end of the second capacitor is connected to the output electrode of the second transistor, and the other end of the first capacitor is connected to the second capacitor. A driving method of a gate driving circuit connected to the other end.

The method of claim 18,
Turning off the i-th memory transistor,
Adjusting the level of the first capacitor and the level of the second capacitor to the third voltage level through charge sharing based on the high level gate signal applied to the i-1th gate line; The method of driving the circuit.

The method of claim 19,
Turning on the i-th memory transistor,
And maintaining a level of the first capacitor and a level of the second capacitor at a boost level based on the high level gate signal applied to the i + 1th gate line.