KR102016073B1 - Organic light emitting diode display device and method of fabricating the same - Google Patents

Abstract

The present invention relates to an OLED display device and a method of manufacturing the OLED display device capable of stabilizing the power supply by minimizing the voltage drop of the power supply line without reducing the aperture ratio. The first and second auxiliary lines overlapping the power supply line to form first and second auxiliary capacitors, respectively, and connected to any one of the first and second auxiliary lines to adjust the threshold voltage Vth of the driving thin film transistor. And a gate electrode for adjusting Vth.

Description

Organic light emitting diode display and manufacturing method {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display device, and more particularly, to an OLED display device capable of displaying an image having uniform luminance by stabilizing a power line and a method of manufacturing the same.

Recently, a flat panel display including a liquid crystal display (LCD), an OLED display, a plasma display panel (PDP), etc. is mainly used as an image display device.

The OLED display is a self-luminous device that emits an organic light emitting layer by recombination of electrons and holes, and is expected to be a next generation display device because of its high brightness, low driving voltage, and ultra-thin film. In addition, the OLED display is a transparent display that can display information on both sides of the display by forming a cathode and an anode as a transparent electrode, each pixel consisting of OLED, a pixel circuit for driving the OLED and a transparent portion to emit light to both sides of the display Can be applied.

Each of the plurality of pixels constituting the OLED display device includes an OLED composed of an organic light emitting layer between an anode and a cathode, and a pixel circuit driving the OLED independently. Pixel circuits can be classified into voltage and current types. Voltage-type pixel circuits are more likely to be used as pixel circuits for OLED TVs because external drive circuits are simpler than current-type pixel circuits and suitable for high-speed operation.

The voltage pixel circuit mainly includes a switching thin film transistor (hereinafter, referred to as TFT), a capacitor, and a driving TFT. The switching TFT charges the capacitor with a voltage corresponding to the data signal in response to the scan pulse, and the driving TFT controls the magnitude of the current supplied from the power supply (VDD) line to the OLED according to the magnitude of the voltage charged in the capacitor. Adjust the amount of light emitted. The amount of light emitted by the OLED is proportional to the current supplied from the driving TFT.

In the OLED display, the power supply (VDD) line supplies current to the driving TFTs of all the pixel circuits. Accordingly, when a large amount of current is consumed by the driving TFTs of the pixel circuit, there is a limit on the amount of current that can be instantaneously supplied from the power supply VDD line, so that the voltage drop of the power supply VDD line increases, resulting in uneven current supply depending on the pixel position. There is a problem that the luminance non-uniformity occurs. On the other hand, when the wiring width is increased to reduce the voltage drop of the power supply line, there is a problem in that the pixel aperture ratio decreases.

In addition, there is a problem that the threshold voltage Vth of the driving TFT of each pixel is changed over time, resulting in a decrease in life due to a decrease in luminance.

SUMMARY OF THE INVENTION The present invention has been made to solve a conventional problem, and an object of the present invention is to provide an OLED display device and a method of manufacturing the same, which can stabilize a power supply by minimizing a voltage drop of a power line without reducing an aperture ratio.

Another object of the present invention is to provide an OLED display device and a method of manufacturing the same, which can compensate for the reduction of the threshold voltage Vth of the driving TFT over time.

In order to solve the above problems, the OLED display device according to the embodiment of the present invention includes an OLED element, and a driving TFT connected to the gate line and the data line to drive the OLED element independently and control the current supplied to the OLED element. A pixel circuit; A power supply line for supplying high potential power to the OLED element via the pixel circuit; At least a portion of the first insulating line overlapping the power line with the upper insulating layer interposed therebetween to form a first auxiliary capacitor; At least one of a second auxiliary line forming a second auxiliary capacitor; The pixel circuit further includes a Vth adjusting gate electrode connected to either one of the first and second auxiliary lines to adjust the threshold voltage (hereinafter, Vth) of the driving TFT.

The first and second auxiliary lines may be supplied with different voltages from the power supply line, and the first and second auxiliary lines may be supplied with the same or different voltages. The first and second auxiliary lines may be formed independently or not connected to each other through contact holes penetrating the upper and lower insulating layers.

The power supply line is positioned between two first and second pixel circuits adjacent in the horizontal direction and commonly connected to the driving TFTs of the first and second pixel circuits; The Vth adjustment gate electrode extends from the power supply line to both sides and overlaps the gate electrode of the driving TFT and the active layer in each of the first and second pixel circuits, respectively.

The gate electrode of the driving TFT overlaps with the active layer interposed therebetween; The gate electrode for adjusting Vth overlaps with an active layer and a passivation layer thereon.

 The power supply line is formed of the same source / drain metal layer as the source electrode and the drain electrode of the driving TFT, and is connected to any one of the source electrode and the drain electrode of the driving TFT; The other one of the source electrode and the drain electrode of the driving TFT is formed on the passivation layer and connected to the pixel electrode serving as one electrode of the OLED element through the contact hole. The first auxiliary line may be formed of the same gate metal layer as the gate electrode of the driving TFT, and may overlap with the power supply line and the gate insulating layer interposed therebetween. The second auxiliary line is formed of the same transparent conductive layer as the pixel electrode and overlaps with the power line and the passivation layer interposed therebetween, or a second source formed with the second passivation layer between the power line and the passivation layer interposed therebetween. It may be formed of a / drain metal layer and overlapped with a power line and a second passivation layer interposed therebetween, or may be formed of a transparent conductive layer and a second source / drain metal layer.

The gate electrode of the driving TFT overlaps with the active layer interposed therebetween; The gate electrode for adjusting Vth may also serve as a light shielding pattern that overlaps an active layer with a buffer layer below it to block light incident to the active layer.

The power supply line is formed of the same source / drain metal layer as the source electrode and the drain electrode of the driving TFT, and is connected to any one of the source electrode and the drain electrode of the driving TFT; The other one of the source electrode and the drain electrode of the driving TFT is formed on the passivation layer thereon and connected through the contact hole with the pixel electrode serving as one electrode of the OLED element. The first auxiliary line may be formed of the same light shielding metal layer as the Vth control gate electrode, and may overlap each other with a plurality of insulating layers including the power line, the buffer layer, and the gate insulating layer interposed therebetween. The second auxiliary line may be formed of the same conductive layer as the pixel electrode, and overlap the power line and the passivation layer.

An OLED manufacturing method according to an embodiment of the present invention includes the steps of forming a power source line with a source electrode and a drain electrode of a driving TFT as a source / drain metal layer; A first auxiliary line overlapping the power line with at least a portion of the power line interposed therebetween to form a first auxiliary capacitor; and a second auxiliary line with at least a portion of the power line overlapping the power line with the lower insulating film Forming at least one of the second auxiliary lines forming a capacitor; Forming a Vth adjusting gate electrode connected to either one of the first and second auxiliary lines to adjust the Vth of the driving TFT; The first and second auxiliary lines may be formed independently or not connected to each other through contact holes penetrating the upper and lower insulating layers.

An OLED manufacturing method according to an embodiment of the present invention includes forming a gate electrode and a first auxiliary line of a driving TFT on a substrate as a gate metal layer; Forming a gate insulating film on the gate metal layer; Forming an active layer of a driving TFT on the gate insulating film; Forming a source electrode and a drain electrode of the driving TFT to be connected with the active layer, and a power supply line as a source / drain metal layer; Forming a passivation layer on the source / drain metal layer and forming a contact hole through at least the passivation layer; And forming a second auxiliary line and a Vth adjusting gate electrode as a transparent conductive layer together with the pixel electrode connected to the driving TFT through the contact hole.

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According to another aspect of the present invention, there is provided a method of manufacturing an OLED, comprising: forming a gate electrode for adjusting Vth and a first auxiliary line as a light blocking metal layer on a substrate; Forming a buffer layer on the light shielding metal layer; Forming an active layer of a driving TFT on the buffer layer; Forming a gate insulating film on the active layer; Forming a gate electrode of the driving TFT on the gate insulating film; Forming an interlayer insulating film on the gate electrode and forming a source contact hole and a drain contact hole exposing the source region and the drain region of the active layer; Forming a power source line as a source / drain metal layer together with a source electrode and a drain electrode of a driving TFT respectively connected to the source region and the drain region of the active layer through the source contact hole and the drain contact hole on the interlayer insulating film; Forming a passivation layer on the source / drain metal layer and forming a contact hole through at least the passivation layer; And forming a second auxiliary line as a transparent conductive layer together with the pixel electrode connected to the driving TFT through the contact hole.

The OLED display device and the method of manufacturing the same according to the present invention form a top and bottom auxiliary capacitor by adding a pair of auxiliary lines that overlap each of the top and bottom with the power line and the insulating film interposed therebetween to compensate for the voltage drop of the power line. Even if the driving current increases, the power line can supply stable power to minimize luminance unevenness.

In addition, the OLED display device and a method of manufacturing the same according to the present invention can be used as an additional gate electrode for controlling the threshold voltage by overlapping one of a pair of auxiliary lines overlapping the power line with the driving TFT of each pixel. As a result, the luminance reduction can be minimized by compensating the threshold voltage of the driving TFT that is varied accordingly, thereby increasing the lifetime.

1 is an equivalent circuit diagram of a pixel circuit of an OLED display according to an exemplary embodiment of the present invention.
2 is a plan view of a pixel of an OLED display according to an exemplary embodiment of the present invention.
3 is a cross-sectional view of one pixel circuit according to the first embodiment of the present invention.
4 is a flowchart illustrating a method of manufacturing the pixel circuit shown in FIG. 3.
5 is a cross-sectional view of one pixel circuit according to a second embodiment of the present invention.
FIG. 6 is a flowchart illustrating a method of manufacturing the pixel circuit shown in FIG. 5.
FIG. 7 is a graph showing that the threshold voltage Vth of the driving TFT is adjusted according to the voltage of the second gate electrode in the OLED display according to the exemplary embodiment of the present invention.

Hereinafter, with reference to Figures 1 to 7 attached to a preferred embodiment of the present invention will be described in detail.

1 is an equivalent circuit diagram illustrating two representative pixels of an OLED display according to an exemplary embodiment of the present invention.

In the OLED display shown in FIG. 1, each pixel includes an OLED and a pixel circuit PC including at least a switching TFT ST and a driving TFT DT and a storage capacitor Cst to independently drive the OLED. do.

The OLED display device includes a gate line GL for controlling the switching TFT ST of the pixel circuit PC, a data line DL for supplying a data signal Vdata to the switching TFT ST, and a driving TFT DT. ) Is provided with a first power supply line (PL1) for supplying a high potential power (ELVDD), and a second power supply line (PL2) for supplying a low potential power (ELVSS) to the cathode of the OLED. The first power line PL1 is positioned between two adjacent pixel circuits PC in the horizontal direction and commonly connected to two adjacent pixel circuits PC. The two pixel circuits PC, which share one first power line PL1 and are adjacent in the horizontal direction, have a symmetrical structure with respect to the first power line PL1 between two adjacent data lines DL1.

In addition, the OLED display device forms the first power line PL1 and the first and second auxiliary capacitors Cp1 and Cp2 to stabilize the high potential power ELVDD supplied to the first power line PL1, respectively. First and second auxiliary lines AL1 and AL2 are further provided.

In addition, the OLED display device is connected to any one of the first and second auxiliary lines AL1 and AL2 and overlaps with the driving TFT DT of each pixel circuit PC, so that the first gate electrode of the driving TFT DT ( A second gate electrode G22 is formed to form a double gate structure with the G21 to control the threshold voltage Vth of the driving TFT DT.

The OLED is connected in series with the driving TFT DT between the first power supply line PL1 and the second power supply line PL2. The OLED includes an anode connected with the driving TFT DT, a cathode connected with the second power supply line PL2, and a light emitting layer between the anode and the cathode. The light emitting layer includes an electron injection layer, an electron transport layer, an organic light emitting layer, a hole transport layer, and a hole injection layer sequentially stacked between the cathode and the anode. When a positive bias is applied between the anode and the cathode, electrons from the cathode are supplied to the organic light emitting layer via the electron injection layer and the electron transport layer, and holes from the anode are supplied to the organic light emitting layer via the hole injection layer and the hole transport layer. do. Accordingly, in the organic light emitting layer, energy generated by recombination of supplied electrons and holes emits fluorescent or phosphorescent material, thereby generating light in proportion to the amount of current.

In the switching TFT ST, the gate electrode G1 is connected to the gate line GL, the source electrode S1 is connected to the data line DL, and the drain TFT is drained to the first gate electrode G21 of the driving TFT DT. The electrode D1 is connected. The source electrode S1 and the drain electrode D1 may be reversed in accordance with the current direction of the switching TFT ST. The switching TFT ST supplies the data signal Vdata of the data line DL to the first gate electrode G21 of the driving TFT DT in response to the scan signal of the gate line GL.

The storage capacitor Cst is connected between the first gate electrode G21 and the source electrode S2 of the driving TFT DT. The storage capacitor Cst charges the data signal Vdata from the switching TFT ST and supplies the driving signal Vgs to the first gate electrode G21 of the driving TFT DT.

In the driving TFT DT, the first gate electrode G21 is connected to the drain electrode D1 of the switching TFT ST, the source electrode S2 is connected to one electrode of the OLED, and the high potential power line PL1 is connected. The drain electrode D2 is connected to it. The source electrode S2 and the drain electrode D2 may be reversed according to the current direction of the driving TFT DT. The driving TFT DT supplies the OLED with a current proportional to the driving voltage Vgs supplied from the storage capacitor Cst to emit the OLED.

In this case, the first and second auxiliary lines AL1 and AL2 apply the auxiliary voltages AV1 and AV2 different from the high potential power ELVDD to the first power line PL1 and the first and second auxiliary capacitors Cp1. By forming Cp2, the voltage drop of the high potential power ELVDD supplied to the first power line PL1 is compensated to maintain the high potential power ELVDD stably. The auxiliary voltages AV1 and AV2 supplied to the first and second auxiliary lines AL1 and AL2 may be set to be the same or different from each other. The first and second auxiliary lines AL1 and AL2 may be connected to each other.

Meanwhile, the second gate electrode G22 of the driving TFT DT is connected to one of the first and second auxiliary lines AL1 and AL2, and the first gate electrode G21 and the semiconductor layer of the driving TFT DT are connected to each other. By overlapping with each other, the driving TFT DT has a double gate structure. Compensation voltage for the threshold voltage Vth through any one of the first and second auxiliary lines AL1 and AL2 when the threshold voltage Vth of the driving TFT DT varies due to continuous bias stress over time. May be supplied to the second gate electrode G22 to compensate for the threshold voltage Vth of the driving TFT DT.

FIG. 2 is a plan view of the pixel circuit shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line II ′ of the pixel circuit according to the first embodiment shown in FIG. 2.

Referring to FIG. 2, one first power line PL1 is formed between two adjacent data lines DL in a horizontal direction, and the gate line GL1 is formed of the data line DL and the first power line PL1. Is formed to intersect.

The first and second auxiliary lines AL1 and AL2 are formed to overlap the first power line PL1 with an insulating layer therebetween to form the first and second auxiliary capacitors Cp1 and Cp2, respectively.

The switching TFT ST includes the gate electrode G1 connected to the gate line GL, the active layer ACT1 overlapping the gate electrode G1 and the gate insulating film GI, and the data line DL. And a source electrode S1 connected to one side of the active layer ACT1, and a drain electrode D1 connected to the other side of the active layer ACT1 while facing the source electrode S1 and a channel region therebetween. .

The driving TFT DT includes a first gate electrode G21 and a first gate electrode connected via the drain electrode D1 of the switching TFT ST, the contact holes H1 and H2 and the contact electrode CE. The active layer ACT2 overlapped with the G21 and the gate insulating layer GI interposed therebetween, the drain electrode D1 connected to one side of the first power line PL1 and the active layer ACT2, and the drain electrode D1. ) And the channel region facing each other, the active layer (S2) connected to the other side of the active layer ACT2 and the second auxiliary line AL2 and connected to the passivation layer (PAS). A second gate electrode G22 overlapping with the ACT2 is provided. Driving through the contact hole H1 (FIG. 2), which exposes a part of the drain electrode D1 of the switching TFT ST through the passivation layer PAS, and through the gate insulating layer GI and the passivation layer PAS. The switching TFT ST is disposed through the contact hole H2 (FIG. 2) exposing a part of the first gate electrode G21 of the TFT DT and the contact electrode CE (FIG. 2) via the contact holes H1 and H2. The drain electrode D1 of FIG. 7 and the first gate electrode G21 of the driving TFT DT are connected to each other. The source electrode S2 of the driving TFT DT is connected to the pixel electrode PXL serving as an anode of the OLED through the contact hole H3 penetrating through the passivation layer PAS.

The storage capacitor Cst is formed by overlapping the drain electrode D1 of the switching TFT ST and the first gate electrode G21 of the driving TFT DT with the gate insulating layer GI interposed therebetween.

2 and 3, the first power line PL1 is formed of the same source / drain metal layer as the source electrode S2 and the drain electrode D2 of the driving TFT DT to drain the driving TFT DT. It is directly connected to the electrode D2.

The first auxiliary line AL1 is formed of the same gate metal layer as the first gate electrode G21 of the driving TFT DT so that the first power source has the gate insulating layer GI therebetween under the first power line PL1. The first auxiliary capacitor Cp1 is formed by overlapping the line PL1.

 The second auxiliary line AL2 is formed of the same conductive layer as the pixel electrode PXL, for example, a transparent electrode layer, and is formed to have at least one passivation film PAS interposed therebetween on the first power line PL1. The second auxiliary capacitor Cp2 is formed by overlapping the first power line PL1. The first auxiliary line AL2 is directly connected to the second gate electrode G22 of the driving TFT DT.

In order to achieve the purpose of the auxiliary capacitors Cp1 and Cp2 for stabilizing the high potential power ELVDD supplied to the first power line PL1, the first and second auxiliary lines AL1 and AL2 and the first power line It is preferable that the overlap area of PL1 is 10% or more inside the pixel array.

The first and second auxiliary lines AL1 and AL2 may be connected to each other through a contact hole (not shown) passing through the gate insulating layer GI and the passivation layer PAS, and the contact holes may be formed in the pixel array or It may be formed so as not to overlap with the first power line PL1 from the outside.

Although only the cross-sectional structure of the driving TFT DT is shown in FIG. 3, the switching TFT ST also uses an amorphous silicon or oxide semiconductor as the active layers ACT1 and ACT2, similarly to the driving TFT DT, and the active layer. The bottom gate structure has gate electrodes G1 and G21 positioned under the ACT1 and ACT2, respectively. An etch stopper ES is further formed on the active layers ACT1 and ACT2 to prevent etching of the active layers ACT1 and ACT2. The oxide semiconductor layer 114 is formed of an oxide semiconductor including at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, and Zr.

In FIG. 2, the data line DL is formed of the same source / drain metal layer as the first power line PL1, the source electrodes S1 and S2, and the drain electrodes D1 and D2, and the gate line GL1 is formed in the first line. It is formed of the same gate metal layer as the auxiliary line AL1 and the gate electrodes G1 and G21, and the second auxiliary line AL2 and the second gate electrode G22 are the same as the pixel electrode PXL and the contact electrode CE. It is formed of a transparent electrode layer.

Meanwhile, a second source / drain metal layer (not shown) and a second passivation layer (not shown) may be further formed between the passivation layer PAS and the pixel electrode PXL as needed. In this case, the second auxiliary line AL2 and the second gate electrode G22 are formed of a second source / drain metal layer (not shown) between the passivation layer PAS and the second passivation layer (not shown). Can be. In addition, the second auxiliary line AL2 may be formed of a second source / drain metal layer and a transparent electrode layer.

4 is a flowchart showing step by step a method of manufacturing the pixel circuit shown in FIGS. 2 and 3.

In operation S2, a first electrode group including a gate line GL, a gate electrode G1 and G21, and a first auxiliary line AL1 is formed on the substrate SUB. The first electrode group is formed by forming a gate metal layer on a substrate SUB through a deposition method such as a sputtering method, and then patterning the gate metal layer by a photolithography process and an etching process using a mask. The gate metal layer is used as a metal material, such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, Mo-Ti alloy and the like.

In step 4 (S4), a gate insulating layer GI covering the first electrode group is formed on the substrate SUB through a deposition process such as plasma enhanced chemical vapor deposition (PECVD). An inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the gate insulating film GI.

In step 6 (S6), active layers ACT1 and ACT2 are formed on the gate insulating layer GI. The active layers ACT1 and ACT2 are formed by forming a semiconductor layer on the gate insulating layer GI through a deposition process such as PECVD, and then patterning the semiconductor layer through a photolithography process and an etching process using a mask. Amorphous silicon is used as the semiconductor layer; It is formed of an oxide semiconductor material comprising at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, Zr.

In step 8 (S8), the etch stopper ES is formed on the active layers ACT1 and ACT2. The etch stopper ES is formed on the active layers ACT1 and ACT2 by a deposition process such as PECVD, and then the etch stopper layer is patterned through a photolithography process and an etching process using a mask using a mask. Is formed. As the etch stopper layer, an inorganic insulating material such as silicon oxide (SiOx) is used.

In step 10 (S10), the data line DL, the source electrodes S1 and S2, and the drain electrodes D1 and D2 are formed on the gate insulating layer GI on which the etch stopper ES and the active layers ACT1 and ACT3 are formed. And a second electrode group including the first power line PL1. The second electrode group is formed by forming a source / drain metal layer through a deposition method such as a sputtering method, and then patterning the source / drain metal layer by a photolithography process and an etching process using a mask. As the source / drain metal layer, titanium (Ti), tungsten (W), aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), or the like is used.

In operation 12 (S12), a passivation layer PAS having contact holes H1, H2, and H3 is formed on the gate insulating layer GI on which the second electrode group is formed. The passivation layer PAS is formed by depositing an organic insulating material or an inorganic insulating material on the gate insulating film GI, and then patterning them through a photolithography process and an etching process using a mask to penetrate the passivation layer PAS and to form the gate insulating film. Contact holes H1, H2, and H3 selectively penetrating the GI are formed. As the passivation layer PAS, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used, or an organic insulating material such as acrylic resin or the like is used. The contact holes H1 and H3 are formed to pass through the passivation layer PAS, and the contact holes H2 are formed to pass through the passivation layer PAS and the gate insulating layer GI.

In operation 14 (S14), a third electrode group including the pixel electrode PXL, the second auxiliary line AL2, the second gate electrode G22, and the contact electrode CE is formed on the passivation layer PAS. do. The third electrode group is formed by forming a transparent electrode layer through a deposition method such as a sputtering method, and then patterning the transparent electrode layer by a photolithography process and an etching process using a mask. As the transparent electrode layer, metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and ZnO are mainly used. In addition, the transparent electrode layer may have a multilayer structure in which a transmissive metal thin film and the metal oxide layer are alternately stacked.

Meanwhile, a second source / drain metal layer (not shown) and a second passivation layer (not shown) may be further formed between the passivation layer PAS and the pixel electrode PXL as needed. In this case, the second auxiliary line AL2 and the second gate electrode G22 are formed of a second source / drain metal layer (not shown) between the passivation layer PAS and the second passivation layer (not shown). Can be. In addition, the second auxiliary line AL2 may be formed of a second source / drain metal layer and a transparent electrode layer.

5 is a cross-sectional view taken along line II ′ of the pixel circuit according to the second exemplary embodiment of the present invention.

The pixel circuit shown in FIG. 5 shows a case where the driving TFT DT is formed in a top gate structure using polysilicon as an active layer, and the switching TFT ST not shown is the same as the driving TFT DT. It is formed into a top gate structure. 5 is identical to the plan view of FIG. 2, and thus descriptions of redundant configurations will be omitted.

The driving TFT DT includes a first gate electrode G21 on the gate insulating film GI, an active layer ACT2 formed under the first gate electrode G21 and the gate insulating film GI, and an interlayer insulating film. A source electrode connected to the source region SA and the drain region DA of the active layer ACT, respectively, through the source contact hole SH and the drain contact hole DH penetrating the IL and the gate insulating layer GI. (S2) and drain electrode D2, and second gate electrode G22 superimposed under active layer ACT2 with buffer film BF interposed therebetween. The second gate electrode G22 also serves as a light blocking pattern to block external light from being incident on the active layer ACT2 to prevent light leakage current. The active layer ACT2 includes a source region SA and a drain region DA doped with impurities and a channel region CA without doping impurities, and includes a channel region CA and a source and A light drop drain (LDD) region (not shown) in which n− impurities are injected may be further provided between the drain regions SA and SD.

The drain electrode D2 of the driving TFT DT is directly connected to the first power line PL1 formed on the same layer, and the source electrode S2 is connected through the contact hole H3 passing through the passivation layer PAS. A contact electrode H1 and H2 (FIG. 2) and a contact electrode connected to the pixel electrode PXL1 and passing through the passivation layer PAS and selectively passing through the interlayer insulating layer IL. The first auxiliary line is connected to the drain electrode D1 of the switching TFT ST of FIG. 2 through CE; FIG. 2, and the second gate electrode G22 is formed in the same layer on the substrate SUB. It is directly connected to (AL1).

The first auxiliary line AL1 formed on the substrate SUB overlaps the first power line PL1 with the buffer layer BF, the gate insulating layer GI, and the interlayer insulating layer IL interposed therebetween, so as to overlap the first auxiliary capacitor ( Cp1) is formed. The first auxiliary line AL1 and the second gate electrode G22 are formed of the same layer as a light blocking pattern (not shown) formed under the active layer ACT1 of the source TFT ST (FIG. 2).

The second auxiliary line AL2 formed on the passivation layer PAS overlaps the first power line PL1 with the passivation layer PAS therebetween to form a second auxiliary capacitor Cp2.

A gate line GL (FIG. 2) is formed on the gate insulating layer GI together with the first gate electrode G21, and a data line DL (FIG. 2) is formed together with the source electrode S2 and the drain electrode D2. It is formed on the interlayer insulating film IL.

The first and second auxiliary lines AL1 and AL2 may be connected to each other through a contact hole (not shown) passing through the passivation layer PAS to the buffer layer BF, and the contact holes may be formed in the pixel array or It may be formed so as not to overlap with the first power line PL1 from the outside.

In FIG. 5, only the cross-sectional structure of the driving TFT DT is illustrated, but the switching TFT ST also uses the driving TFT DT and the polysilicon layer as the active layer ACT1, respectively, on the upper portion of the active layer ACT1. Each of the gate electrodes G1 has a top gate structure in which the gate electrodes G1 are positioned.

6 is a flowchart illustrating a method of manufacturing the pixel circuit shown in FIG. 5 step by step.

In operation 22 (S22), a first electrode group including a light blocking pattern (not shown), a first auxiliary line AL1, and a second gate electrode G22 is formed on the substrate SUB. The first electrode group is formed by forming a light shielding metal layer on a substrate SUB through a deposition method such as a sputtering method, and then patterning the light shielding metal layer by a photolithography process and an etching process using a mask. As the light blocking metal layer, a metal material such as chromium (Cr), molybdenum (Mo), or the like having a relatively low reflectance is used.

In operation S24, a buffer film BF covering the first electrode group is formed on the substrate SUB through a deposition process such as plasma enhanced chemical vapor deposition (PECVD). An inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the buffer film GI.

In operation 26 (S26), active layers ACT1 and ACT2 are formed on the buffer film BF. The active layers ACT1 and ACT2 form an amorphous silicon layer on the buffer film BF through a deposition process such as PECVD, and then crystallize by a laser / heat treatment process to convert into a poly-silicon layer, and then mask the poly-silicon. It is formed by patterning in a photolithography process and an etching process using.

In step 28 (S28), a gate insulating film GI covering the active layers ACT1 and ACT2 is formed on the buffer film BF through a deposition process such as PECVD. An inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the gate insulating film GI.

In operation 30 (S30), a second electrode group including a gate line GL and gate electrodes G1 and G21 is formed on the gate insulating layer GI. The second electrode group is formed by forming a gate metal layer on the gate insulating layer GI through a deposition process such as sputtering, and then patterning the gate metal layer by a photolithography process and an etching process using a mask. The gate metal layer is used as a metal material, such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, Mo-Ti alloy and the like. Next, n + impurities are implanted into each of the active layers ACT1 and ACT2 using the gate electrodes G1 and G21 as masks, and the source regions facing each other with the channel region CA interposed therebetween in the active layers ACT1 and ACT2. SA and the drain region DA are formed.

In step 32 (S32), an interlayer insulating film IL covering the second electrode group on the gate insulating film GI is formed through a deposition process such as PECVD, and an interlayer insulating film IL by a photolithography process and an etching process using a mask. ) Is patterned to form a source contact hole SH and a drain contact hole DH exposing the source region SA and the drain region DA of the active layers ACT1 and ACT2, respectively. As the interlayer insulating film IL, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

In operation 34 (S34), a third electrode group including the data line DL, the source electrodes S1 and S2, the drain electrodes D1 and D2, and the first power line PL1 is formed on the interlayer insulating layer IL. Is formed. The third electrode group is formed by forming a source / drain metal layer through a deposition method such as a sputtering method, and then patterning the source / drain metal layer by a photolithography process and an etching process using a mask. As the source / drain metal layer, titanium (Ti), tungsten (W), aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), or the like is used.

In operation S36, a passivation layer PAS having contact holes H1, H2, and H3 is formed on the interlayer insulating layer IL on which the third electrode group is formed. The passivation layer (PAS) is an entire surface of the organic insulating material or inorganic insulating material deposited on the interlayer insulating film (IL), and then patterned by a photolithography process and an etching process using a mask to penetrate the passivation layer (PAS) and the interlayer insulating film Contact holes H1, H2, and H3 penetrating the IL and the gate insulating layer GI are formed. As the passivation layer PAS, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used, or an organic insulating material such as acrylic resin or the like is used. The contact holes H1 and H3 are formed to penetrate the passivation layer PAS, and the contact holes H2 are formed to penetrate from the passivation layer PAS to the gate insulating layer GI.

In operation S38, a third electrode group including the pixel electrode PXL, the second auxiliary line AL2, and the contact electrode CE is formed on the passivation layer PAS. The third electrode group is formed by forming a transparent electrode layer through a deposition method such as a sputtering method, and then patterning the transparent electrode layer by a photolithography process and an etching process using a mask. As the transparent electrode layer, metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and ZnO are mainly used. In addition, the transparent electrode layer may have a multilayer structure in which a transmissive metal thin film and the metal oxide layer are alternately stacked.

FIG. 7 is a graph showing that the threshold voltage Vth is controlled by the second gate electrode in the TFT having the double gate structure applied to the embodiment of the present invention.

Referring to FIG. 7, the TFT DT of the bottom gate structure illustrated in FIG. 3 and the TFT DT of the top gate structure illustrated in FIG. 6 are controlled by adjusting a voltage supplied to the second gate electrode G22. It can be seen that the threshold voltage (Vth) can be adjusted toward +) and negative (-).

As described above, the OLED display device and the method of manufacturing the same according to the present invention form a top and bottom auxiliary capacitor by adding a pair of auxiliary lines that overlap each of the top and bottom with the power line and the insulating layer interposed therebetween to reduce the voltage drop of the power line. By compensating, even if the driving current of each pixel increases, the power line can supply stable power to minimize luminance unevenness.

In addition, the OLED display device and the method of manufacturing the same according to the present invention can be used as an additional gate electrode for controlling the threshold voltage by superimposing one of a pair of auxiliary lines overlapping the power line with the driving TFT of each pixel. As a result, the luminance reduction can be minimized by compensating the threshold voltage of the driving TFT that is varied accordingly, thereby increasing the lifetime.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

PC: pixel circuit GL: gate line
DL: data line PL1, PL2: power line
AL1, AL2: auxiliary line ST: switching TFT
DT: Driving TFT Cst: Storage Capacitor
Cp1, Cp2: auxiliary capacitors G1, G21, G22: gate electrode
S1, S2: source electrode D1, D2: drain electrode
SCAN: Scan Signal Vdata: Data Signal
ELVDD: High Potential Power ELVSS: Low Potential Power
AV1, AV2: Auxiliary voltage H1, H2, H3: Contact hole
PXL: pixel electrode CE: contact electrode
ACT1, ACT2: active layer SUB: substrate
GI: gate insulating film ES: etch stopper
PAS: passivation layer BF: buffer layer

Claims (12)

An organic light emitting diode (hereinafter OLED) element;
A pixel circuit connected to a gate line and a data line to independently drive the OLED element, and including a driving thin film transistor (hereinafter referred to as TFT) for controlling a current supplied to the OLED element;
A power supply line supplying a high potential power to the OLED element via the pixel circuit;
At least a portion of the power supply line overlapping the power supply line with at least a portion of the power supply line overlapping the power supply line to form a first auxiliary capacitor; At least one of a second auxiliary line to form a second auxiliary capacitor;
The pixel circuit further comprises a Vth adjusting gate electrode connected to any one of the first and second auxiliary lines to adjust a threshold voltage (hereinafter, Vth) of the driving TFT. The method according to claim 1,
The first and second auxiliary lines are supplied with a different voltage from the power line,
The first and second auxiliary lines are supplied with the same or different voltages,
And the first and second auxiliary lines are formed independently of each other or not connected to each other through contact holes penetrating through the upper insulating film and the lower insulating film. The method according to claim 2,
The power supply line is positioned between two first and second pixel circuits adjacent in the horizontal direction and commonly connected to the driving TFTs of the first and second pixel circuits;
And the Vth adjusting gate electrode extends from both sides of the power supply line to overlap both sides of the first and second pixel circuits with the gate electrode and the active layer of the driving TFT interposed therebetween. The method according to claim 3,
A gate electrode of the driving TFT overlaps with the active layer interposed therebetween;
The Vth control gate electrode overlaps the active layer with a passivation layer therebetween. The method according to claim 4,
The power supply line is formed of the same source / drain metal layer as the source electrode and the drain electrode of the driving TFT, and is connected to any one of the source electrode and the drain electrode of the driving TFT;
The other one of the source electrode and the drain electrode of the driving TFT is formed on the passivation layer and connected through a contact hole with a pixel electrode serving as one electrode of the OLED element;
The first auxiliary line is formed of the same gate metal layer as the gate electrode of the driving TFT and overlaps the power line and the gate insulating film;
The second auxiliary line is formed of the same transparent conductive layer as the pixel electrode, and overlaps the power line and the passivation layer, or between the power line and the passivation layer, between the second passivation layer. And a second source / drain metal layer formed to be disposed so as to overlap the power line and the second passivation layer, or to be formed of the transparent conductive layer and the second source / drain metal layer. The method according to claim 3,
A gate electrode of the driving TFT overlaps with the active layer interposed therebetween with a gate insulating film therebetween;
And the Vth control gate electrode overlaps the active layer and a buffer layer below the active layer to block light incident to the active layer. The method according to claim 6,
The power supply line is formed of the same source / drain metal layer as the source electrode and the drain electrode of the driving TFT, and is connected to any one of the source electrode and the drain electrode of the driving TFT;
The other one of the source electrode and the drain electrode of the driving TFT is formed on the passivation layer thereon and connected through a contact hole with a pixel electrode serving as one electrode of the OLED element;
The first auxiliary line is formed of the same light-shielding metal layer as the Vth control gate electrode and overlaps the plurality of insulating films including the power line, the buffer layer, and the gate insulating film;
And the second auxiliary line is formed of the same conductive layer as the pixel electrode, and overlaps the power line and the passivation layer. In the manufacturing method of the OLED display device provided with the pixel circuit containing the drive TFT connected between a power supply line and OLED element,
Forming the power supply line as a source / drain metal layer together with a source electrode and a drain electrode of the driving TFT;
At least a portion of the power supply line overlapping the power supply line with at least a portion of the power supply line overlapping the power supply line to form a first auxiliary capacitor; Forming at least one of a second auxiliary line to form a second auxiliary capacitor;
Forming a Vth adjusting gate electrode connected to either one of the first and second auxiliary lines to adjust Vth of the driving TFT;
And the first and second auxiliary lines are formed independently of each other or not connected to each other through contact holes penetrating through the upper insulating film and the lower insulating film. delete The method according to claim 8,
The power supply line is positioned between two first and second pixel circuits adjacent in the horizontal direction and commonly connected to the driving TFTs of the first and second pixel circuits;
And the gate electrode for adjusting the Vth is extended from both sides of the power supply line so as to overlap the gate electrode and the active layer of the driving TFT in each of the first and second pixel circuits. The method according to claim 10,
Forming a gate electrode of the driving TFT and the first auxiliary line as a gate metal layer on a substrate;
Forming a gate insulating film on the gate metal layer;
Forming an active layer of the driving TFT on the gate insulating film;
Forming a source electrode and a drain electrode of the driving TFT connected with the active layer, and the power supply line as a source / drain metal layer;
Forming a passivation layer on said source / drain metal layer and forming a contact hole through said at least passivation layer;
And forming the second auxiliary line and the Vth adjusting gate electrode as a transparent conductive layer together with a pixel electrode connected to the driving TFT through the contact hole. The method according to claim 8,
Forming the Vth adjusting gate electrode and the first auxiliary line as a light blocking metal layer on a substrate;
Forming a buffer layer on the light shielding metal layer;
Forming an active layer of the driving TFT on the buffer layer;
Forming a gate insulating film on the active layer;
Forming a gate electrode of the driving TFT on the gate insulating film;
Forming an interlayer insulating layer on the gate electrode and forming a source contact hole and a drain contact hole exposing a source region and a drain region of the active layer;
Forming the power supply line as a source / drain metal layer on the interlayer insulating layer together with the source electrode and the drain electrode of the driving TFT respectively connected to the source region and the drain region of the active layer through the source contact hole and the drain contact hole; Steps;
Forming a passivation layer on said source / drain metal layer and forming a contact hole through said at least passivation layer;
Forming the second auxiliary line as a transparent conductive layer together with a pixel electrode connected to the driving TFT through the contact hole.

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