KR102009930B1 - Chopper stabilized amplifying circuit and signal processing circuit for capacitive sensor using the chopper stabilized amplifying circuit - Google Patents

Abstract

The chopper stabilized amplifier circuit includes an amplifier; A first chopper circuit having an output terminal connected to an input terminal of the amplifier; A second chopper circuit having an input terminal connected to an output terminal of the amplifier; And a first switch circuit connected to an input terminal of the first chopper circuit and an output terminal of the second chopper circuit; And a first capacitor connected with the first switch circuit.

Description

CHAPPER STABILIZED AMPLIFYING CIRCUIT AND SIGNAL PROCESSING CIRCUIT FOR CAPACITIVE SENSOR USING THE CHOPPER STABILIZED AMPLIFYING CIRCUIT}

The present invention relates to a chopper stabilized amplifier circuit and a capacitive sensor signal processing circuit using the chopper stabilized amplifier circuit, and a chopper stabilized amplifier circuit capable of efficiently removing noise by sweeping both ends of a feedback capacitor of an amplifier and The present invention relates to a capacitive sensor signal processing circuit using a chopper stabilized amplifier circuit.

Capacitive sensors are widely used in a variety of sensor applications for measuring pressure, humidity and acceleration. In particular, with the recent development of IoT technology, processing circuits for capacitive sensors require high performance.

Figure 1 shows a prior art 1 (A. Alhoshany, et al., "A 45.8 fJ / Step, energy efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing," Sens. Actuators A, Phys., Vol. 245 , pp. 10-18, Jul. 2016.) shows a circuit diagram of the capacitive sensor signal processing circuit.

In the prior art 1, the successive approximation register (SAR) capacitive-to-digital converter technology of the successive approximation register (SAR) with the capacitive sensor signal processing circuit introduced has the advantages of low power and simple structure, but has a limitation in obtaining high resolution.

FIG. 2 shows prior art 2 (Z. Tan, et al., "A 1.2V 8.3nJ Energy-Efficient CMOS Humidity Sensor for RFID Applications," in Symposium on VLSI Circuits Digest Technical Papers, Jul. 2012, pp. 24-25 The circuit diagram of the capacitive sensor signal processing circuit of FIG.

In the prior art 2, the ΔΣ Capacitance-to-Digital Converter adopting a delta-sigma (ΔΣ) structure can obtain high resolution through oversampling and noise shaping. The sensor signal processing circuit using the higher order ΔΣ modulator of this structure can more effectively reduce noise in the signal band and detect more accurate capacitive sensor changes. However, the higher the order, the more complicated the circuit and the more area is required. In order to compensate for the disadvantages of the conventional ΔΣ capacitive sensor signal processing circuit, there is a need for a capacitive sensor signal processing circuit that can effectively reduce noise in a signal band without increasing the order of the ΔΣ capacitive sensor signal processing circuit. .

SUMMARY OF THE INVENTION The present invention has an object of solving the above technical problem, and a chopper stabilized amplifying circuit to which a dynamic capacitor exchange technique is applied to effectively reduce noise in a signal band without increasing the order of the capacitive sensor signal processing circuit and its It is an object of the present invention to provide a capacitive sensor signal processing circuit using a chopper stabilized amplifier circuit.

The chopper stabilized amplifier circuit of the present invention, the amplifier; A first chopper circuit having an output terminal connected to an input terminal of the amplifier; A second chopper circuit having an input terminal connected to an output terminal of the amplifier; A first switch circuit connected to an input terminal of the first chopper circuit and an output terminal of the second chopper circuit; And a first capacitor connected with the first switch circuit.

Specifically, the input terminal of the first chopper circuit receives a signal through a 1-1 chopper input node and a 1-2 chopper input node, and the output terminal of the second chopper circuit is a 2-1 chopper output node and a second. It is desirable to output the signal through the -2 chopper output node.

In addition, the first switch circuit, a first-1 to connect one end of the first capacitor to the first-1 chopper input node, the other end of the first capacitor is connected to the 2-2 chopper output node Capacitor mode; And a first 1-2 capacitor mode in which one end of the first capacitor is connected to the 1-2 chopper input node and the other end of the first capacitor is connected to the 2-1 chopper output node. .

Preferably, the chopper stabilized amplifier circuit of the present invention comprises: a second switch circuit connected to an input terminal of the first chopper circuit and an output terminal of the second chopper circuit; And a second capacitor connected with the second switch circuit.

The second switch circuit may include a second-1 connecting one end of the second capacitor to the 1-2 chopper input node and the other end of the second capacitor to the 2-1 chopper output node. Capacitor mode; And a 2-2 capacitor mode in which one end of the second capacitor is connected to the 1-1 chopper input node, and the other end of the second capacitor is connected to the 2-2 chopper output node. .

In addition, the operating time in the first-1 capacitor mode of the first switch circuit and the second-1 capacitor mode of the second switch circuit is the same, and the 1-2 capacitor mode of the first switch circuit is the same. Is the same as the operating time in the 2-2 capacitor mode of the second switch circuit, the operating time in the 1-1 capacitor mode of the first switch circuit and the 1-2 capacitor The operation time in the mode does not overlap, and the operating frequency in the first-1 capacitor mode of the first switch circuit and the operating frequency in the 1-2 capacitor mode are characterized in that the same.

In addition, the output terminal of the first chopper circuit outputs a signal through a 1-1 chopper output node and a 1-2 chopper output node, wherein the first chopper circuit includes: the 1-1 chopper input node and the A 1-1 chopper mode for connecting a 1-1 chopper output node and connecting the 1-2 chopper input node and the 1-2 chopper output node; And a 1-2 chopper mode that connects the 1-1 chopper input node and the 1-2 chopper output node and connects the 1-2 chopper input node and the 1-1 chopper output node. It can work.

Preferably, the operating time in the first chopper mode of the first chopper circuit and the operating time in the 1-2 chopper mode do not overlap, but the first chopper of the first chopper circuit does not overlap. The operating frequency in the mode and the operating frequency in the 1-2 chopper mode is characterized in that the same.

In addition, the operating frequency of the first switch circuit in the first-1 capacitor mode is preferably a multiple of the operating frequency of the first chopper circuit in the first-1 chopper mode.

To express the configuration of the chopper stabilized amplifier circuit of the present invention described above, the chopper stabilized amplifier circuit of the present invention includes: an amplifier; A first chopper circuit having an output terminal connected to an input terminal of the amplifier; A second chopper circuit having an input terminal connected to an output terminal of the amplifier; A switch circuit unit connected to an input terminal of the first chopper circuit and an output terminal of the second chopper circuit and including at least one switch circuit; And a capacitor unit including at least one feedback capacitor that may be connected between an input terminal of the amplifier and an output terminal of the amplifier.

Specifically, the switch circuit unit may include: a 1-1 capacitor mode in which one end of the first capacitor of the at least one feedback capacitor is connected to an input terminal of the amplifier and the other end of the first capacitor is connected to an output terminal of the amplifier; And a first and second capacitor modes in which one end of the first capacitor is connected to the output terminal of the amplifier and the other end of the first capacitor is connected to the input terminal of the amplifier.

In addition, the operating time of the 1-1 capacitor mode and the operating time of the 1-2 capacitor mode do not overlap, and the operating frequency of the 1-1 capacitor mode and the operating frequency of the 1-2 capacitor mode are The same is preferable.

The operating frequency of the first-1 capacitor mode is a multiple of the operating frequency of the first chopper circuit.

The capacitive sensor signal processing circuit of the present invention includes the chopper stabilized amplifier circuit of the present invention described above.

According to the chopper stabilized amplifier circuit of the present invention and the capacitive sensor signal processing circuit using the chopper stabilized amplifier circuit, the noise in the signal band can be effectively reduced by applying the dynamic capacitor exchange technique without increasing the order of the capacitive sensor signal processing circuit. have.

1 is a circuit diagram of a capacitive sensor signal processing circuit of the prior art 1. FIG.
2 is a circuit diagram of a capacitive sensor signal processing circuit of the related art 2. FIG.
3 is a block diagram of a chopper stabilized amplifier circuit according to a first embodiment of the present invention.
4 is a circuit diagram of a first chopper circuit and a second chopper circuit.
Fig. 5 is a timing diagram of the main part of the chopper stabilized amplifier circuit according to the first embodiment of the present invention.
6 is a block diagram of a capacitive sensor signal processing circuit according to a first preferred embodiment of the present invention.
7 is a circuit diagram of a third chopper circuit.
8 is a block diagram of a capacitive sensor signal processing circuit according to a second preferred embodiment of the present invention.

Hereinafter, a chopper stabilized amplifier circuit and a capacitive sensor signal processing circuit using the chopper stabilized amplifier circuit according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The following examples of the present invention are intended to embody the present invention, but not to limit or limit the scope of the present invention. From the detailed description and the embodiments of the present invention, those skilled in the art to which the present invention pertains can easily be interpreted as belonging to the scope of the present invention.

3 shows a configuration diagram of a chopper stabilized amplifier circuit 10 according to a first preferred embodiment of the present invention.

As can be seen from FIG. 3, the chopper stabilized amplifier circuit 10 according to the first preferred embodiment of the present invention includes an amplifier 11, a first chopper circuit 12, a second chopper circuit 13, and a switch. The circuit part 14 and the capacitor part 15 are comprised.

The amplifier 11 can use an operational amplifier, and the form of an inverting amplifier is preferable. In addition, the amplifier 11 may output a differential signal or perform a single output.

In the first chopper circuit 12, an output terminal is connected to an input terminal of the amplifier 11, and the second chopper circuit 13 is connected to an input terminal of the second chopper circuit 13 to an output terminal of the amplifier 11.

4 shows a circuit diagram of the first chopper circuit 12 and the second chopper circuit 13. Fig. 5 shows a timing diagram of main parts of the chopper stabilized amplifier circuit 10 according to the first embodiment of the present invention.

3 to 5, the operation of the first chopper circuit 12 and the second chopper circuit 13 will be described in detail.

The input terminal of the first chopper circuit 12 receives a signal through the 1-1 chopper input node Ni11 and the 1-2 chopper input node Ni12. In addition, the output terminal of the first chopper circuit 12 outputs a signal through the 1-1 chopper output node No11 and the 1-2 chopper output node No12.

In addition, the first chopper circuit 12 connects the first-first chopper input node Ni11 and the first-first chopper output node No11, and the first-second chopper input node Ni12 and the first- A 1-1 chopper mode for connecting two chopper output nodes No12; And connecting the 1-1 chopper input node Ni11 and the 1-2 chopper output node No12 and the 1-2 chopper input node Ni12 and the 1-1 chopper output node No11. It can operate in the 1-2 chopper mode.

That is, in the 1-1 chopper mode, the 1-1 chopper switch SW_CH11 and the 1-4 chopper switch SW_CH14 are turned on, and the 1-2 chopper switch SW_CH12 and the 1-3 chopper switch ( SW_CH13) is turned off. In addition, in the 1-2th chopper mode, the 1-2th chopper switch SW_CH12 and the 1-3th chopper switch SW_CH13 are turned on, and the 1-1th chopper switch SW_CH11 and the 1-4th chopper switch ( SW_CH14) is turned off. The 1-1 chopper switch SW_CH11 and the 1-4 chopper switch SW_CH14 are controlled by the first chopper control signal CON_CH1, and the 1-2 chopper switch SW_CH12 and the 1-3 chopper switch ( SW_CH13 is controlled by the second chopper control signal CON_CH2.

The operating time in the 1-1 chopper mode of the first chopper circuit 12 and the operating time in the 1-2 chopper mode do not overlap, but in the 1-1 chopper mode of the first chopper circuit 12. It can be seen that the operating frequency and the operating frequency in the first 1-2 chopper mode are the same.

The input terminal of the second chopper circuit 13 receives a signal through the 2-1 chopper input node Ni21 and the 2-2 chopper input node Ni22. In addition, the output terminal of the second chopper circuit 13 outputs a signal through the 2-1 chopper output node No21 and the 2-2 chopper output node No22.

In addition, the second chopper circuit 13 connects the 2-1 chopper input node Ni21 and the 2-1 chopper output node No21, and the 2-2 chopper input node Ni22 and the second 2-second chopper input node Ni21. A 2-1 chopper mode for connecting two chopper output nodes No22; And a 2-1 chopper input node Ni21 and a 2-2 chopper output node No22, and a 2-2 chopper input node Ni22 and a 2-1 chopper output node No21. It can operate in the 2-2 chopper mode.

That is, in the 2-1 chopper mode, the 2-1 chopper switch SW_CH21 and the 2-4 chopper switch SW_CH24 are turned on, and the 2-2 chopper switch SW_CH22 and the 2-3 chopper switch ( SW_CH23) is a section that is off. In addition, in the 2-2 chopper mode, the 2-2 chopper switch SW_CH22 and the 2-3 chopper switch SW_CH23 are turned on, and the 2-1 chopper switch SW_CH21 and the 2-4 chopper switch ( SW_CH24) is turned off. That is, the 2-1 chopper switch SW_CH21 and the 2-4 chopper switch SW_CH24 are controlled by the first chopper control signal CON_CH1 and the 2-2 chopper switch SW_CH22 and the 2-3 chopper. The switch SW_CH23 is controlled by the second chopper control signal CON_CH2.

The operating time in the 2-1 chopper mode of the second chopper circuit 13 and the operating time in the 2-2 chopper mode do not overlap, but in the 2-1 chopper mode of the second chopper circuit 13. It can be seen that the operating frequency and the operating frequency in the 2-2 chopper mode are the same.

The switch circuit unit 14 is connected to an input terminal of the first chopper circuit 12 and an output terminal of the second chopper circuit 13 and includes at least one switch circuit. When the amplifier 11 outputs a single output, the switch circuit section 14 includes only the first switch circuit 14a. When the amplifier 11 outputs a differential signal, the switch circuit section 14 includes the first switch circuit 14a and the second switch. It is preferable to include the switch circuit 14b.

The capacitor unit 15 includes at least one feedback capacitor which can be connected between the input terminal of the amplifier 11 and the output terminal of the amplifier 11. When the amplifier 11 outputs a single output, the capacitor unit 15 includes only the first capacitor C1. When the amplifier 11 outputs a differential signal, the capacitor unit 15 includes the first capacitor C1 and the second capacitor ( It is preferable to include C2).

Specifically, the switch circuit unit 14, one end of the first capacitor (C1) of the at least one feedback capacitor is connected to the input terminal of the amplifier 11 and the other end of the first capacitor (C1) and the output terminal of the amplifier 11 A 1-1 capacitor mode for connecting; And a first 1-2 capacitor mode in which one end of the first capacitor C1 is connected to the output terminal of the amplifier 11 and the other end of the first capacitor C1 is connected to the input terminal of the amplifier 11.

In addition, the operating time of the 1-1 capacitor mode and the operating time of the 1-2 capacitor mode do not overlap, and the operating frequency of the 1-1 capacitor mode and the operating frequency of the 1-2 capacitor mode is the same. do. In addition, it is preferable that the operating frequency of the 1-1 capacitor mode is a multiple of the operating frequency of the first chopper circuit 12.

The first switch circuit 14a of the switch circuit section 14 is connected to an input terminal of the first chopper circuit 12 and an output terminal of the second chopper circuit 13. In addition, the first capacitor C1 of the capacitor unit 15 is connected to the first switch circuit 14a.

That is, the first switch circuit 14a connects one end of the first capacitor C1 to the first-1 chopper input node Ni11 and the other end of the first capacitor C1 is the second-2 chopper output node. A 1-1 capacitor mode connected to No22; And a first 1-2 connecting one end of the first capacitor C1 to the 1-2 th chopper input node Ni12 and the other end of the first capacitor C1 connected to the 2-1 chopper output node No21. Capacitor mode; To this end, the first switch circuit 14a may include a 1-1 capacitor switch SW_CA11 and a 2-2 chopper output node connected between the 1-1 chopper input node Ni11 and one end of the first capacitor C1. A first-second capacitor switch SW_CA12 connected between No22 and the other end of the first capacitor C1, a first-second connected between the 1-2 chopper input node Ni12 and one end of the first capacitor C1; And a first capacitor switch SW_CA14 connected between the third capacitor switch SW_CA13 and the second-first chopper output node No21 and the other end of the first capacitor C1. The first-first capacitor switch SW_CA11 and the first-two capacitor switch SW_CA12 operate by the same timing signal, and the first-three capacitor switch SW_CA13 and the first-four capacitor switch SW_CA14 are the same timing. It is operated by signal.

That is, the first-first capacitor switch SW_CA11 and the first-two capacitor switch SW_CA12 are controlled by the first capacitor control signal CON_CA1, and the first-three capacitor switches SW_CA13 and the first-4 capacitors. The switch SW_CA14 is controlled by the second capacitor control signal CON_CA2.

In addition, it is preferable that the 1st switch circuit 14a further contains the 1st reset switch SW_RT1.

In addition, the second switch circuit 14b of the switch circuit unit 14 is connected to an input terminal of the first chopper circuit 12 and an output terminal of the second chopper circuit 13. In addition, the second capacitor C2 of the capacitor unit 15 is connected to the second switch circuit 14b.

That is, the second switch circuit 14b connects one end of the second capacitor C2 to the first 1-2 chopper input node Ni12 and the other end of the second capacitor C2 is the second-1 chopper output node. A 2-1 capacitor mode connected to No21; And a second-2 connecting one end of the second capacitor C2 to the 1-1 chopper input node Ni11 and the other end of the second capacitor C2 to the 2-2 chopper output node No22. Capacitor mode; For this purpose, the second switch circuit 14b may include a 2-1 capacitor switch SW_CA21 and a 2-1 chopper output node connected between the first 1-2 chopper input node Ni12 and one end of the second capacitor C2. A second-2 capacitor switch SW_CA22 connected between the second end of the second capacitor C2 and a second capacitor connected between the first capacitor chopper input node Ni11 and one end of the second capacitor C2 (No21). And a first capacitor capacitor SW_CA14 connected between the third capacitor switch SW_CA23 and the second-2 chopper output node No22 and the other end of the second capacitor C2. The 2-1 capacitor switch SW_CA21 and the 2-2 capacitor switch SW_CA22 operate by the same timing signal, and the 2-3 capacitor switch SW_CA23 and the 2-4 capacitor switch SW_CA24 have the same timing. It is operated by signal.

That is, the 2-1 capacitor switch SW_CA21 and the 2-2 capacitor switch SW_CA22 are controlled by the first capacitor control signal CON_CA1, the 2-3 capacitor switch SW_CA23 and the 2-4 capacitor. The switch SW_CA24 is controlled by the second capacitor control signal CON_CA2.

In addition, the second switch circuit 14b preferably further includes a second reset switch SW_RT2.

The operating time in the 1-1 capacitor mode of the first switch circuit 14a and the operating time in the 2-1 capacitor mode of the second switch circuit 14b are the same, and the operation time of the first switch circuit 14a is the same. The operating time in the 1-2 capacitor mode and the operating time in the 2-2 capacitor mode of the second switch circuit 14b are the same. In addition, the operating time in the 1-1 capacitor mode of the first switch circuit 14a and the operating time in the 1-2 capacitor mode do not overlap, and the 1-1 capacitor mode of the first switch circuit 14a does not overlap. The operating frequency in and the operating frequency in the 1-2 capacitor mode is characterized in that the same. In addition, the operating time in the 2-1 capacitor mode of the second switch circuit 14b and the operating time in the 2-2 capacitor mode do not overlap, and the 2-1 capacitor mode of the second switch circuit 14b does not overlap. The operating frequency in and the operating frequency in the 2-2 capacitor mode is characterized in that the same. In addition, the operating frequency in the 1-1 capacitor mode of the first switch circuit 14a and the operating frequency in the 1-2 capacitor mode are operated in the 1-1 chopper mode of the first chopper circuit 12. It is preferably a multiple of the frequency. That is, the operating frequency in the 2-1 capacitor mode of the second switch circuit 14b and the operating frequency in the 2-2 capacitor mode are operated in the 1-1 chopper mode of the first chopper circuit 12. It is preferably a multiple of the frequency.

As described above, the chopper stabilized amplifier circuit 10 according to the first preferred embodiment of the present invention is the first capacitor C1 which is a feedback capacitor by the first switch circuit 14a and the second switch circuit 14b. And / or a sweep operation for changing the polarity connected to the input terminal and the output terminal of the amplifier 11 of the second capacitor C2. The sweep operation increases the common mode rejection ratio (CMRR) and reduces the low frequency noise and the common mode noise.

Accordingly, it is possible to effectively reduce the signal band to noise without increasing the order of the amplifier stage.

6 shows a configuration diagram of the capacitive sensor signal processing circuit 100 according to the first preferred embodiment of the present invention.

The capacitive sensor signal processing circuit 100 according to the first preferred embodiment of the present invention uses the chopper stabilized amplification circuit 10 according to the first preferred embodiment of the present invention. It goes without saying that it includes all the features of the chopper stabilized amplifier circuit 10 according to the first preferred embodiment.

As can be seen from FIG. 6, the capacitive sensor signal processing circuit 100 according to the first preferred embodiment of the present invention includes a sensor signal input unit 110, a first chopper stabilized amplification circuit 120, and a comparison unit ( 140 and the accumulator 150.

The sensor signal input unit 110 outputs a signal from at least one sensor by using a capacitor and a switch. The first chopper stabilized amplifier circuit 120 amplifies and outputs a signal input from the sensor signal input unit 110. The first chopper stabilized amplifier circuit 120 uses the chopper stabilized amplifier circuit 10 according to the first preferred embodiment of the present invention described above. The comparator 140 outputs the output of the first chopper stabilized amplifier circuit 120 as '1' or '0' using the comparator 141. However, the chopper stabilized amplifier circuit 10 according to the first preferred embodiment of the present invention includes the first capacitor C1 and / or the feedback capacitor by the first switch circuit 14a and the second switch circuit 14b. By the sweep operation of changing the polarity of the second capacitor C2, the output node of the first chopper stabilizing amplification circuit 120 is changed according to the change of the polarity of the first capacitor C1 and / or the second capacitor C2. Since it is changed, the comparator 140 may further include a third chopper circuit 142 that connects the output of the comparator 141 with the output terminal of the comparator 141. The third chopper circuit 142 plays a role of returning to the original state that the output node of the first chopper stabilized amplifying circuit 120 is changed.

7 shows a circuit diagram of the third chopper circuit 142.

As can be seen from FIG. 7, the third chopper circuit 142 receives a signal through the 3-1 chopper input node Ni31 and the 3-2 chopper input node Ni32, and 3-1. The signal is output through the chopper output node No31 and the 3-2 chopper output node No32.

That is, the third chopper circuit 142 connects the 3-1 chopper input node Ni31 and the 3-1 chopper output node No31, and the 3-2 chopper input node Ni32 and the 3- A 3-1 chopper mode for connecting two chopper output nodes No32; And a 3-1 chopper input node Ni31 and a 3-2 chopper output node No32, and a 3-2 chopper input node Ni32 and a 3-1 chopper output node No31. 3-2 chopper mode;

That is, in the 3-1 chopper mode, the 3-1 chopper switch SW_CH31 and the 3-4 chopper switch SW_CH34 are turned on, and the 3-2 chopper switch SW_CH32 and the 3-3 chopper switch ( SW_CH33) is turned off. In addition, in the 3-2 chopper mode, the 3-2 chopper switch SW_CH32 and the 3-3 chopper switch SW_CH33 are turned on, and the 3-1 chopper switch SW_CH31 and the 3-4 chopper switch ( SW_CH34) is a section that is off. That is, the 3-1 chopper switch SW_CH31 and the 3-4 chopper switch SW_CH34 are controlled by the first chopper control signal CON_CH1 and the 3-2 chopper switch SW_CH32 and the 3-3 chopper. The switch SW_CH33 is controlled by the second chopper control signal CON_CH2.

The accumulator 150 accumulates and outputs the output of the comparator 140.

8 shows a schematic diagram of a capacitive sensor signal processing circuit 200 according to a second preferred embodiment of the present invention.

The capacitive sensor signal processing circuit 200 according to the second preferred embodiment of the present invention uses the chopper stabilized amplification circuit 10 according to the first preferred embodiment of the present invention. It goes without saying that it includes all the features of the chopper stabilized amplifier circuit 10 according to the first preferred embodiment.

As can be seen from FIG. 8, the capacitive sensor signal processing circuit 200 according to the second preferred embodiment of the present invention includes a sensor signal input unit 210, a first chopper stabilized amplification circuit 220, and a second chopper. It includes a stabilization amplifier circuit 230, a comparator 240 and the accumulator 250 (Accumulator).

The sensor signal input unit 210 outputs a signal from at least one sensor by using a capacitor and a switch. The first chopper stabilized amplifier circuit 220 amplifies and outputs a signal input from the sensor signal input unit 210. The second chopper stabilized amplifier circuit 230 serves to amplify and output the signal input from the first chopper stabilized amplifier circuit 220. The first chopper stabilized amplifier circuit 220 and the second chopper stabilized amplifier circuit 230 use the chopper stabilized amplifier circuit 10 according to the first preferred embodiment of the present invention described above. The comparator 240 outputs the output of the second chopper stabilized amplifier circuit 230 as '1' or '0' using the comparator 241. Since the capacitive sensor signal processing circuit 200 according to the second preferred embodiment of the present invention includes a first chopper stabilized amplifier circuit 220 and a second chopper stabilized amplifier circuit 230, the first chopper stabilized amplifier circuit ( Since the output of the 220 is changed in accordance with the change of the polarity of the feedback capacitor, and again the output of the second chopper stabilized amplification circuit 230 is changed in accordance with the change of the polarity of the feedback capacitor, according to the first preferred embodiment of the present invention. It is not necessary to include the third chopper circuit 142 like the capacitive sensor signal processing circuit 100.

The accumulator 250 accumulates and outputs the output of the comparator 240.

The difference between the capacitive sensor signal processing circuit 100 according to the first preferred embodiment of the present invention and the capacitive sensor signal processing circuit 200 according to the second preferred embodiment of the present invention is that the amplifying stage has one stage and two stages, respectively. It is designed as a stage. The amplification stage may use a plurality of orders as necessary, but due to the excellent noise characteristics of the chopper stabilized amplification circuit 10, many amplification stages may not be necessary.

As described above, according to the capacitive sensor signal processing circuits 100 and 200 using the chopper stabilized amplifying circuit 10 and the chopper stabilized amplifying circuit 10 of the present invention, the capacitive type is applied by applying a dynamic capacitor exchange technique. It can be seen that the noise in the signal band can be effectively reduced without increasing the order of the sensor signal processing circuit.

10: chopper stabilized amplifier circuit
11: amplifier 12: first chopper circuit
13: second chopper circuit 14: switch circuit portion
15: capacitor
14a: first switch circuit 14b: second switch circuit
SW_CH11: 1st-1 Chopper Switch SW_CH12: 1-2th Chopper Switch
SW_CH13: First 1-3 Chopper Switch SW_CH14: First 1-3 Chopper Switch
SW_CH21: 2-1 Chopper Switch SW_CH22: 2-2 Chopper Switch
SW_CH23: 2-3th chopper switch SW_CH24: 2nd-4 chopper switch
C1: first capacitor C2: second capacitor
SW_CA11: 1st-1 capacitor switch SW_CA12: 1st-2 capacitor switch
SW_CA13: First 1-3 Capacitor Switch SW_CA14: First 1-3 Capacitor Switch
SW_CA21: 2-1 Capacitor Switch SW_CA22: 2-2 Capacitor Switch
SW_CA23: 2nd-3 Capacitor Switch SW_CA24: 2nd-2 Capacitor Switch
SW_RT1: first reset switch SW_RT2: second reset switch
Ni11: 1st-1 Chopper Input Node Ni12: 1-2th Chopper Input Node
No11: 1st-1 Chopper Output Node No12: 1-2th Chopper Output Node
Ni21: 2-1 Chopper Input Node Ni22: 2-2 Chopper Input Node
No21: 2-1 chopper output node No22: 2-2 chopper output node
CON_CH1: first chopper control signal CON_CH2: second chopper control signal
CON_CA1: first capacitor control signal CON_CA2: second capacitor control signal
100, 200: capacitive sensor signal processing circuit
110, 210: sensor signal input unit
120, 220: first chopper stabilized amplifier circuit
230: second chopper stabilized amplifier circuit 140, 240: comparison unit
150, 250: accumulator
141, 241: comparator 142: third chopper circuit
SW_CH31: 3-1 Chopper Switch SW_CH32: 3-2 Chopper Switch
SW_CH33: 3-3 Chopper Switch SW_CH34: 3-4 Chopper Switch
Ni31: 3-1 Chopper Input Node Ni32: 3-2 Chopper Input Node
No31: 3-1 Chopper Output Node No32: 3-2 Chopper Output Node

Claims (14)

delete delete delete delete delete delete delete delete delete In the chopper stabilized amplifier circuit,
amplifier;
A first chopper circuit having an output terminal connected to an input terminal of the amplifier;
A second chopper circuit having an input terminal connected to an output terminal of the amplifier;
A switch circuit unit connected to an input terminal of the first chopper circuit and an output terminal of the second chopper circuit and including at least one switch circuit; And
And a capacitor unit including at least one feedback capacitor that may be connected between an input terminal of the amplifier and an output terminal of the amplifier.
The switch circuit unit,
A 1-1 capacitor mode in which one end of the first capacitor of the at least one feedback capacitor is connected to an input terminal of the amplifier and the other end of the first capacitor is connected to an output terminal of the amplifier; And
And one or two capacitor modes connecting one end of the first capacitor to an output end of the amplifier and the other end of the first capacitor to an input end of the amplifier. delete The method of claim 10,
The operating time of the 1-1 capacitor mode and the operating time of the 1-2 capacitor mode do not overlap,
And the operating frequency of the 1-1 capacitor mode and the operating frequency of the 1-2 capacitor mode are the same. The method of claim 12,
The operating frequency of the first-1 capacitor mode is a multiple of the operating frequency of the first chopper circuit. 14. A capacitive sensor signal processing circuit comprising the chopper stabilized amplifying circuit of any one of claims 10, 12 and 13.

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