KR101952209B1 - 벡터 레지스터 파일의 동적 재명명 기반의 레지스터 재구성 - Google Patents

벡터 레지스터 파일의 동적 재명명 기반의 레지스터 재구성 Download PDF

Info

Publication number
KR101952209B1
KR101952209B1 KR1020130160351A KR20130160351A KR101952209B1 KR 101952209 B1 KR101952209 B1 KR 101952209B1 KR 1020130160351 A KR1020130160351 A KR 1020130160351A KR 20130160351 A KR20130160351 A KR 20130160351A KR 101952209 B1 KR101952209 B1 KR 101952209B1
Authority
KR
South Korea
Prior art keywords
register
entry
registers
information
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020130160351A
Other languages
English (en)
Korean (ko)
Other versions
KR20140113307A (ko
Inventor
브래들리 진 버제스
아쉬라프 아메드
라비 아이옌가
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Publication of KR20140113307A publication Critical patent/KR20140113307A/ko
Application granted granted Critical
Publication of KR101952209B1 publication Critical patent/KR101952209B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
KR1020130160351A 2013-03-15 2013-12-20 벡터 레지스터 파일의 동적 재명명 기반의 레지스터 재구성 Active KR101952209B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/837,213 US9588770B2 (en) 2013-03-15 2013-03-15 Dynamic rename based register reconfiguration of a vector register file
US13/837,213 2013-03-15

Publications (2)

Publication Number Publication Date
KR20140113307A KR20140113307A (ko) 2014-09-24
KR101952209B1 true KR101952209B1 (ko) 2019-04-22

Family

ID=51419102

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130160351A Active KR101952209B1 (ko) 2013-03-15 2013-12-20 벡터 레지스터 파일의 동적 재명명 기반의 레지스터 재구성

Country Status (5)

Country Link
US (1) US9588770B2 (enExample)
JP (1) JP6196176B2 (enExample)
KR (1) KR101952209B1 (enExample)
CN (1) CN104049947B (enExample)
DE (1) DE102014103184A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11429393B2 (en) * 2015-11-11 2022-08-30 Arm Limited Apparatus and method for supporting out-of-order program execution of instructions
CN106095393B (zh) * 2016-06-22 2019-04-30 上海兆芯集成电路有限公司 在回退阶段期间合并部分写结果的系统和方法
CN107291425B (zh) * 2017-06-23 2020-11-24 上海兆芯集成电路有限公司 合并解决重命名尺寸问题的部分写入结果的系统和方法
US11256509B2 (en) * 2017-12-07 2022-02-22 International Business Machines Corporation Instruction fusion after register rename
US11276223B2 (en) 2018-12-13 2022-03-15 Advanced Micro Devices, Inc. Merged data path for triangle and box intersection test in ray tracing
US10747538B2 (en) 2018-12-21 2020-08-18 Intel Corporation Method and apparatus to re-configure MDIO registers on an ethernet device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030217249A1 (en) 2002-05-20 2003-11-20 The Regents Of The University Of Michigan Method and apparatus for virtual register renaming to implement an out-of-order processor
US20100205409A1 (en) 2009-02-04 2010-08-12 Stmicroelectronics (Beijing) R&D Co. Ltd. Novel register renaming system using multi-bank physical register mapping table and method thereof
US7809932B1 (en) 2004-03-22 2010-10-05 Altera Corporation Methods and apparatus for adapting pipeline stage latency based on instruction type
JP2011018120A (ja) 2009-07-07 2011-01-27 Nec Computertechno Ltd 情報処理装置及びベクトル型情報処理装置
US20120124337A1 (en) 2010-11-16 2012-05-17 Arm Limited Size mis-match hazard detection
US20120151182A1 (en) 2010-12-09 2012-06-14 Tomasz Madajczak Performing Function Calls Using Single Instruction Multiple Data (SIMD) Registers

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481683A (en) 1992-10-30 1996-01-02 International Business Machines Corporation Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US6609189B1 (en) 1998-03-12 2003-08-19 Yale University Cycle segmented prefix circuits
US20080077782A1 (en) 2006-09-26 2008-03-27 Arm Limited Restoring a register renaming table within a processor following an exception
US7765384B2 (en) * 2007-04-18 2010-07-27 International Business Machines Corporation Universal register rename mechanism for targets of different instruction types in a microprocessor
US7725439B2 (en) 2007-08-03 2010-05-25 International Business Machines Corporation Handling column renaming as part of schema evolution in a data archiving tool
US8250346B2 (en) 2009-06-04 2012-08-21 Arm Limited Register renaming of a partially updated data granule
TWI389026B (zh) 2009-06-08 2013-03-11 Rdc Semiconductor Co Ltd 暫存器更名表的回復方法與回復系統
US20110238962A1 (en) 2010-03-23 2011-09-29 International Business Machines Corporation Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030217249A1 (en) 2002-05-20 2003-11-20 The Regents Of The University Of Michigan Method and apparatus for virtual register renaming to implement an out-of-order processor
US7809932B1 (en) 2004-03-22 2010-10-05 Altera Corporation Methods and apparatus for adapting pipeline stage latency based on instruction type
US20100205409A1 (en) 2009-02-04 2010-08-12 Stmicroelectronics (Beijing) R&D Co. Ltd. Novel register renaming system using multi-bank physical register mapping table and method thereof
JP2011018120A (ja) 2009-07-07 2011-01-27 Nec Computertechno Ltd 情報処理装置及びベクトル型情報処理装置
US20120124337A1 (en) 2010-11-16 2012-05-17 Arm Limited Size mis-match hazard detection
US20120151182A1 (en) 2010-12-09 2012-06-14 Tomasz Madajczak Performing Function Calls Using Single Instruction Multiple Data (SIMD) Registers

Also Published As

Publication number Publication date
KR20140113307A (ko) 2014-09-24
US9588770B2 (en) 2017-03-07
JP2014182830A (ja) 2014-09-29
DE102014103184A1 (de) 2014-09-18
CN104049947B (zh) 2018-03-09
JP6196176B2 (ja) 2017-09-13
US20140281415A1 (en) 2014-09-18
CN104049947A (zh) 2014-09-17

Similar Documents

Publication Publication Date Title
US9250901B2 (en) Execution context swap between heterogeneous functional hardware units
US8386754B2 (en) Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism
CN106648843B (zh) 用于改善连续的事务性存储器区的吞吐量的系统、方法和装置
JP5894120B2 (ja) ゼロサイクルロード
US9256433B2 (en) Systems and methods for move elimination with bypass multiple instantiation table
KR101655713B1 (ko) 이동 제거 연산들에서의 플래그 트래킹을 위한 시스템들 및 방법들
KR101952209B1 (ko) 벡터 레지스터 파일의 동적 재명명 기반의 레지스터 재구성
US20120060015A1 (en) Vector Loads with Multiple Vector Elements from a Same Cache Line in a Scattered Load Operation
US20120060016A1 (en) Vector Loads from Scattered Memory Locations
US20130305022A1 (en) Speeding Up Younger Store Instruction Execution after a Sync Instruction
US9740623B2 (en) Object liveness tracking for use in processing device cache
US10445101B2 (en) Controlling processing of instructions in a processing pipeline
CN113590197A (zh) 一种支持可变长向量处理的可配置处理器及其实现方法
KR20160075639A (ko) 이미디에이트 핸들링 및 플래그 핸들링을 위한 프로세서 및 방법
US20150309796A1 (en) Renaming with generation numbers
US10579384B2 (en) Effective address based instruction fetch unit for out of order processors
US10387162B2 (en) Effective address table with multiple taken branch handling for out-of-order processors
US10552156B2 (en) Processing operation issue control
CN120255960A (zh) 一种寄存器重命名方法和处理器

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20131220

PG1501 Laying open of application
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20180726

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 20131220

Comment text: Patent Application

PA0302 Request for accelerated examination

Patent event date: 20180726

Patent event code: PA03022R01D

Comment text: Request for Accelerated Examination

Patent event date: 20131220

Patent event code: PA03021R01I

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20181113

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20190130

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20190220

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20190221

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20211229

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20221221

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20231226

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20241226

Start annual number: 7

End annual number: 7