KR101949506B1 - Light emitting diode chip having plurality of mesa structures - Google Patents

Abstract

A light emitting diode chip having a plurality of mesa structures is disclosed. The light emitting diode chip comprises: a substrate; A first conductive semiconductor layer disposed on a substrate; A plurality of mesa structures located on the first conductivity type semiconductor layer and each including a second conductivity type semiconductor layer and an active layer; A first electrode pad disposed on the second conductivity type semiconductor layer at least partially opposite to the first conductivity type semiconductor layer; A first electrode extension extending from the first electrode pad and connected to the first conductivity type semiconductor layer; A second electrode pad electrically connected to the second conductivity type semiconductor layer; An insulating layer interposed between the first electrode pad and the second conductive type semiconductor layer; A bottom reflector disposed below the substrate opposite to the first conductivity type semiconductor layer; A transparent conductive layer positioned on the second conductivity type semiconductor layer; And a current blocking layer positioned between the second conductive type semiconductor layer and the transparent conductive layer, wherein the current blocking layer is disposed in a region overlapping with the second electrode pad in a plan view, and the transparent conductive layer is a second conductive semiconductor layer And is in contact with the second conductivity type semiconductor layer in an area not overlapping with the electrode pad.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode chip having a plurality of mesa structures,

The present invention relates to a light emitting diode chip, and more particularly, to a light emitting diode chip having a plurality of mesa structures.

GaN-based LEDs are currently used in various applications such as color LED display devices, LED traffic signals, and white LEDs. In recent years, high efficiency white LEDs are expected to replace fluorescent lamps. In particular, the efficiency of white LEDs has reached a level similar to that of ordinary fluorescent lamps.

The gallium nitride series light emitting diode is generally formed by growing epitaxial layers on a substrate such as sapphire, and includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer interposed therebetween. On the other hand, an n-electrode pad is formed on the n-type semiconductor layer, and a p-electrode pad is formed on the p-type semiconductor layer. The light emitting diode is electrically connected to an external power source through the electrode pads. At this time, current flows from the p-electrode pad to the n-electrode pad through the semiconductor layers.

On the other hand, extensions extending from the electrode pads are used to facilitate current dispersion in the light emitting diode. For example, U.S. Patent No. 6,650,018 discloses a technique in which electrode contacts, that is, a plurality of extensions from electrode pads extend in opposite directions to enhance current dispersion. By using an extension extended from the electrode pad, the efficiency of the light emitting diode can be increased by dispersing the current.

However, the n-electrode pad and the n-electrode extension are usually formed on the exposed n-type semiconductor layer by etching the p-type semiconductor layer and the active layer. Accordingly, the light emitting area is reduced by forming the n-electrode pad and the n-electrode extension, resulting in a reduction in luminous efficiency.

On the other hand, since the electrode pads and the electrode extensions are formed of metal, the light generated in the active layer is absorbed and lost by the electrode pads and the electrode extensions. Further, even if the electrode extensions are used to disperse the current, since the current is mainly concentrated in the region adjacent to the electrode extensions, the optical loss due to the electrode extensions is amplified. Furthermore, since the electrode pad and the electrode extension use a material having a poor reflection property such as Cr as a lower layer, for example, the light loss due to light absorption at the bottom of the electrode pad and / or electrode extension is large.

Furthermore, as the size of the light emitting diode becomes larger, the probability that a defect is included in the light emitting diode increases. For example, defects such as threading dislocations, pinholes, and the like, provide a path through which current is abruptly impeded, thereby impeding current dispersion.

Further, when a large-area light emitting diode having a size of about 1 mm 2 is driven with a driving current of about 200 mA or more, the current is concentrated through the defects or through a specific location where current is concentrated, Droop phenomenon becomes serious.

U.S. Patent No. 6,650,018

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting diode chip capable of preventing a decrease in light emitting area due to the formation of electrode pads and / or electrode extension parts.

Another object of the present invention is to provide a light emitting diode chip capable of dispersing a current over a wide area of the light emitting diode chip by mitigating current concentration generated around the electrode pad and the electrode extension part.

Another object of the present invention is to provide a light emitting diode chip capable of preventing light loss due to electrode pads and electrode extension parts.

Another object of the present invention is to provide a light emitting diode chip capable of improving external quantum efficiency by preventing current from being concentrated at a specific position when driven under a high current.

A light emitting diode chip according to an embodiment of the present invention includes: a first conductive semiconductor layer; A plurality of mesa structures located on the first conductivity type semiconductor layer, each including a second conductivity type semiconductor layer and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; A first electrode pad at least partially disposed on the second conductive type semiconductor layer so as to face the first conductive type semiconductor layer; A first electrode extension extending from the first electrode pad and connected to the first conductive type semiconductor layer; A second electrode pad electrically connected to the second conductivity type semiconductor layer; And an insulating layer interposed between the first electrode pad and the second conductive type semiconductor layer. Since the first electrode pad is located on the second conductivity type semiconductor layer, it is possible to prevent the light emitting area from being reduced due to the formation of the first electrode pad. In addition, since a plurality of mesa structures are adopted, the current can be dispersed in a plurality of mesa structures, thereby preventing the current density from rapidly increasing at a specific position of the light emitting diode chip, thereby increasing the external quantum efficiency.

The light emitting diode chip may further include a substrate, and the first conductive semiconductor layer may be disposed on the substrate. In this case, the first conductivity type semiconductor layer is positioned closer to the substrate than the second conductivity type semiconductor layer. Furthermore, the second electrode pad may also be located on the second conductive type semiconductor layer.

The second electrode pad may include a plurality of electrode pads disposed on the plurality of mesa structures. Further, the first electrode pad may include a plurality of electrode pads respectively disposed on the plurality of mesa structures.

The plurality of mesa structures are separated by an isolation region exposing the first conductive type semiconductor layer. Thus, the surface of the first conductivity type semiconductor layer is exposed in the isolation region.

In one embodiment, the first electrode extension portion may include an electrode extension portion connected to the first conductivity type semiconductor layer in the isolation region. Furthermore, the dot pattern may be interposed between the electrode extension portion and the first conductivity type semiconductor layer along the electrode extension portion in the isolation region to partially separate the electrode extension portion from the first conductivity type semiconductor layer. The dot pattern may be formed of an insulating material and may include a distributed Bragg reflector. It is possible to mitigate the concentration of current around the electrode extension portion by the dot pattern, and to disperse the current more widely.

Meanwhile, the insulating layer interposed between the first electrode pad and the second conductive type semiconductor layer may include a distributed Bragg reflector. Further, a reflector may be interposed between the insulating layer and the second conductive type semiconductor layer. The reflector may be a distributed Bragg reflector or a metal reflector.

In addition, the first electrode pad may include an electrode pad that is partially located within the isolation region.

In some embodiments, a transparent conductive layer may be interposed between the insulating layer and the second conductive type semiconductor layer. The transparent conductive layer under the insulating layer helps to supply current to the active layer in the region below the insulating layer. Alternatively, the reflector may directly contact the second conductivity type semiconductor layer in the region below the first electrode pad, thereby reducing optical loss due to the transparent conductive layer.

The mesa structures may include a plurality of through holes exposing the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer, respectively. The first electrode extension may include an electrode extension connected to the first conductivity type semiconductor layer through the plurality of through holes. The plurality of through holes are disposed along the electrode extension portion. Since the electrode extension portion is connected to the first conductivity type semiconductor layer through the through holes, concentration of current around the electrode extension portion can be mitigated and the current can be more widely dispersed.

Further, an insulating layer is interposed between the second conductive type semiconductor layer and the electrode extension portion connected to the first conductive type semiconductor layer through the plurality of through holes. The electrode extension may be insulated from the second conductivity type semiconductor layer by the insulating layer.

In addition, the insulating layer interposed between the electrode extension part and the second conductive type semiconductor layer may include a distributed Bragg reflector. Thus, light generated inside the mesa structure can be prevented from being lost by the electrode extension portion.

The insulating layer interposed between the electrode extension part and the second conductivity type semiconductor layer may extend to the side wall of the through holes to insulate the first electrode extension part from the side wall of the through hole.

Furthermore, a transparent conductive layer may be interposed between the insulating layer below the electrode extension and the second conductive type semiconductor layer. And the current can be supplied to the active layer under the electrode extension portion by the transparent conductive layer. Alternatively, the insulating layer may directly contact the second conductive type semiconductor layer under the electrode extension portion. That is, the transparent conductive layer is excluded under the electrode extension portion, and therefore, light loss due to the transparent conductive layer can be prevented.

The light emitting diode chip may include a second electrode extension portion extending from the second electrode pad. And a transparent conductive layer disposed on the second conductive semiconductor layer. The second electrode pad and the second electrode extension may be electrically connected to the second conductive type semiconductor layer through the transparent conductive layer.

In some embodiments, a current blocking layer may be interposed between the transparent conductive layer and the second conductive semiconductor layer along the second electrode extension. The current blocking layer may be arranged in a line or dot pattern. Accordingly, concentration of current around the second electrode extension portion can be mitigated. The current blocking layer may also be disposed under the second electrode pad.

Further, the current blocking layer may comprise a reflector, for example a distributed Bragg reflector. Therefore, light directed toward the second electrode extension can be prevented from being absorbed by the second electrode extension and lost.

In other embodiments, the current blocking layer may be arranged in a dot pattern between the transparent conductive layer and the second electrode extension along the second electrode extension. And the second electrode extension connects to the second conductive type semiconductor layer through the transparent conductive layer in regions between the dot patterns.

According to the present invention, it is possible to provide a light emitting diode chip capable of preventing reduction in light emitting area due to the formation of a conventional electrode pad by disposing the first electrode pad on the mesa structure. Further, by connecting the electrode extension portion to the semiconductor layer through the through holes, it is possible to prevent the reduction of the light emission area due to the formation of the electrode extension portion, and the current can be dispersed widely. Furthermore, by arranging the reflector between the electrode pad and the electrode extension portion and the semiconductor laminated structure, light loss due to the electrode pad and the electrode extension portion can be prevented. Further, by separating the light emitting region into a plurality of mesa structures, it is possible to prevent the external quantum efficiency from decreasing under a high current density by crowding the current at a specific position.

1 is a schematic plan view illustrating a light emitting diode chip according to an embodiment of the present invention.
Figures 2a, 2b, 2c and 2d are cross-sectional views taken along the perforations AA, BB, CC and DD, respectively, of Figure 1.
3 is a schematic plan view illustrating a light emitting diode chip according to another embodiment of the present invention.
4A, 4B, 4C, and 4D are cross-sectional views taken along the perforations AA, BB, CC, and DD of FIG. 3, respectively.
5A, 5B and 5C are cross-sectional views illustrating a light emitting diode chip according to another embodiment of the present invention.
6A, 6B and 6C are cross-sectional views illustrating a light emitting diode chip according to another embodiment of the present invention.
7 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention.
8 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention.
9 (a) and 9 (b) are schematic plan views illustrating a light emitting diode chip according to still another embodiment of the present invention.
FIG. 10 is a plan view illustrating a light emission pattern actually measured in order to explain the improvement in luminescence characteristics as a plurality of mesa structures are adopted.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view for explaining a light emitting diode chip according to an embodiment of the present invention, and Figs. 2a, 2b, 2c and 2d are sectional views taken along the cut lines A-A, B-B, C-C and D-D,

1, 2A, 2B, 2C, and 2D, the LED chip includes a semiconductor multilayer structure 30, a plurality of mesa structures M1 and M2, a separation region SR, a first electrode pad 37, A second electrode pad 39, first electrode extensions 37a, 37b, and 37c, a second electrode extension 39a, and a protective insulation layer 35. [ The light emitting diode chip further includes a substrate 21, a buffer layer 23, a first functional layer 31a, a second functional layer 31b, a transparent conductive layer 33, a lower reflector 45, and a metal layer 47 ). The semiconductor laminated structure 30 includes a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29.

The substrate 21 may be, for example, a sapphire substrate, a silicon carbide substrate, or a silicon substrate, but is not limited thereto. The substrate 21 may be a growth substrate for growing a gallium nitride compound semiconductor layer.

The first conductivity type semiconductor layer 25 is located on the substrate 21 and the second conductivity type semiconductor layer 29 is located on the first conductivity type semiconductor layer 25, The active layer 27 is interposed between the two-conductivity-type semiconductor layers. The first conductive semiconductor layer 25, the active layer 27 and the second conductive semiconductor layer 29 may be formed of a gallium nitride compound semiconductor material, that is, (Al, In, Ga) N. The compositional element and the composition ratio are determined so that the active layer 27 emits light of a desired wavelength, for example, ultraviolet light or visible light.

The first conductive semiconductor layer 25 may be an n-type nitride semiconductor layer, the second conductive semiconductor layer 29 may be a p-type nitride semiconductor layer, or vice versa.

As shown in the figure, the first conductive semiconductor layer 25 and / or the second conductive semiconductor layer 29 may be formed as a single layer or may have a multi-layer structure. In addition, the active layer 27 may have a single quantum well structure or a multiple quantum well structure. A buffer layer 23 such as GaN or AlN may be interposed between the substrate 21 and the first conductivity type semiconductor layer 25. The semiconductor layers 25, 27 and 29 may be formed using MOCVD or MBE techniques.

Meanwhile, the semiconductor laminated structure 30 includes a plurality of mesa structures M1 and M2 separated by a separation region SR. The mesa structures M 1 and M 2 may include the second conductivity type semiconductor layer 29 and the active layer between the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 29 27). That is, the second conductive semiconductor layer 29 and the active layer 27 are divided by the isolation region SR to form a plurality of mesa structures M1 and M2. The upper surface of the first conductive semiconductor layer 25 is exposed by the isolation region SR.

The plurality of mesa structures M1 and M2 may have the same shape. For example, as shown in FIG. 1, the two mesa structures M1 and M2 may have a symmetrical structure with respect to the isolation region SR. In this embodiment, two mesa structures M1 and M2 are illustrated, but the present invention is not limited thereto and may include two or more mesa structures.

The mesa structures M1 and M2 may include a plurality of through holes 30a through the second conductive semiconductor layer 29 and the active layer 27 to expose the first conductive semiconductor layer 25, Respectively. The plurality of through holes 30a are linearly arranged along the first electrode extension portions 37a as shown in FIG.

On the other hand, the transparent conductive layer 33 may be positioned on the second conductive type semiconductor layer 29. The transparent conductive layer 33 may be formed of a transparent oxide such as ITO or Ni / Au and is ohmically contacted with the second conductive type semiconductor layer 29.

Meanwhile, as shown in FIG. 2A, the first electrode pad 37 is located on the second conductive semiconductor layer 29 of the semiconductor laminated structure 30. The first electrode pad 37 may include a plurality of electrode pads 37 disposed on the mesa structures M1 and M2. These electrode pads may be connected to each other by, for example, an electrode extension portion 37c. On the other hand, the first electrode extensions 37a extend from the first electrode pad 37. The first electrode pad 37 is insulated from the semiconductor multilayer structure 30 and electrically connected to the first conductive semiconductor layer 25 through the first electrode extensions 37a. The first electrode extension portions 37a are connected to the first conductive semiconductor layer 25 exposed through the plurality of through holes 30a.

Meanwhile, the first electrode extension portion 37b may be connected to the first conductive semiconductor layer 25 exposed in the isolation region SR. The first electrode extension 37b is electrically connected to the first electrode pad 37.

The first conductive semiconductor layer 25 is exposed by the isolation region SR and the first electrode extension portion 37b exposes the first conductive semiconductor layer 25 in the isolation region SR, Layer 25 as shown in FIG. A dot pattern 31c formed of an insulating material is disposed between the first conductive type semiconductor layer 25 and the first electrode extension portion 37b to partially overlap the first electrode extension portion 37b with the first conductive type Is separated from the semiconductor layer (25). The first electrode extension portion 37b is not continuously connected to the first conductivity type semiconductor layer 25 by the dot pattern 31c but is connected in a plurality of dot regions spaced apart from each other, It is possible to mitigate the concentration of the current around the second electrode 37b. The dot pattern 31c includes a plurality of dots, as shown in Fig. 1, and has a width wider than the width of the first electrode extension portion.

On the other hand, the second electrode pad 39 may be located on the transparent conductive layer 33. The second electrode pad 39 may include a plurality of electrode pads 39 positioned on the mesa structures M1 and M2. In addition, the second electrode extension portions 39a can extend from the second electrode pad 39. [ The second electrode pad 39 and the second electrode extensions 39a may be connected to the transparent conductive layer 33.

On the other hand, the protective insulating layer 35 is located on the semiconductor laminated structure 30 and covers the semiconductor laminated structure 30. The protective insulating layer 35 may cover the transparent conductive layer 33. The protective insulating layer 35 may be interposed between the first electrode pad 37 and the second conductive semiconductor layer 29 to separate the first electrode pad 37 from the second conductive semiconductor layer 29 And the first electrode extension portions 37a may be interposed between the first electrode extension portions 37a and the second conductivity type semiconductor layer 29 to separate the first electrode extension portions 37a from the second conductivity type semiconductor layer 29 have. The protective insulating layer 35 covers the side walls of the plurality of through holes 30a and insulates the first electrode extending portions 37a from the side walls. The protective insulating layer 35 may also separate the first electrode extension 37b from the second conductive type semiconductor layer 29. [

The first functional layer 31a is formed in the form of a dot pattern on the protective insulating layer 35 and the second conductive type semiconductor layer 29 under the first electrode pad 37 and the first electrode extension portions 37a, Respectively. The first functional layer 31a may be a reflector having a reflectance of 50% or more, for example, a distributed Bragg reflector. The distributed Bragg reflector may be formed by alternately laminating insulating layers having different refractive indices such as SiO2 / TiO2 or SiO2 / Nb2O5. By forming the first functional layer 31a with a reflector having a reflectance of 50% or more, it is possible to reflect light directed toward the first electrode pad 37 and the first electrode extensions 37a, thereby reducing light loss. The first functional layer 31a is formed of a distributed Bragg reflector so that the first functional layer 31a together with the protective insulation layer 35 protects the first electrode pad 37 from the semiconductor laminated structure 30 ) From the insulating layer.

In addition, the second functional layer 31b may be located between the transparent conductive layer 33 and the second conductive type semiconductor layer 29. The second functional layer 31b is limited below the second electrode pad 39 and the second electrode extensions 39a and the transparent conductive layer 33 covers the second functional layer 31b, And is connected to the conductive semiconductor layer 29.

The second functional layer 31b may function as a current blocking layer and / or a reflector. For example, the second functional layer 31b may be formed of an insulating material, and may extend from the second electrode pad 39 and the second electrode extensions 39a through the transparent conductive layer 33, It is possible to prevent current from flowing to the layer 29. Accordingly, concentration of currents around the second electrode pad 39 and the second electrode extensions 39a can be mitigated to enhance the current dispersion performance. The second functional layer 31b may also be formed of a reflector having a reflectance of 50% or more, and the reflector may include a metal reflector or a distributed Bragg reflector. Particularly, when the second functional layer 31b is a distributed Bragg reflector in which insulating layers having different refractive indexes are alternately stacked, a function as a current block layer and a function as a reflector can be simultaneously performed. Furthermore, the second functional layer 31b may be formed of the same material as the first functional layer 31a. Furthermore, the above-described dot pattern 31c may also be formed of the same material as these functional layers 31a and 31b.

Meanwhile, the lower reflector 45 may be a distributed Bragg reflector. The lower distributed Bragg reflector 45 is formed by alternately laminating insulating layers having different refractive indexes, and is formed of light in the blue wavelength region, for example, light generated in the active layer 27 as well as light in the yellow wavelength region and / Or in the red wavelength region, and preferably has a reflectance of 90% or more. Further, the lower distribution Bragg reflector 45 may have a reflectance of 90% or more as a whole over a wavelength range of 400 to 700 nm, for example.

A lower distributed Bragg reflector 45 having a relatively high reflectance over a wide wavelength region is formed by controlling the respective optical thicknesses of the repeated stacked material layers. The lower distributed Bragg reflector 45 may be formed, for example, by alternately laminating a first layer of SiO ₂ and a second layer of TiO ₂ , or alternatively by alternating between a first layer of SiO ₂ and a second layer of Nb ₂ O ₅ And may be formed by laminating. It is more preferable to alternately laminate the first layer of SiO ₂ and the second layer of Nb ₂ O ₅ because the light absorptance of Nb ₂ O ₅ is relatively smaller than that of TiO ₂ . As the number of layers in the first layer and the second layer increases, the reflectance of the distributed Bragg reflector 45 becomes more stable. For example, the number of layers of the distributed Bragg reflector 40 may be 50 or more, that is, 25 or more.

It is not necessary that the first layers or the second layers alternately stacked have the same thickness and the first layers and the second layers are formed so as to have a relatively high reflectance for the wavelengths of light generated in the active layer 27 as well as for other wavelengths in the visible region The thickness of the two layers is selected. In addition, a plurality of distributed Bragg reflectors having a high reflectance for a specific wavelength band may be laminated to form the lower distributed Bragg reflector 45.

By adopting the lower distribution Bragg reflector 45, not only the light generated in the active layer 27 but also the light incident on the substrate 21 from the outside can be reflected again and emitted to the outside.

Also, a metal layer 47 may be located below the bottom distributed Bragg reflector 45. The metal layer 47 may be formed of a reflective metal such as aluminum to reflect light transmitted through the lower distributed Bragg reflector 45, but may be formed of a metal other than the reflective metal. Furthermore, the metal layer 47 helps to release the heat generated in the laminated structure 30 to the outside, and improves the heat dissipation performance of the light emitting diode chip 102.

According to the present embodiment, the first electrode pad 37 is located above the second conductivity type semiconductor layer 29 of the semiconductor laminated structure 30. [ Therefore, it is not necessary to etch the second conductive type semiconductor layer 29 and the active layer 27 to form the first electrode pad 37, thereby reducing the light emitting area. Further, since the first electrode extension portions 37a are connected to the first conductivity type semiconductor layer 25 through the plurality of through holes 30a, the decrease in the light emission area due to the formation of the first electrode extension portions 37a can be alleviated can do. Furthermore, since the first electrode extension portions 37a are continuously connected in a dot pattern without being connected to the first conductivity type semiconductor layer 25, concentration of current around the first electrode extension portions 37a is alleviated .

Further, according to this embodiment, the plurality of mesa structures M1 and M2 are separated from each other and located on the first conductive type semiconductor layer 25. Therefore, when the light emitting diode chip is driven under a high current, the electric current is distributed to the respective mesa structures M1 and M2. Therefore, it is possible to prevent a decrease in external quantum efficiency due to current concentration at a specific position of the semiconductor laminated structure 30. [ In particular, even if there is a defect in one mesa structure, it is possible to mitigate the flow of high current through such a defect, thereby preventing a decrease in external quantum efficiency of the large area light emitting diode chip.

Hereinafter, a method of manufacturing the light emitting diode chip will be briefly described.

First, epitaxial layers 25, 27, 29 are grown on a substrate 21. [ The buffer layer 23 may be formed before growing the epi layers. Next, the second conductive semiconductor layer 29 and the active layer 27 are patterned to form a semiconductor laminated structure 30 having a plurality of mesa structures M1 and M2. At this time, the plurality of through holes 30a are formed together, and the isolation region SR is formed to separate the mesa structures M1 and M2.

Thereafter, a first functional layer 31a and a second functional layer 31b are formed on the second conductive type semiconductor layer 29. In addition, the dot pattern 31c may be formed together. The first functional layer 31a may be formed in a dot pattern and may include a region where the first electrode pad 37 is to be formed and a region between the plurality of through holes 30a, 29). The second functional layer 31b is formed along a region where the second electrode pad 39 and the second electrode extensions 39a are to be formed. The dot pattern 31c is formed on the first conductive type semiconductor layer 25 exposed in the isolation region SR. As shown in Fig. 1, the dots of the dot pattern 31c are located on the first conductivity type semiconductor layer and spaced apart from the second conductivity type semiconductor layer and the active layer. The first functional layer 31a and the second functional layer 31b may be formed of an insulating material or a reflective material and may be formed of a distributed Bragg reflector. The first and second functional layers 31a and 31b may be formed before the semiconductor laminated structure 30 of the mesa structure is formed.

Thereafter, a transparent conductive layer 33 covering the second functional layer 31b and connected to the second conductive type semiconductor layer 29 is formed on the second conductive type semiconductor layer 29. At this time, the first functional layer 31a is not covered with the transparent conductive layer 33 but is exposed.

Thereafter, a protective insulating layer 35 covering the transparent conductive layer 33, the first functional layer 31a, and the plurality of through holes 30a is formed. On the other hand, the protective insulating layer 35 in the plurality of through holes 30a is etched to expose the first conductivity type semiconductor layer 25. In addition, the protective insulating layer 35 on the second functional layer 31b is etched to expose the transparent conductive layer 33. The protective insulating layer 35 may cover the sidewalls of the mesa structures M1 and M2 located on both sides of the isolation region SR.

The first electrode pad 37, the second electrode pad 39, the first electrode extensions 37a, 37b, and 37c, and the second electrode extensions 39a are formed. The first electrode pad 37 is formed on the protective insulating layer 35 and may be formed on the first functional layer 31a. On the other hand, the first electrode extension portions 37a cover the plurality of through holes 30a arranged in a line shape and connect to the first conductivity type semiconductor layer 25. On the other hand, the first electrode extension portion 37b is formed in the isolation region SR and covers the dot pattern 31c. The first electrode extensions 37a and 37b may be connected to the first electrode pad 37 through the first electrode extensions 37c and the plurality of first electrode pads may be connected to the mesa structures M1 and M2 , And the first electrode pads 37 may be electrically connected to each other through the first electrode extensions 37c. The first electrode extensions 37c may be disposed at the edges of the mesa structures M1 and M2. In this case, the first electrode extensions 37c may also be partially connected to the first conductivity type semiconductor layer 25 . The first electrode extension portions 37c may be formed in portions of the mesa structure M1 and M2 except for the second conductivity type semiconductor layer 29 and the active layer 27 in place of the through holes 30a, It can be connected to the semiconductor layer. That is, the portion of the through hole 30a through which the first electrode extension portions 37c are connected to the first conductivity type semiconductor layer 25 may have a shape opened to the outside of the mesa structures M1 and M2.

The second electrode pad 39 and the second electrode extensions 39a are formed on the transparent conductive layer 33 and formed on the second functional layer 31b.

Thereafter, a lower reflector 45 and a metal layer 47 are formed on the lower surface of the substrate 21, and then the light emitting diode chip is completed by dividing the lower reflector 45 and the metal layer 47 into individual light emitting diode chips.

In the present embodiment, the dot pattern 31c is formed by the same process as the first functional layer 31a and the second functional layer 31b, but the dot pattern 31c may be omitted. In this case, after the protective insulating layer 31c covering the isolation region SR is formed, the protective insulating layer 35 in the isolation region SR is partially etched to expose the first conductivity type semiconductor layer 25 By forming the plurality of openings, it is possible to form an insulating pattern that partially separates the first electrode extension portion 37b from the first conductivity type semiconductor layer 25.

FIG. 3 is a schematic plan view for explaining a light emitting diode chip according to another embodiment of the present invention, and FIGS. 4A, 4B, 4C and 4D are sectional views taken along the cut lines A-A, B-B, C-C and D-D in FIG.

3, 4A, 4B, 4C, and 4D, the light emitting diode chip according to the present embodiment is substantially similar to the light emitting diode chip described above, so that the same elements will not be described in detail in order to avoid redundancy. Explain.

First, as shown in Fig. 4A, the first electrode pad 37 is directly located on the first functional layer 51a. That is, the protective insulating layer 35 between the first electrode pad 37 and the first functional layer 51a is removed. In addition, the protective insulating layer 35 between the first electrode extension portions 37a and the semiconductor laminated structure 30 is also removed. Here, the first functional layer 51a may be formed of an insulating material, and may be formed of a distributed Bragg reflector. The second functional layer 31b may be formed of the same material as the first functional layer 51a by the same process.

On the other hand, in the plurality of through holes 30a, the first electrode extensions 37a are separated from the side walls in the through holes 30a by the first functional layer 51a. That is, the first functional layer 51a located on the second conductivity type semiconductor layer 29 in the regions between the plurality of through holes 30a extends into the plurality of through holes 30a to cover the side walls. Meanwhile, the sidewalls located on both sides of the first electrode extension part 37a in a part of the sidewalls, that is, the plurality of through holes 30a, may be covered with the protective insulation layer 35. [

The opening portions formed in the protective insulating layer 35 are formed in a region that exposes the transparent conductive layer 33 and a region in which the first conductivity type semiconductor layer 25). Of these, the region for exposing the transparent conductive layer 33 corresponds to the region where the second electrode pad 39 and the second electrode extensions 39a are formed, but the region for exposing the first conductivity type semiconductor layer 25 The regions do not correspond to the first electrode pad 37 and the first electrode extensions 37a and 37b. Therefore, when the first and second electrode pads 37 and 39 and the first and second electrode extensions 37a, 37b, 37c, and 39a are simultaneously formed using a lift-off technique, The first and second electrode pads 37 and 39 and the first and second electrode extensions 37a and 37b and 37c and 39a are formed by using a photomask, ).

However, according to the present embodiment, the shape of the first and second electrode pads 37 and 39 and the first and second electrode extensions 37a, 37b, 37c and 39a is formed in the protective insulating layer 35 The first and second electrode pads 37 and 39 and the first and second electrode extensions (i.e., the first and second electrode pads 37 and 39) are formed by using the same photomask as the photomask for patterning the protective insulating layer 35 37a, 37b, 37c, and 39a. Further, after the opening pattern is formed using the photoresist in the protective insulating layer 35, the first and second electrode pads 37 and 39 and the first and second electrode pads 37 and 39, Portions 37a, 37b, 37c, and 39a may be formed. Accordingly, it is possible to reduce the number of photomasks required for fabricating the LED chip, and further reduce the number of photographs and development processes for forming the photoresist pattern.

5A, 5B and 5C are cross-sectional views illustrating a light emitting diode chip according to another embodiment of the present invention. Here, the respective figures correspond to the sectional views taken along the perforations A-A, B-B and C-C of Fig. In the present embodiment, the sectional view taken along the perforated line D-D in Fig. 1 is the same as the corresponding sectional view of this embodiment, and therefore, the drawing is omitted.

5A, 5B, and 5C, the light emitting diode chip according to the present embodiment is substantially similar to the light emitting diode chip described with reference to FIGS. 1 and 2, except that the transparent conductive layer 33 is electrically connected to the first electrode pad 37 And the region between the first electrode extension portion 37a and the second conductivity type semiconductor layer 29 and the region between the first electrode extension portion 37a and the second conductivity type semiconductor layer 29 are different from each other. The transparent conductive layer 33 may extend to a region between the first electrode extension portion 37c and the second conductive type semiconductor layer 29. [

That is, in the above embodiments, the transparent conductive layer 33 is not formed on the region of the second conductivity type semiconductor layer 29 under the first electrode pad 37 and the first electrode extensions 37a and 37c In this embodiment, the transparent conductive layer 33 is also located in this region. The transparent conductive layer 33 is connected to the first electrode pad 37 and the second conductivity type semiconductor layer 29 under the first electrode extensions 37a and 37c so that current flows in the semiconductor laminated structure 30). ≪ / RTI >

The first electrode pad 37 and the first electrode extensions 37a and 37c are insulated from the transparent conductive layer 33 by the protective insulating layer 35 and further pass through the protective insulating layer 35, The first functional layer 61a may be positioned between the layers 33. [

In the present embodiment, the first functional layer 61a and the second functional layer 31b are formed by separate processes. That is, after the transparent conductive layer 33 is formed to cover the second functional layer 31b, the first functional layer 61a is formed on the transparent conductive layer 33 again.

6A, 6B and 6C are cross-sectional views illustrating a light emitting diode chip according to another embodiment of the present invention. Here, the respective figures correspond to the cross-sectional views taken along the perforations A-A, B-B and C-C of Fig. In the present embodiment, the sectional view taken along the perforation line D-D in Fig. 3 is the same as the corresponding sectional view of this embodiment, and therefore, the drawing is omitted.

6A, 6B and 6C, the light emitting diode chip according to the present embodiment is substantially similar to the light emitting diode chip described with reference to FIGS. 3 and 4, except that the transparent conductive layer 33 is electrically connected to the first electrode pad 37 And the region between the first electrode extension portion 37a and the second conductivity type semiconductor layer 29 and the region between the first electrode extension portion 37a and the second conductivity type semiconductor layer 29 are different from each other. The transparent conductive layer 33 may extend to a region between the first electrode extension portion 37c and the second conductive type semiconductor layer 29. [

3, the transparent conductive layer 33 is not formed on the region of the second conductivity type semiconductor layer 29 under the first electrode pad 37 and the first electrode extensions 37a and 37c In this embodiment, the transparent conductive layer 33 is also located in this region. The transparent conductive layer 33 is connected to the first electrode pad 37 and the second conductivity type semiconductor layer 29 under the first electrode extensions 37a and 37c so that current flows in the semiconductor laminated structure 30). ≪ / RTI >

The first electrode pad 37 and the first electrode extensions 37a and 37c are insulated from the transparent conductive layer 33 by the first functional layer 71a.

In the present embodiment, the first functional layer 61a and the second functional layer 31b are formed by separate processes. That is, after the transparent conductive layer 33 is formed to cover the second functional layer 31b, the first functional layer 71a is formed on the transparent conductive layer 33 again.

7 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention.

Referring to FIG. 7, the light emitting diode chip according to the present embodiment is substantially similar to the light emitting diode chip described with reference to FIGS. 1 and 2, except that the second functional layer 71b includes a second electrode pad 39 and a second And are arranged in a dot pattern along the electrode extension portion 39a.

That is, the second functional layers 71b are arranged in a dot pattern instead of a continuous line shape. On the other hand, the transparent conductive layer 33 covers the second functional layer 71b, and is also connected to the second conductivity type semiconductor layer 29 in the region between the dots.

The arrangement of the second functional layers 71b in a dot pattern is not limited to the embodiments shown in Figs. 1 and 2 but may be applied to the embodiment shown in Figs. 3 and 4, the embodiment shown in Fig. 5, and the embodiment shown in Fig. .

8 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention.

8, the light emitting diode chip according to the present embodiment is substantially similar to the light emitting diode chip described with reference to FIGS. 1 and 2, except that the second functional layer 81b is formed on the transparent conductive layer 33, The electrode pad 39 and the second electrode extension 39a are arranged in a dot pattern.

That is, the second functional layer 81b is arranged in a dot pattern between the transparent conductive layer 33 and the second electrode pad 30, and between the transparent conductive layer 33 and the second electrode extending portions 39a. The second electrode extensions 39a connect to the transparent conductive layer 33 in the region between the dots.

The second functional layer 81b according to the present embodiment is not limited to the embodiment shown in Figs. 1 and 2, but may be applied to the embodiment shown in Figs. 3 and 4, the embodiment shown in Fig. 5, have. 5 and FIG. 6, the first functional layers 61a and 71a and the second functional layer 81b may be formed on the transparent conductive layer 33 in the same process.

9 is a schematic plan view illustrating a light emitting diode chip according to another embodiment of the present invention.

Referring to FIG. 9A, the LED chip according to the present embodiment is electrically isolated from the first electrode pads 37, unlike the previous embodiments. That is, although the first electrode pads 37 and 39 located on the mesa structures M1 and M2 are electrically connected by the first electrode extension portion 37c in the above embodiments, In the example, the first electrode pads 37 are electrically separated from each other.

Referring to FIG. 9 (b), in the LED chip according to the present embodiment, a part of the first electrode pad 37 is located in the isolation region SR, unlike the previous embodiments. The remaining portion of the first electrode pad 37 is located on the mesa structures M1 and M2. In this embodiment, the two mesa structures M1 and M2 can share the first electrode pad 37, and thus the number of the first electrode pads 37 can be reduced. The first electrode extension 37b in the isolation region SR may be directly connected to the first electrode pad 37. [

Various embodiments and variations are also possible, including two or more multiple mesa structures M1, M2. A first electrode pad and a second electrode pad are disposed on each of the mesa structures, and the first electrode pads may be electrically connected or disconnected from each other. Also, the second electrode pads may be electrically connected or disconnected from each other. have.

FIG. 10 is a plan view illustrating a light emission pattern actually measured in order to explain the improvement in luminescence characteristics as a plurality of mesa structures are adopted. 10 (a) shows a light emission pattern of a light emitting diode chip in which a first electrode extension portion and a second electrode extension portion are formed in a single mesa structure, and FIG. 10 (b) (Example) having mesa structures M1 and M2 completely separated into regions. In addition, the closer to the red color the more light is emitted, the closer the blue color indicates the less light emission, and the black color indicates the area without light emission.

The light emitting diode chip of Fig. 10 (a) is a single mesa structure without the mesa structure being separated, and the light emitting diode chip of Fig. 10 (b) has the mesa structures separated by the isolation region SR. The electrode pads 37 and 39 and the electrode extensions 37a and 37b are arranged similarly to the light emitting diode chips but the light emitting diodes 30a and 30b of FIG. 10 (b) completely separated by the two mesa structures M1 and M2 It can be seen that the diode chip exhibits a uniform light emission pattern in a wider area than the light emitting diode chip of Fig. 10 (a) and also emits more light.

21: substrate, 23: buffer layer, 25: first conductivity type semiconductor layer,
27: active layer, 29: second conductivity type semiconductor layer, 30: semiconductor laminated structure,
30a: through hole, 31a, 51a, 61a, 71a: first functional layer,
31b, 71b, 81b: second functional layer, 31c: dot pattern, 33: transparent conductive layer,
35: protective insulating layer, 37: first electrode pad,
37a, 37b, 37c: a first electrode extending portion, 39: a second electrode pad,
39a: second electrode extension portion, 45: lower reflector, 47: metal layer,
M1, M2: mesa structure, SR: isolation region

Claims (22)

Board;
A first conductive semiconductor layer disposed on the substrate;
A plurality of mesa structures located on the first conductivity type semiconductor layer, each including a second conductivity type semiconductor layer and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
A first electrode pad at least partially disposed on the second conductive type semiconductor layer so as to face the first conductive type semiconductor layer;
A part of the first conductive type semiconductor layer is located on the second conductive type semiconductor layer opposite to the first conductive type semiconductor layer and has the same layer structure as the first electrode pad and extends from the first electrode pad, A first electrode extension connected to the first electrode extension;
A second electrode pad electrically connected to the second conductivity type semiconductor layer;
An insulating layer interposed between the first electrode pad and the second conductive type semiconductor layer;
A lower reflector disposed under the substrate opposite to the first conductive type semiconductor layer;
A transparent conductive layer on the second conductive type semiconductor layer; And
And a current blocking layer positioned between the second conductivity type semiconductor layer and the transparent conductive layer,
Wherein the current blocking layer is disposed in a region overlapping with the second electrode pad in a plan view,
Wherein the transparent conductive layer is in contact with the second conductive type semiconductor layer in a region that does not overlap with the second electrode pad in a plan view. The method according to claim 1,
Wherein the lower reflector comprises a distributed Bragg reflector. The method of claim 2,
And a reflective metal layer disposed under the lower reflector so as to face the substrate. The method according to claim 1,
And the second electrode pad includes a plurality of electrode pads respectively positioned on the plurality of mesa structures. The method of claim 4,
Wherein the first electrode pad includes a plurality of electrode pads respectively positioned on the plurality of mesa structures. The method according to claim 1,
Wherein the plurality of mesa structures are separated by an isolation region exposing the first conductive type semiconductor layer. The method of claim 6,
Wherein the first electrode extension portion includes an electrode extension portion connected to the first conductivity type semiconductor layer in the isolation region. The method of claim 7,
And a dot pattern interposed between the electrode extension part and the first conductivity type semiconductor layer along the electrode extension part in the isolation region and partially separating the electrode extension part from the first conductivity type semiconductor layer. . The method of claim 8,
Wherein the dot pattern is formed of an insulating material. The method of claim 8,
Wherein the dot pattern includes a distributed Bragg reflector. The method of claim 6,
Wherein the first electrode pad includes an electrode pad partially located within the isolation region. The method according to claim 1,
Wherein the insulating layer comprises a distributed Bragg reflector. The method according to claim 1,
The mesa structures each include a plurality of through holes exposing the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer,
Wherein the first electrode extension portion includes an electrode extension portion connected to the first conductivity type semiconductor layer through the plurality of through holes. 14. The method of claim 13,
And an insulating layer interposed between the electrode extension part connected to the first conductive type semiconductor layer through the plurality of through holes and the second conductive type semiconductor layer. 15. The method of claim 14,
Wherein the insulating layer interposed between the electrode extension portion connected to the first conductive type semiconductor layer through the plurality of through holes and the second conductive type semiconductor layer includes a distributed Bragg reflector. 15. The method of claim 14,
The insulating layer interposed between the electrode extension portion connected to the first conductive type semiconductor layer and the second conductive type semiconductor layer through the plurality of through holes extends to the side wall of the through holes, And the light emitting diode chip is insulated from the side wall of the hole. 15. The method of claim 14,
And a transparent conductive layer interposed between the second conductive type semiconductor layer and the insulating layer below the electrode extension portion connected to the first conductive type semiconductor layer through the plurality of through holes. The method according to claim 1,
Further comprising a second electrode extension extending from the second electrode pad,
Wherein the second electrode pad and the second electrode extension are electrically connected to the second conductivity type semiconductor layer through the transparent conductive layer. 19. The method of claim 18,
Wherein the current blocking layer is disposed in a line or dot pattern between the transparent conductive layer and the second conductive type semiconductor layer along the second electrode extension portion. The method of claim 19,
Wherein the current blocking layer comprises a reflector. The method of claim 20,
Wherein the reflector is a distributed Bragg reflector. 19. The method of claim 18,
And the current blocking layer is interposed in a dot pattern between the second electrode extension part and the transparent conductive layer along the second electrode extension part.

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