KR101907413B1 - System for effective clock synchronization and method of synchronization - Google Patents

Abstract

Disclosed are a system capable of efficiently performing clock synchronization and a synchronization method thereof. According to an embodiment of the present invention, the system capable of efficiently performing clock synchronization comprises: a clock; a first device receiving a clock signal outputted by the clock through a first phased locked loop (PLL); a second device receiving the clock signal outputted by the clock through a second PLL; a first delay module interposed between the clock and the first device to deliver the clock signal wherein the clock signal includes a plurality of first delay paths generated so that different time delays can occur; and a second delay module interposed between the clock and the second device to deliver the clock signal wherein the clock signal includes a plurality of second delay paths generated so that different time delays can occur. The system selects any one first selection path among the first delay paths and any one second selection path among the second delay paths to perform synchronization of the first and second devices.

Description

[0001] The present invention relates to a system and a synchronization method,

The present invention relates to clock synchronization and relates to enabling efficient synchronization between two devices at low cost.

There are various devices whose operation is controlled by a clock signal.

In a system including a plurality of such devices, there is a need for time synchronization between a plurality of devices.

An example of this is shown in a stereo camera with two image sensors (e.g., a CIS: CMOS Image Sensor).

1 is a diagram for explaining a method of synchronizing timing between devices in a conventional system.

Referring to Figure 1, a conventional system 10 (e.g., a stereo camera) has two image sensors 1, 2.

In such a system 10, it may be very important to synchronize the output times of two devices (e.g., image sensors such as 1, 2, e.g., a CMOS Image Sensor (CIS)). Synchronization between the devices 1 and 2 may be achieved by synchronizing the outputs of the clocks 3 and 4 corresponding to the devices 1 and 2, respectively. The devices 1 and 2 may also include PLLs 1-1 and 2-1 for adjusting the phase of the clock signal, respectively.

If the time synchronization between the devices 1 and 2 in the system 10 is not suitable, there is a great need for time synchronization depending on the type of the system 10, such as generating a large error in three-dimensional position measurement of a moving object .

Therefore, the conventional system 10 receives the external trigger signal output from the trigger signal generator 5, and determines the time at which each of the devices 1 and 2 starts a specific operation as a trigger event and a specific event of the clock signal , A rising edge or a falling edge).

However, this method can obtain accurate results from the viewpoint of matching the outputs of the devices 1 and 2, but can not use the maximum output speeds outputted by the devices 1 and 2. That is, there is a problem that each device 1 and 2 includes a time for waiting for an external trigger signal every predetermined period (for example, every frame), so that the specification maximum value of each of the devices 1 and 2 can not be used If the sensor is capable of outputting 60 frames at a resolution of 640x480, the output will be degraded to 45 frames when operated with an external trigger).

Korean Patent Publication No. 10-2012-0138183, "Device for Generating Stereoscopic Image"

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an effective synchronization system and method for reducing the performance degradation while synchronizing a plurality of devices at low cost.

According to an aspect of the present invention, there is provided a system for efficiently performing clock synchronization, including a clock, a first apparatus for receiving a clock signal output from the clock through a first PLL (Phased Locked Loop) A second device for receiving the clock signal output through the second PLL, a second device for receiving the clock signal between the clock and the first device, And a plurality of second delay paths that are located between the clock and the second device and are adapted to transfer the clock signal, wherein the clock signal is implemented to have a different time delay, Wherein the system selects any one of the plurality of first delay paths and selects one of the plurality of first delay paths, And selects any one second selected path among the plurality of second delay paths to perform the synchronization of the first device and the second device.

The system may further comprise a processor for selecting the first selected path or the second selected path.

The at least two delay paths included in the first delay paths or the second delay paths may be implemented such that the clock signal is transmitted through a different number of TTL (Transistor Transistor Logic) circuits.

One of the two delay paths may be a TTL circuit, and the other of the two delay paths may be characterized by three TTL circuits arranged in series.

The processor acquires a first sync signal output from the first device and a second sync signal output from the second device, and based on the obtained first sync signal and the second sync signal, Or the selection path of the second delay module is changed.

The first device and the second device may be image sensors, respectively.

According to an aspect of the present invention, there is provided a synchronization method performed by a system in which clock synchronization is efficiently performed, the clock signal output from a clock is supplied to a first PLL (Phased) provided in a first device through a default selection path included in a first delay module, Locked loop, the clock signal output from the clock is transferred to a second PLL included in the second device via a default selected path included in the second delay module, and the first device and the second device The clock signal propagation path of either the first delay module or the second delay module is changed to another delay path in the default selected path based on the first sync signal and the second sync signal outputted from the first sync signal and the second sync signal.

Wherein the first delay module includes a plurality of first delay paths implemented such that the clock signals have different time delays, and wherein the second delay module is operable to receive a plurality of And second delay paths.

The at least two delay paths included in the first delay paths or the second delay paths are implemented such that the clock signal is transmitted through a different number of TTL (Transistor Transistor Logic) circuits, respectively have.

Also, the default delay path may be a path in which the shortest time delay is performed in each of the first delay paths or the second delay paths.

According to the technical idea of the present invention, it is possible to use a very inexpensive (e.g., several cents) configuration (e.g., TTL circuits) to synchronize the system without complicated circuit configuration.

Also, since the external trigger signal is not used, the performance degradation of each device can be reduced and one clock can be advantageously used. Also, the difference in time delay between PLLs can be easily reduced while using the PLL.

The technical idea of the present invention can be widely used even when the output of the device using the PLL is to be synchronized.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a diagram for explaining a method of synchronizing timing between devices in a conventional system.
2 is a diagram for explaining a method of synchronizing timings between devices in accordance with an embodiment of the present invention.
3 is a diagram for explaining a method of synchronizing timings between devices according to another embodiment of the present invention.
4 is a diagram for explaining a method of synchronizing timings between devices according to another embodiment of the present invention.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

2 is a diagram for explaining a method of synchronizing timings between devices in accordance with an embodiment of the present invention.

Referring to FIG. 2, a system 100 according to an exemplary embodiment of the present invention includes a first device 110 and a second device 120. The first device 110 and the second device 120 may each include PLLs 111 and 121 for adjusting the phase of an input clock signal.

The system 100 may be a stereo camera, and the first device 110 and the second device 120 may be, but are not limited to, image sensors (CIS), respectively. That is, the technical expertise of the present invention can easily be inferred that the technical idea of the present invention can be applied to various systems requiring time synchronization between a plurality of devices equipped with a PLL.

The first PLL 111 and the second PLL 121 receive the clock signal output from the single clock 130 and adjust the phase as necessary to output the adjusted clock signal to the first device 110 and the second device 120 ). ≪ / RTI >

Theoretically, since each of the devices 110 and 120 receives the same clock signal output by the single clock 130, when outputting the same restart command 140 to each of the devices at a specific time, 110, and 120 may preferably be synchronized.

However, according to the embodiment, synchronization errors may occur due to the PLLs 111 and 121 provided in the respective devices 110 and 120. That is, since the clock signal before being input to the first PLL 111 and the second PLL 121 is the same clock signal, it may be a completely synchronized signal. However, due to differences in device characteristics and the difference between the PLLs 111 and 121, the clock signals passing through the PLLs 111 and 121 may be out of synchronization. That is, the difference in time delay occurring in each of the PLLs 111 and 121 may be different from each other, so that the accuracy of synchronization may be significantly lowered.

When the PLL is operated with a single common clock, for example, in the case where the system 100 is a stereo camera device, the synchronization is shifted at the pixel level. According to the application example, it is assumed that the error is negligible. Stereo cameras can also be commercialized. However, if precise calculations are required, this error can not be ignored and a fundamental solution may be needed.

Another embodiment of the present invention for solving such a problem will be described with reference to FIG.

3 is a diagram for explaining a method of synchronizing timings between devices according to another embodiment of the present invention.

3, a system 200 according to another embodiment of the present invention operates in a bypass mode even though a PLL is not provided or is provided in each of the devices 210 and 220 as shown in FIG. . ≪ / RTI >

That is, an external clock signal may be directly applied to the devices 210 and 220. In this case, since the clock signal applied to each of the devices 210 and 220 is the same signal, synchronization can be easily performed when the software reset (reset) command 240 is outputted.

However, in this case, since the PLL can not be used, there arises a problem that the external clock frequency is fixed to one and thus the performance of the device requiring adjustment of the phase (for example, resolution of the image sensor, control of the frame rate, etc.) .

Therefore, another embodiment of the present invention for solving the problems described in FIGS. 2 and 3 will be described with reference to FIG.

4 is a diagram for explaining a method of synchronizing timings between devices according to another embodiment of the present invention.

Referring to FIG. 4, a system 300 according to an exemplary embodiment of the present invention includes a plurality of devices (e.g., 310, 320) to be synchronized.

The first device 310 and the second device 320 may each include PLLs 311 and 321 for adjusting the phase of an input clock signal.

The system 300 may be a stereo camera, and the first device 310 and the second device 320 may be, respectively, an image sensor (CIS), as described above.

The first PLL 311 and the second PLL 321 can receive the clock signal output from the single clock 350. [

At this time, delay modules 330 and 340 may be provided between the clock 350 and the respective devices 310 and 320.

The clock signal output from the clock 350 is selectively delayed through the first delay module 330 and then transmitted to the first PLL 311. The clock signal output from the clock 350 is selectively delayed through the second delay module 340 and then transmitted to the second PLL 321.

Each delay module 330, 340 may include a plurality of delay paths (e.g., 331, 333 and 341, 343).

The first delay module 330 may include first delay paths 331, 333.

Second delay module 340 may include second delay paths 341, 343.

Although FIG. 4 shows one example in which two delay paths are provided for each of the delay modules 330 and 340, it is needless to say that a larger number of delay paths may be provided.

Each of the delay paths included in one delay module 330 or 340 is implemented such that the clock signal has a different time delay.

Also, as shown in FIG. 4, the delay times of the respective delay paths can be adjusted by a transistor transistor logic (TTL) circuit (for example, a NOT gate).

In one example, each of the first and second delay modules 330 and 340 may include two delay paths as shown in FIG. 4, one of which may be a TTL (e.g., 331- 1, and 341-1. And the other may be a path through which three TTLs (e.g., 331-1, 331-2, 331-3, and 341-1, 341-2, and 341-3) are connected in series.

Depending on the embodiment, each delay module may have more than two delay paths. Also, any one of the delay paths may be provided with a simple signal line in which no TTL is provided, that is, no time delay occurs.

In any case, if the TTL is provided in the delay path, the clock signal may be arranged to pass all the TTLs provided in the delay path.

Also, the number of TTLs arranged in each delay path may be different. According to one example, each delay path may be implemented to output the same logic signal.

For example, the first delay path 331 included in the first delay module 330 may be implemented with NOT logic as a result of the placement of a single gate. Accordingly, other delay paths 333 included in the first delay module 330 may also be implemented as NOT logic. For example, the second delay path 333 may be provided with three sickle gates, and when a third delay path (not shown) and / or a fourth delay path (not shown) is provided, , The fourth delay path may be arranged with seven sickle gates.

A path selected by a path through which a clock signal passes among a plurality of delay paths (for example, first delay paths) may be represented by a selected path.

The selected path of each of the delay modules 330 and 340 may then be selected by the processor (or microprocessor, 360).

The processor 360 may select the selected path by turning on or off each TTL circuit. For example, in order to select the first delay path 331 of the first delay module 330, the processor 360 selects only the first TTL 331-1 (turns on the clock signal to pass) and selects the other TTLs 333 -1, 333-2, 333-3, etc.) can be unselected (turned off so that the clock signal can not pass). For example, to select the second delay path 333 of the first delay module 330, the processor 360 selects all the TTLs placed in the second delay path 333, and the TTL in the remaining delay path Can be selected. In this manner, the processor 360 may select a selected path. Of course, the processor 360 may select the selected path of the second delay module 340 in the same manner.

The processor 360 may select a predetermined selected path by default. The default selected path may be a delay path with the shortest delay time of the clock signal. For example, in the example shown in FIG. 4, the default selected path of the first delay module 330 may be the first delay path 331, and the default selected path of the second delay module 340 may be the delay path 341 .

When the software reset command 370 is outputted to each of the devices 310 and 320, the PLL circuits 311 and 321 of the respective devices 310 and 320 are operated and accordingly the clock signal A specific operation (e.g., output of an image) can be performed.

At this time, as described above with reference to FIG. 2, the PLLs 311 and 321 may not be synchronized due to the difference.

For this, the processor 360 may acquire a sync signal output from each of the devices 310 and 320. For example, when each of the devices 310 and 320 is implemented as a CIS, each of the devices 310 and 320 may output VSYNCH and HSYNCH. Therefore, the sync signal may include a plurality of signals.

VSYNCH outputs a specific value every time a line of an image is changed, and HSYNCH may be a signal that outputs a specific value each time a frame of an image changes. Thus, through this sync signal, it is possible to determine which device is outputting images relatively quickly and / or how fast. The processor 360 may obtain such information based on the first sync signal output from the first device 310 and the second sync signal output from the second device 320. [

You can then change the selection path of the device that is performing the output faster.

(E.g., 320) to delay the clock signal to a relatively faster device (e.g., 320) because the default selected path is the path with the least time delay, The selection path of the delay module (e.g., the second delay module 340). It may be calculated how much the device 320 performs a particular operation at a faster timing in order to change the selected path so that it is possible to determine which path among the plurality of delay paths other than the default selected path is selected as the selected path May be determined.

Of course, depending on the embodiment, when there are only two delay paths as shown in FIG. 4, it is possible to simply select a path from a default selected path (e.g., 341) to another selected path (e.g., 343) , You may simply change the selection path.

As described above, according to the technical idea of the present invention, when a delay module is implemented, synchronization of a plurality of devices to be synchronized can be performed through a relatively inexpensive TTL circuit.

Also, when the PLL function is required, the synchronization error caused by the PLL difference can be reduced while using the PLL.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

In a system in which clock synchronization is efficiently performed,
Clark;
A first device for receiving a clock signal output from the clock through a first PLL (Phased Locked Loop);
A second device for receiving the clock signal output from the clock via a second PLL;
A first delay module positioned between the clock and the first device for transmitting the clock signal, the first delay module including a plurality of first delay paths implemented such that the clock signal has different time delays; And
And a second delay module located between the clock and the second device for transmitting the clock signal, the second delay module comprising a plurality of second delay paths implemented such that the clock signal has a different time delay,
The system comprises:
Selecting any one first selected path among the plurality of first delay paths and selecting any one second selected path among the plurality of second delay paths to synchronize the first device and the second device Lt; / RTI >
Wherein the at least two delay paths included in the first delay paths or the second delay paths comprise:
And the clock signal is transmitted through a different number of TTL (Transistor Transistor Logic) circuits,
Characterized in that one TTL circuit is arranged for one of the two delay paths and three TTL circuits are arranged in series for the other of the two delay paths. The system on which the synchronization occurs.
The system of claim 1,
Further comprising a processor for selecting the first selected path or the second selected path.
delete delete 3. The apparatus of claim 2,
A second sync signal output from the first device and a second sync signal output from the second device, and outputting the first sync signal and the second sync signal based on the obtained first sync signal and the second sync signal, 2 < / RTI > delay module is changed.
2. The apparatus of claim 1, wherein the first device and the second device comprise:
Each of which is an image sensor.
A synchronization method performed by a system in which clock synchronization is efficiently performed,
The clock signal output from the clock is transmitted to the first PLL (Phased Locked Loop) provided in the first device through the default selection path included in the first delay module, and the clock signal output from the clock is supplied to the second delay module To a second PLL included in the second device via the included default selection path;
Wherein the clock signal propagation path of either the first delay module or the second delay module is delayed by another delay in the default selection path based on the first sync signal and the second sync signal output from the first device and the second device, Path, < / RTI >
Wherein the first delay module comprises:
Wherein the clock signal comprises a plurality of first delay paths implemented to provide different time delays,
Wherein the second delay module comprises:
Wherein the clock signal comprises a plurality of second delay paths implemented to provide different time delays,
Wherein the at least two delay paths included in the first delay paths or the second delay paths comprise:
The clock signal is transmitted through a different number of TTL (Transistor Transistor Logic) circuits,
Wherein one of the two delay paths is arranged in one TTL circuit and the other of the two delay paths is arranged in three TTL circuits.
delete delete 8. The method according to claim 7,
And wherein a shortest time delay is provided in each of the first delay paths or the second delay paths.

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