KR101905755B1 - Array substrate for liquid crystal display device - Google Patents

Abstract

The present invention provides a display device comprising: a plurality of gate wirings and data wirings formed on a substrate on which a display region having a plurality of pixel regions are defined, the gate wirings and the data wirings being formed by defining a plurality of the pixel regions; A common wiring line extending apart from and spaced apart from the plurality of gate wirings; A thin film transistor formed in each of the pixel regions to be electrically connected to the gate and data lines; A plurality of pixel electrodes disposed in the pixel region in contact with the drain electrode of the thin film transistor and having a long axis in one direction; A plurality of common electrodes disposed in the pixel region in contact with the common wiring and arranged in parallel with the pixel electrodes; And a UV alignment layer formed on the common electrode and the pixel electrode. The alignment direction of the UV alignment layer is different between neighboring pixel regions.

Description

[0001] The present invention relates to an array substrate for a liquid crystal display,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device which improves display quality by implementing multiple domains to prevent a color shift phenomenon.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal due to optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

However, liquid crystal driving by an electric field which is applied to the upper and lower sides has a disadvantage that the viewing angle characteristic is not excellent.

Therefore, a transverse electric field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9, .

The common electrode 17 and the pixel electrode 30 are formed on the same plane on the lower substrate 10 and the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30 And is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field type liquid crystal display device.

2A showing the alignment state of the liquid crystal in the ON state to which the voltage is applied, the phase of the liquid crystal 11a at the position corresponding to the common electrode 17 and the pixel electrode 30 is The liquid crystal 11b located between the common electrode 17 and the pixel electrode 30 is formed by a horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, And arranged in the same direction as the horizontal electric field (L). That is, since the liquid crystal is moved by the horizontal electric field in the transverse electric field type liquid crystal display device, the viewing angle becomes wide.

Therefore, when the transverse electric field type liquid crystal display device is viewed from the front, it can be visually displayed in the direction of about 80 to 85 degrees in the up / down / left / right direction without reversal.

Referring to FIG. 2B, a horizontal electric field is not formed between the common electrode and the pixel electrode because the liquid crystal display device is in an OFF state in which no voltage is applied to the liquid crystal display device, so that the alignment state of the liquid crystal layer 11 is not changed.

3 is a plan view showing one pixel region including a switching element in a conventional substrate for a conventional lateral electric field type liquid crystal display apparatus.

As shown in the drawing, a conventional general array substrate 40 for a liquid crystal display has a plurality of gate wirings 43 arranged parallel to each other at a predetermined interval in the horizontal direction, A data line 60 which intersects the two lines 43 and 47 and which crosses the gate line 12 and defines the pixel region P, .

A thin film transistor Tr composed of a gate electrode 45, a semiconductor layer (not shown) and source / drain electrodes 53 and 55 is formed at the intersection of the gate line 43 and the data line 60. At this time, the source electrode 53 branches off from the data line 60, and the gate electrode 45 is a part of the gate line 43.

A plurality of pixel electrodes 70a and 70b electrically connected to the drain electrode through the drain electrode 55 and the drain contact hole 67 are formed in the pixel region P, And a plurality of common electrodes 49a and 49b branched from the common wiring 47 are formed.

On the other hand, in the conventional array substrate for a transverse electric field type liquid crystal display device having the above-described configuration, a color shift phenomenon occurs when viewed from the upper side, the upper side, the upper side, and the lower side because each pixel region forms a single domain.

Particularly, when viewing the image from the upper side (10 o'clock direction), the yellow color appears strongly, and when viewed from the upper side (2 o'clock side), the blue color is strongly displayed and the display quality is degraded.

Therefore, in order to solve such a problem, a transverse electric field type array substrate having two domain configurations has been proposed in which the common electrode and the pixel electrode are symmetrically bent at the center of each pixel region.

4 is a diagram showing a common electrode and a pixel electrode provided in one pixel region of a conventional array substrate for a transverse electric field type liquid crystal display having a double domain structure in one pixel region.

As shown in the drawing, a conventional array substrate for a transverse electric field type liquid crystal display having a double domain structure in one pixel region P has a common electrode 80 and a pixel electrode 83 spaced from each other in one pixel region (P) Is symmetrically bent around the central portion of each pixel region P, thereby forming a vertically symmetrical double-domain structure in one pixel region P, thereby forming a vertically symmetrical double-domain structure in which the upper, Thereby preventing the color shift phenomenon when viewed from the front.

However, as described above, in the case of the conventional transverse electric field type array substrate having two domain regions in one pixel region P, a bent portion exists in each pixel region P, and the bent portions are formed in different directions The transmissivity is reduced due to the formation of the domain boundary where the liquid crystal molecules driven by the liquid crystal molecules are driven, and the luminance characteristic is lowered.

DISCLOSURE OF THE INVENTION It is therefore an object of the present invention to provide an array substrate for a liquid crystal display capable of preventing a color shift phenomenon without deteriorating transmittance and luminance characteristics, .

According to an aspect of the present invention, there is provided an array substrate for a liquid crystal display, including: a plurality of gate electrodes formed on a substrate defining a display region having a plurality of pixel regions, Wiring and data wiring; A common wiring line extending apart from and spaced apart from the plurality of gate wirings; A thin film transistor formed in each of the pixel regions to be electrically connected to the gate and data lines; A plurality of pixel electrodes disposed in the pixel region in contact with the drain electrode of the thin film transistor and having a long axis in one direction; A plurality of common electrodes disposed in the pixel region in contact with the common wiring and arranged in parallel with the pixel electrodes; And a UV alignment layer formed on the common electrode and the pixel electrode, and the alignment direction of the UV alignment layer is different between neighboring pixel regions.

In this case, all of the pixel electrodes and the common electrodes provided in the respective pixel regions in the display region are arranged in the same direction in the same direction, and the direction in which the major axes of the pixel electrodes and the common electrodes are arranged is the length Direction.

The alignment direction may be a first angle of 2 ° to 25 ° or a second angle of 155 ° to 178 ° in a clockwise or counterclockwise direction with respect to the major axis direction of the pixel electrode.

When four pixel regions adjacent to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the order of upper left, upper right, lower left, and right lower, And the second pixel region is oriented in a second direction having the first angle in a clockwise direction with respect to a long axis of the pixel electrode, and the second pixel region is oriented in a first direction having the first angle in a counterclockwise direction with respect to the long axis of the pixel electrode, The three pixel regions are oriented in a third direction having the second angle counterclockwise with respect to the long axis of the pixel electrode, and the fourth pixel region has the second angle in the clockwise direction with respect to the long axis of the pixel electrode And is oriented in the fourth direction.

In this case, the first pixel region and the second pixel region, and the third pixel region and the fourth pixel region are oriented so as to be symmetrical to each other with reference to the data line located at the boundary between the pixel regions, The pixel region and the third pixel region, and the second pixel region and the fourth pixel region are oriented so as to be symmetrical with respect to each other with respect to the gate wiring located at the boundary between the pixel regions.

When four pixel regions adjacent to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the order of upper left, upper right, lower left, and right lower, And the second pixel region is oriented in a second direction having the first angle in a clockwise direction with respect to a long axis of the pixel electrode, and the second pixel region is oriented in a first direction having the first angle in a counterclockwise direction with respect to the long axis of the pixel electrode, The three pixel regions are oriented in the second direction having the first angle in the clockwise direction with respect to the long axis of the pixel electrode, and the fourth pixel region has the first angle in the counterclockwise direction with respect to the long axis of the pixel electrode In the first direction.

In this case, the first pixel region and the second pixel region, and the third pixel region and the fourth pixel region are oriented so as to be symmetrical with respect to each other with reference to the data line located at the boundary between the pixel regions.

According to another aspect of the present invention, there is provided an array substrate for a liquid crystal display, comprising: a plurality of gate wirings and data wirings formed to define a plurality of pixel regions intersecting with each other; A thin film transistor formed in each of the pixel regions to be electrically connected to the gate and data lines; A pixel electrode formed in the pixel region in contact with a drain electrode of the thin film transistor; A common electrode formed on the entire surface of the display region above or below the insulating layer with an insulating layer interposed therebetween above or below the pixel electrode; And a plurality of first openings having a long axis in one direction and having a bar shape in each pixel region corresponding to an electric field of any one of the pixel electrodes or the common electrode, And the alignment direction of the UV alignment layer is different between adjacent pixel regions.

In this case, the first openings of all the bar-shaped openings provided in the pixel regions in the display region are arranged in the same one direction, and the long axis of the first openings is arranged in a direction And is in the longitudinal direction.

The alignment direction may be a first angle of 2 ° to 25 ° or a second angle of 155 ° to 178 ° in a clockwise or counterclockwise direction with respect to the major axis direction of the first opening.

When four pixel regions adjacent to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the order of upper left, upper right, lower left, and right lower, Said second pixel region being oriented in a second direction having said first angle in a clockwise direction with respect to a long axis of said first aperture, said second pixel region being oriented in a first direction having said first angle in a counterclockwise direction with respect to a long axis, Wherein the third pixel region is oriented in a third direction having the second angle in a counterclockwise direction with respect to a long axis of the first aperture, the fourth pixel region is oriented in a clockwise direction with respect to the long axis of the first aperture, And is oriented in a fourth direction having two angles.

In this case, the first pixel region and the second pixel region, and the third pixel region and the fourth pixel region are oriented so as to be symmetrical to each other with reference to the data line located at the boundary between the pixel regions, The pixel region and the third pixel region, and the second pixel region and the fourth pixel region are oriented so as to be symmetrical with respect to each other with respect to the gate wiring located at the boundary between the pixel regions.

When four pixel regions adjacent to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the order of upper left, upper right, lower left, and right lower, Said second pixel region being oriented in a second direction having said first angle in a clockwise direction with respect to a long axis of said first aperture, said second pixel region being oriented in a first direction having said first angle in a counterclockwise direction with respect to a long axis, Wherein the third pixel region is oriented in the second direction having the first angle in a clockwise direction with respect to the long axis of the first aperture and the fourth pixel region is oriented in the counterclockwise direction with respect to the long axis of the first aperture And is oriented in the first direction having a first angle.

In this case, the first pixel region and the second pixel region, and the third pixel region and the fourth pixel region are oriented so as to be symmetrical with respect to each other with reference to the data line located at the boundary between the pixel regions.

In the array substrate for a liquid crystal display according to the present invention, since the multi-domain region is provided in the display region without the electrode bending in each pixel region, color deviation occurs according to the position where the image is viewed without the transmittance or the luminance, The shift phenomenon is prevented and the display quality is improved.

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.
FIGS. 2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field liquid crystal display device;
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device.
4 is a view showing a common electrode and a pixel electrode provided in one pixel region of a conventional array substrate for a transverse electric field type liquid crystal display device having a double domain structure in one pixel region;
5 is a plan view of four neighboring pixel regions of an array substrate for a liquid crystal display according to the first embodiment of the present invention.
6 is a plan view of four neighboring pixel regions of an array substrate for a liquid crystal display according to a modification of the first embodiment of the present invention;
7 is a cross-sectional view of a portion cut along line VII-VII of FIG. 6;
8 is a plan view of four neighboring pixel regions of an array substrate for a liquid crystal display according to a second embodiment of the present invention.
9 is a plan view of four neighboring pixel regions of an array substrate for a liquid crystal display according to a modification of the second embodiment of the present invention.
Fig. 10 is a cross-sectional view of a portion cut along the cutting line X-X in Fig. 8; Fig.
11 is a cross-sectional view of a pixel electrode (in the case of the first embodiment) or a first opening (in the case of the first embodiment) provided in the first, second, third and fourth pixel regions of the array substrate for a liquid crystal display according to the first and second embodiments of the present invention, (In the case of the embodiment) and the orientation direction.
12 is a sectional view of a pixel electrode (in the case of the first embodiment) or a first opening (in the second embodiment) provided in the first, second, third, and fourth pixel regions of the array substrate for a liquid crystal display according to the first and second embodiments of the present invention (In the case of the second embodiment) and the orientation direction.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

5 is a plan view of four neighboring pixel regions of the array substrate for a liquid crystal display according to the first embodiment of the present invention. In order to simplify the description, reference numerals P1, P2, P3, and P4 denote the four pixel regions, respectively, located at the upper left, upper right, upper left, lower left, and lower right. In each pixel region, The formed portion is defined as a switching region (not shown).

First, a planar configuration of an array substrate for a liquid crystal display according to a first embodiment of the present invention will be described with reference to FIG.

As shown in the drawings, the array substrate 101 for a liquid crystal display according to the first embodiment of the present invention has gate wirings 103 in the first direction for each pixel region P1, P2, P3, and P4 A data line 130 extending in a second direction and intersecting the gate line 103 defines the pixel regions P1, P2, P3, and P4.

The common lines 110 are formed through the pixel regions P1, P2, P3 and P4 and spaced apart from the gate lines 103. In each of the pixel regions P1, P2, P3 and P4, An outermost common electrode 116 that branches off from the common wiring 110 and extends in parallel and spaced apart from the data wiring 130 is formed.

A gate insulating film (not shown), a gate insulating film (not shown), a gate insulating film (not shown), a gate electrode 108, and a gate electrode 108 are formed in the pixel regions P1, P2, P3, and P4, A thin film transistor Tr including a semiconductor layer (not shown) composed of an active layer (not shown) of impurity amorphous silicon and an ohmic contact layer (not shown) of impurity amorphous silicon and source and drain electrodes 133 and 136 spaced from each other Respectively.

On the other hand, in the vicinity of the formation of the thin film transistor Tr in each of the pixel regions P1, P2, P3 and P4, the outermost common electrode 116 branched from the common wiring 110 has a wider width than the other region (Not shown), which overlaps with the first storage electrode 117 and forms the drain electrode 136. The drain electrode 136 is formed on the first storage electrode 117, The second storage electrode 139 is formed of the same metal material as the first storage electrode 136 and has an island shape. Accordingly, the first and second storage electrodes 117 and 139 overlapping each other with the gate insulating film (not shown) interposed therebetween form a storage capacitor StgC.

At this time, the width of the auxiliary pixel pattern 161, which is in contact with the drain electrode 236 of the thin film transistor Tr, is greater than the width of the other regions, thereby overlapping the second storage electrode 117, The second storage electrode 117 is exposed through the storage contact hole 149 which exposes the second storage electrode 139 provided in the second storage electrode 117. In this case,

In addition, a protective layer (not shown) is provided on the entire surface of the display region covering the thin film transistor Tr, and a protective layer (not shown) corresponding to each of the pixel regions P1, P2, P3, And a storage contact hole 149 for exposing the second storage electrode 117 connected to the drain electrode 136 of each of the thin film transistors Tr is formed on the substrate 100. The protective layer (not shown) A common contact hole 151 for exposing the common wiring 110 or the outermost common electrode 116 is provided.

An auxiliary common pattern (not shown) that contacts the outermost common electrode 116 through the common contact hole 151 is formed in the pixel regions P1, P2, P3, and P4, And a plurality of central common electrodes 165 are formed in parallel with the outermost common electrode 116 in the auxiliary common pattern 164.

In addition, the drain electrode 136 of the thin film transistor Tr is connected to the protective layer (not shown) through the first storage contact hole 149 in each pixel region P1, P2, P3, and P4 The auxiliary pixel pattern 261 is formed in parallel with the common wiring 110 and a plurality of pixel electrodes 262 are formed by branching from the auxiliary pixel pattern 261.

At this time, the center portion common electrode 165 and the pixel electrode 162 provided in the pixel regions P1, P2, P3, and P4 are arranged to alternate with each other.

Although not shown in the drawing, a UV alignment film (not shown) is provided on the central portion common electrode 165 and the pixel electrode 162 in such a manner that the side chains are aligned in one direction in response to the UV light corresponding to the display region .

The most characteristic feature of the array substrate 101 for a liquid crystal display according to the embodiment of the present invention having such a configuration is that the pixel electrode 162 and the common electrode (not shown) provided in each pixel region P1, P2, P3, And the alignment direction of the UV alignment film (not shown) provided in each of the pixel regions P1, P2, P3, and P4.

That is, the pixel electrodes 162 and the outermost and central common electrodes 116 and 165 alternately spaced from each other in the pixel regions P1, P2, P3, 130 are extended. At this time, a UV alignment film (not shown) is provided on the common electrodes 116 and 165 and the pixel electrode 162 in response to UV light. In the UV alignment film (not shown), pixel regions P1, P2, P3, and P4) are different from each other in the UV direction, and thus their alignment directions are different.

11, which schematically shows only the electrodes provided in the first, second, third, and fourth pixel regions P1, P2, P3, and P4 and the alignment direction together with FIG. 5, The state of being UV-oriented in the first direction (d1) so as to have one first angle (? 1) selected from 2 degrees to 25 degrees in the counterclockwise direction with respect to the long axis of the electrodes (116, 165) and the pixel electrode It accomplishes.

The second pixel region P2 neighboring the first pixel region P1 in the lateral direction, that is, in the extending direction of the gate wiring 103, is located at the boundary between the first and second pixel regions P1 and P2 The pixel electrode 162 and the common electrode 116 and the pixel electrode 162 are formed in the second direction so as to have a symmetrical configuration with respect to the data line 130 positioned on the common electrode 116, (d2).

The first pixel region P1 and the two pixel regions P1 and P3 are formed in the third pixel region P3 adjacent to the first pixel region P1 and the data line 130, That is, at the first angle? 1 (180 degrees) at 180 degrees in the counterclockwise direction with respect to the long axis of the common electrode 116, 165 and the pixel electrode 162 so as to be symmetrical with respect to the gate wiring 103 provided at the boundary between the common electrode And the data line 130 is connected to the third pixel region P3 in a third direction d3, which is a second angle? 2 (having a range of 155 to 178 degrees) The fourth pixel region P4 adjacent to the third pixel region P3 between the common electrode 116 and the pixel electrode 162 is symmetrical with respect to the third pixel region P3 and the data line 130, (? 2: 155 to 178 degrees) obtained by subtracting the first angle from 180 degrees in the clockwise direction And is in the UV-oriented state in the fourth direction (d4).

6 and the modified example of the first embodiment, the electrodes provided in the first, second, third, and fourth pixel regions P1, P2, P3, and P4 of the array substrate for a liquid crystal display device and the alignment direction 12, the third pixel region P3 is the same as the second pixel region P2 in a state in which the UV alignment directions of the first and second pixel regions P1 and P2 remain unchanged, The fourth pixel region P4 may be in the UV-oriented state in the second direction d2 and the fourth pixel region P4 may be in the UV-oriented state in the first direction d1, which is the same as the first pixel region P1.

Although only the first, second, third, and fourth pixel regions P1, P2, P3, and P4 adjacent to each other in the up, down, left, and right directions are shown in the first embodiment and the modification of the present invention, The pixel regions P1, P2, P3, and P4 are sequentially arranged in the order of the first, second, third, and fourth pixel regions P1, P2, P3, and P4.

The common electrodes 116 and 165 and the pixel electrodes 162 and 162 provided in the respective pixel regions P1, P2, P3 and P4 in the four pixel regions P1, P2, P3 and P4 neighboring up and down, ) Are aligned in the same direction, the liquid crystal display device having the array substrate 101 having such a configuration by changing the alignment directions of the respective UV alignment layers has a problem that when the same voltage having the same gray level is applied, Even if the user changes the azimuth angle and looks at the display area by displaying images by aligning molecules in different directions for the first, second, third, and fourth pixel regions P1, P2, P3, and P4, The color shift is not generated by the compensation between the third and fourth pixel regions P1, P2, P3, and P4.

In the case of the array substrate 101 for a liquid crystal display according to the first embodiment of the present invention and its modification having such a configuration, each of the pixel regions P1, P2, P3, and P4 has one domain region The domain boundary is not generated since there is no bending portion in the pixel electrode 162 and common electrodes 116 and 165 provided in each pixel region P1, P2, P3 and P4. Accordingly, it is possible to fundamentally suppress the occurrence of the disclination region in which the brightness is rapidly reduced in each of the pixel regions P1, P2, P3 and P4, thereby improving the transmittance and the brightness characteristic.

Hereinafter, the sectional configuration of the array substrate 101 for a liquid crystal display according to the first embodiment of the present invention having such a configuration will be briefly described.

FIG. 7 is a cross-sectional view of the portion cut along the section line VII-VII of FIG. 5; FIG. For convenience of description, a region where the thin film transistor Tr as a switching element is formed is defined as a switching region TrA, and a region where the storage capacitor StgC is formed is defined as a storage region StgA.

As shown in the drawing, a gate wiring (103 in FIG. 5) extending in one direction is formed on the substrate 101, and a common wiring 110 is formed in parallel to the gate wiring (103 in FIG. 5) have. At this time, corresponding to the switching region TrA, the gate wiring (103 in FIG. 5) itself forms a gate electrode 106 in a part of the region.

In each pixel region P, an outermost common electrode (116 in FIG. 5) is formed, which is branched from the common wiring 110 and is adjacent to the data wiring 130.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) is formed on the entire surface of the gate wiring (103 in FIG. 5), the gate electrode 106, the common wiring 110 and the outermost common electrode Or a gate insulating film 119 made of silicon nitride (SiNx) is formed.

An active layer 120a made of pure amorphous silicon and a semiconductor layer 120 composed of an ohmic contact layer 120b made of impurity amorphous silicon are formed in the switching region TrA above the gate insulating layer 119. [

A data line 130 defining each pixel region P is formed on the gate insulating film 119 so as to intersect with the gate line (103 in FIG. 5). In the switching region TrA, A source electrode 133 is formed on the data line 130 branched from the source electrode 133 and spaced apart from the source electrode 133 and a drain electrode 136 is formed.

At this time, the gate electrode 106, the gate insulating film 119, the semiconductor layer 120, and the source and drain electrodes 133 and 136, which are sequentially stacked in the switching region TrA, ).

A second storage electrode 139 is formed in an island shape corresponding to the first storage electrode 117 above the gate insulating layer 119 in the storage region StgA. At this time, the first storage electrode 117, the gate insulating layer 119, and the second storage electrode 139, which are sequentially stacked in the storage region StgA, form a storage capacitor StgC.

Next, a protective layer (not shown) made of photo acryl which is a material having a relatively low dielectric constant among the organic insulating materials on the data line 130, the source and drain electrodes 133 and 136, and the second storage electrode 139 145 are formed.

The formation of the protective layer 145 as a photo-acryl having low-dielectric-constant characteristics is a function of a parasitic capacitance generated by overlapping the data line 130 and a conductive pattern (169 in FIG. 5) made of a conductive material formed on the data line 130 And the influence of the outermost common electrode 116 formed around the data line 130 is minimized.

A common contact hole (151 in FIG. 5) exposing one end of the outermost common wiring line 110 is formed in the passivation layer 145 made of photoacrylic having such a low dielectric constant, And a storage contact hole 149 is formed to expose the second storage electrode 139 connected thereto.

Next, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (ITO) is deposited on the passivation layer 145 having the common contact hole 251 and the storage contact hole 149 A conductive pattern (169 in FIG. 5) for overlapping the data line 130 and minimizing the influence on the peripheral electrodes of the data line 130 is formed. At this time, this conductive pattern (169 in FIG. 5) is connected to the auxiliary common pattern 164 provided in each pixel region P so that a common voltage is applied.

In the pixel region P, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) or a conductive material such as molybdenum (Mo) or moly titanium (MoTi), and is in contact with the outermost common electrode 116 through the common contact hole 151 (FIG. 5) And a plurality of central portion common electrodes 165 are formed in the auxiliary common pattern 164 and spaced apart from each other in parallel to the data lines 130. [

The auxiliary common pattern 264 is formed on the protection layer 145 in each pixel region P and is electrically connected to the second storage electrode 139 through the storage contact hole 149. [ And the auxiliary pixel pattern 161 extends in parallel with the gate wiring (103 of FIG. 5). The auxiliary pixel pattern 161 branches from the auxiliary pixel pattern 161 and extends parallel to the central common electrode 165 And a plurality of pixel electrodes 162 are formed alternately at regular intervals.

The UV alignment layer 181 is formed on the entire surface of the display region on the pixel electrode 162 and the central common electrode 165. The UV alignment layer 181 is formed on the entire surface of the display region, (Not shown) of the liquid crystal display device according to the first embodiment of the present invention having such a configuration by UV-alignment in the different directions with respect to the first, second, third, and fourth pixel regions So that the color shift can be suppressed.

8 is a plan view of four neighboring pixel regions of an array substrate for a liquid crystal display according to a second embodiment of the present invention. P1, P2, P3 and P4 are assigned to the four pixel regions, respectively, located at the upper left, upper right, upper right, lower left and lower right. (Hereinafter referred to as " switching region ") is defined as a switching region (not shown).

The array substrate 201 for a liquid crystal display according to the second embodiment of the present invention is substantially an array substrate 201 for a fringe field switching mode liquid crystal display device, A plurality of gate wirings 203 are formed and a plurality of data wirings 230 that intersect the plurality of gate wirings 203 and define a plurality of pixel regions P1, P2, P3, and P4 are formed.

A thin film transistor Tr connected to the gate wiring 203 and the data wiring 230 is formed in each of the pixel regions P1, P2, P3, and P4. At this time, the thin film transistor Tr is formed by successively stacking a gate electrode 205, a gate insulating film (not shown), an active layer (not shown) of pure amorphous silicon and an ohmic contact layer (not shown) of impurity amorphous silicon, (Not shown), and source and drain electrodes 233 and 236 spaced from each other.

The first passivation layer (not shown) is provided with a first passivation layer (not shown) covering the thin film transistor Tr, and a drain contact hole 243 exposing the drain electrode 236 is provided .

In the pixel regions P1, P2, P3 and P4, a plate-shaped pixel electrode (not shown) is formed in contact with the drain electrode 236 through the drain contact hole 243 over the first passivation layer 250 are provided.

In addition, a plate-shaped pixel electrode 250 provided in each of the pixel regions P1, P2, P3, P4 (P) in the display region composed of the plurality of pixel regions P1, P2, P3, P4 And a plurality of first openings op1 spaced apart from each other by a predetermined distance in the form of a bar via a second protective layer (not shown) corresponding to the thin film transistors Tr, A common electrode 270 made of a transparent conductive material having an opening (not shown) is formed. The plurality of first openings op1 provided in the pixel regions P1, P2, P3, and P4 are arranged in parallel with the data lines 230 in the major axis.

In this case, in the array substrate 201 for a liquid crystal display according to the second embodiment of the present invention, the plurality of first openings op1 are formed on the common electrode 270. However, The opening op1 may be provided in the pixel electrode 250 having the plate shape. In this case, the positions of the common electrode 270 and the pixel electrode 250 may be changed.

Although not shown in the figure, the side chains are arranged in one direction in response to UV light corresponding to the display area on the common electrode 270 having the plurality of first openings op1 (not shown) .

The most prominent feature of the array substrate 201 for a liquid crystal display according to the second embodiment of the present invention having such a configuration is that a plurality of first openings op1 (P1, P2, P3, P4) (Not shown) provided in each of the pixel regions P1, P2, P3, and P4.

The plurality of first openings op1 in each of the pixel regions P1, P2, P3 and P4 are arranged in the same manner in all the pixel regions P1, P2, P3 and P4 in the display region, The UV alignment layer is formed in the UV alignment layer (not shown) in different directions for each of the pixel regions P1, P2, P3, and P4.

7, the first openings op1 (P1, P2, P3, P4) provided in the first, second, third and fourth pixel regions P1, P2, P3, P4 of the array substrate 201 for a liquid crystal display according to the second embodiment of the present invention, 11, which schematically shows only the alignment direction and the alignment direction, the first pixel region P1 is formed by a first angle? 1 selected from 2 degrees to 25 degrees in the counterclockwise direction with respect to the long axis of the first opening (op1) and the second pixel region P2 neighboring in the extending direction of the gate line 203 is in a state of being UV-oriented in the first direction d1 so as to have the first pixel region P1, P2 so as to form a symmetrical configuration with respect to the data line 230 located at the boundary between the first direction OP1 and the second direction OP2 so as to have the first angle? 1 clockwise with respect to the long axis of the first opening OP1, ) In a UV-oriented state.

The first pixel region P1 and the two pixel regions P1 and P3 may be formed in the third pixel region P3 adjacent to the first pixel region P1 and the data line 230, That is, a second angle (? 1) obtained by subtracting the first angle? 1 from 180 degrees in the counterclockwise direction with respect to the long axis of the first opening (op1) and the data line 230 is disposed between the third pixel region P3 and the data line 230. The first pixel region P3 and the data line 230 are arranged in a UV direction in a third direction d3, The fourth pixel region P4 is formed to be symmetrical with respect to the third pixel region P3 and the data line 230. That is, the first pixel region P4 is arranged at 180 degrees in the clockwise direction with respect to the long axis of the first opening op1. The state of being UV-oriented in the fourth direction (d4) forming the second angle (? 2: 155 to 172 degrees) And it is characterized.

9 and FIG. 9 as a modified example of the second embodiment, the first, second, third, and fourth pixel regions P1 and P2 of the array substrate 201 for a liquid crystal display according to the modified example of the second embodiment of the present invention 12, which schematically show only the first opening op1 and the alignment direction of the first and second pixel regions P1, P2 and P3, P3, P4, The third pixel region P3 is UV-oriented in a second direction d2 which is the same as the second pixel region P2 and the fourth pixel region P4 is the same as the first pixel region P1 It may be in a state of being UV-oriented in the first direction (d1).

Although only the first, second, third, and fourth pixel regions P1, P2, P3, and P4 adjacent to each other in the up, down, left, and right directions are shown in the second embodiment and its modified examples of the present invention, The pixel regions P1, P2, P3, and P4 are sequentially formed in a one-to-one correspondence with the pixel regions P1, P2, P3, and P4.

The arrangement of the long axes of the plurality of first openings op1 provided in the pixel regions P1, P2, P3, and P4 in the four pixel regions P1, P2, P3, On the other hand, in the liquid crystal display device having the array substrate 201 having such a configuration by changing the alignment direction of the UV alignment film (not shown), when the same voltage having the same gray level is applied, 2, 3 and 4 are arranged in different directions for each of the first, second, third and fourth pixel regions P1, P2, P3 and P4 so that the user can change the azimuth angle and look at the display region, , And color shift is not generated by compensation between the four pixel regions P1, P2, P3, and P4.

Also in the case of the array substrate 201 for a liquid crystal display according to the second embodiment and its modified example having such a configuration, each of the pixel regions P1, P2, P3, and P4 is a single domain region A plurality of first openings op1 provided in the pixel regions P1, P2, P3 and P4 do not have a bent portion, so that a domain boundary is not generated. Accordingly, it is possible to fundamentally suppress the occurrence of the disclination region in which the brightness is rapidly reduced in each of the pixel regions P1, P2, P3 and P4, thereby improving the transmittance and the brightness characteristic.

Hereinafter, the sectional structure of the array substrate for a liquid crystal display according to the second embodiment of the present invention having such a structure will be described.

Fig. 10 is a cross-sectional view of a portion cut along the cutting line X-X in Fig. 8; For convenience of description, a region in which the thin film transistor Tr as a switching element is formed is defined as a switching region TrA.

As shown in the figure, the array substrate 201 for a fringe field switching mode liquid crystal display according to the second embodiment of the present invention has a gate wiring (not shown) formed of a metal material having a low- (203 in FIG. 8) is formed, and a gate electrode 205 is formed in the switching region TrA in connection therewith.

A gate insulating film 210 is formed on the entire surface of the substrate 201 over the gate wiring (203 in FIG. 9) and the gate electrode 205 as an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) Respectively.

A semiconductor layer 220 including an active layer 220a of pure amorphous silicon and an ohmic contact layer 220b of impurity amorphous silicon corresponding to the gate electrode 210 in the switching region TrA above the gate insulating layer 210, And a source electrode 233 and a drain electrode 236 are formed on the semiconductor layer 220 to be spaced apart from each other. At this time, the active layer 220a is exposed between the source and drain electrodes 233 and 236 which are spaced apart from each other.

A data line 230 extending in the second direction is formed on the gate insulating layer 210 to define a pixel region P intersecting the gate line 203 (FIG. 8). At this time, the first and second semiconductor patterns 221a and 221b are formed under the data line 230 as the same material that forms the active layer 220a and the ohmic contact layer 220b. However, And may be omitted.

The source electrode 233 of the thin film transistor Tr is connected to the data line 230.

A first passivation layer 240 is formed on the entire surface of the substrate 201 as an organic insulating material such as benzocyclobutene (BCB) or photo acryl covering the data line 230 and the thin film transistor Tr, Is formed. At this time, the first passivation layer 240 has a drain contact hole 243 exposing a part of the drain electrode 236 of the thin film transistor Tr.

In addition, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is formed for each pixel region P on the first passivation layer 240 having the drain contact hole 243, A plate-shaped pixel electrode 250 is formed in contact with the drain electrode 236 through the drain contact hole 243. In this case, the pixel electrode 250 may be formed directly on the gate insulating layer 210, in direct contact with the drain electrode 236 of the thin film transistor Tr. In this case, The first passivation layer 240 having the contact hole 243 may be omitted.

A second passivation layer 260 is formed on the entire surface of the substrate 201 using the inorganic insulating material or the organic insulating material on the pixel electrode 250. The second passivation layer 260 may be formed of the transparent conductive material A common electrode 270 in the form of a plate is formed on the entire surface of the display region made up of the pixel regions P. [ At this time, the common electrode 270 has a plurality of first openings op1 corresponding to the pixel electrodes 250 formed in the pixel regions P. The plurality of first openings op1 are arranged in the pixel region P in the display region so that their major axes are aligned with the data lines 230.

 Meanwhile, in the case of the second embodiment of the present invention, in the drawing, the bar-shaped first openings op1 are spaced at equal intervals in the common electrode 270 for each pixel region P, A plurality of first openings op1 corresponding to the pixel regions P for efficient fringe field formation may be formed in a suitable number within a range of about two to ten, Deformed and formed.

The UV alignment layer 281 is formed on the common electrode 270 having the plurality of first openings op1 and the UV alignment layer 281 is formed on the first, The liquid crystal display device according to the second embodiment of the present invention having such a structure by UV-orienting in different directions with respect to the 3, 4 pixel regions (P1, P2, P3, P4 in Figs. 8 and 9) ) Can realize multiple domains in the display region without lowering the luminance and transmittance, thereby suppressing color shift.

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

101: substrate 103: gate wiring
106: gate electrode 116: outermost common electrode
117: first storage electrode 130: data wiring
133: source electrode 136: drain electrode
139: second storage electrode 149: first storage contact hole
151: common contact hole 161: auxiliary pixel pattern
162: pixel electrode 164: auxiliary common pattern
169: auxiliary pattern
d1, d2, d3, d4: the first, second, third, and fourth orientation directions of the UV alignment film
P: pixel region op1: first opening
StgC: storage capacitor Tr: thin film transistor

Claims (16)

A plurality of gate wirings and data wirings provided on a substrate on which a display region having a plurality of pixel regions are defined and defining a plurality of pixel regions intersecting with each other;
A common wiring line extending apart from and spaced apart from the plurality of gate wirings;
A thin film transistor electrically connected to the gate lines and the data lines in the pixel regions;
A plurality of pixel electrodes disposed in the pixel region in contact with the drain electrode of the thin film transistor and having a long axis in one direction;
A plurality of common electrodes disposed in the pixel region in contact with the common wiring and arranged in parallel with the pixel electrodes;
And a UV alignment layer formed on the common electrode and the pixel electrode,
And the alignment direction of the UV alignment layer is different between adjacent pixel regions,
Wherein the long axis of all of the pixel electrodes provided in each of the pixel regions in the display region and the long axis of the common electrode are all arranged in the same direction.
delete The method according to claim 1,
Wherein the direction in which the long axes of the pixel electrode and the common electrode are arranged is the longitudinal direction of the data line.
The method of claim 3,
Wherein the alignment direction forms a first angle of 2 DEG to 25 DEG or a second angle of 155 DEG to 178 DEG in a clockwise or counterclockwise direction with respect to the major axis direction of the pixel electrode Board.
5. The method of claim 4,
When four pixel regions neighboring to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the top left, top right, bottom left,
Wherein the first pixel region is oriented in a first direction having the first angle in a counterclockwise direction with respect to a long axis of the pixel electrode,
The second pixel region is oriented in a second direction having the first angle in a clockwise direction with respect to a long axis of the pixel electrode,
The third pixel region is oriented in a third direction having the second angle counterclockwise with respect to the long axis of the pixel electrode,
And the fourth pixel region is oriented in a fourth direction having the second angle in a clockwise direction with respect to the long axis of the pixel electrode.
6. The method of claim 5,
Wherein the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region are oriented so as to be symmetrical with respect to each other with respect to the data line located at the boundary,
Wherein the first pixel region, the third pixel region, the second pixel region, and the fourth pixel region are oriented so as to be symmetrical to each other with reference to the gate wiring located at the boundary between the first pixel region and the third pixel region, Board.
5. The method of claim 4,
When four pixel regions neighboring to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the top left, top right, bottom left,
Wherein the first pixel region is oriented in a first direction having the first angle in a counterclockwise direction with respect to a long axis of the pixel electrode,
The second pixel region is oriented in a second direction having the first angle in a clockwise direction with respect to a long axis of the pixel electrode,
The third pixel region is oriented in the second direction having the first angle in a clockwise direction with respect to the long axis of the pixel electrode,
And the fourth pixel region is oriented in the first direction having the first angle counterclockwise with respect to the long axis of the pixel electrode.
8. The method of claim 7,
Wherein the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region are oriented so as to be symmetrical with respect to a data line located at the boundary between the first pixel region and the second pixel region, respectively.
A plurality of gate wirings and data wirings provided on a substrate on which a display region having a plurality of pixel regions are defined and defining a plurality of pixel regions intersecting with each other;
A thin film transistor formed in each of the pixel regions to be electrically connected to the gate and data lines;
A pixel electrode formed in the pixel region in contact with a drain electrode of the thin film transistor;
A common electrode formed on the entire surface of the display region above or below the insulating layer with an insulating layer interposed therebetween above or below the pixel electrode;
The UV alignment film formed on the common electrode
Wherein a plurality of first openings having a long axis in one direction and having a bar shape are provided in each pixel region corresponding to an electric field of any one of the pixel electrodes or each common electrode, And the alignment direction of the UV alignment layer is different between the neighboring pixel regions,
Wherein all the bar-shaped first openings provided in the pixel regions in the display region are arranged in the same one direction.
delete 10. The method of claim 9,
And the direction in which the major axis of the first opening is arranged is the longitudinal direction of the data line.
12. The method of claim 11,
Wherein the alignment direction forms a first angle of 2 to 25 degrees in a clockwise or counterclockwise direction with respect to a major axis direction of the first opening or a second angle of 155 to 178 degrees Array substrate.
13. The method of claim 12,
When four pixel regions neighboring to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the top left, top right, bottom left,
Wherein the first pixel region is oriented in a first direction having the first angle in a counterclockwise direction with respect to a long axis of the first aperture,
The second pixel region is oriented in a second direction with the first angle clockwise with respect to the long axis of the first aperture,
The third pixel region is oriented in a third direction having the second angle counterclockwise with respect to the long axis of the first aperture,
And the fourth pixel region is oriented in a fourth direction having the second angle clockwise with respect to the long axis of the first aperture.
14. The method of claim 13,
Wherein the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region are oriented so as to be symmetrical with respect to each other with respect to the data line located at the boundary,
Wherein the first pixel region, the third pixel region, the second pixel region, and the fourth pixel region are oriented so as to be symmetrical to each other with reference to the gate wiring located at the boundary between the first pixel region and the third pixel region, Board.
13. The method of claim 12,
When four pixel regions neighboring to each other in the up, down, left, and right directions are defined as first, second, third, and fourth pixel regions in the top left, top right, bottom left,
Wherein the first pixel region is oriented in a first direction having the first angle in a counterclockwise direction with respect to a long axis of the first aperture,
The second pixel region is oriented in a second direction with the first angle clockwise with respect to the long axis of the first aperture,
Wherein the third pixel region is oriented in the second direction with the first angle clockwise with respect to the long axis of the first aperture,
And the fourth pixel region is oriented in the first direction having the first angle in a counterclockwise direction with respect to the long axis of the first opening.
16. The method of claim 15,
Wherein the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region are oriented so as to be symmetrical with respect to a data line located at the boundary between the first pixel region and the second pixel region, respectively.

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