KR101884641B1 - Electrode materials and interface layers to minimize chalcogenide interface resistance - Google Patents

Electrode materials and interface layers to minimize chalcogenide interface resistance Download PDF

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KR101884641B1
KR101884641B1 KR1020167008852A KR20167008852A KR101884641B1 KR 101884641 B1 KR101884641 B1 KR 101884641B1 KR 1020167008852 A KR1020167008852 A KR 1020167008852A KR 20167008852 A KR20167008852 A KR 20167008852A KR 101884641 B1 KR101884641 B1 KR 101884641B1
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layer
side
interface
interface layer
chalcogenide
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KR1020167008852A
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KR20160051865A (en
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에프. 다니엘 길리
안드레아 고티
다비드 콜롬보
쿼-웨이 창
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인텔 코포레이션
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Priority to US14/073,927 priority patent/US9543515B2/en
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Priority to PCT/US2014/061947 priority patent/WO2015069468A1/en
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
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    • H01L27/2409Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes
    • H01L27/2427Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes of the Ovonic threshold switching type
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    • H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
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    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
    • H01L27/2481Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/06Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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    • H01L45/12Details
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1608Formation of the switching material, e.g. layer deposition
    • H01L45/1625Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering

Abstract

A phase change memory cell with reduced electrode-chalcogenide interface resistance and a method of fabricating such a phase change memory cell are disclosed. An interface layer is formed between the electrode layer and the chalcogenide layer to form a chalcogenide- Thereby providing a reduced resistance between the layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises tungsten carbide, molybdenum carbide, tungsten boride, or molybdenum boride, or combinations thereof. In one exemplary embodiment, the interface layer comprises a thickness between about 1 nm and about 10 nm.

Description

ELECTRODE MATERIALS AND INTERFACE LAYERS TO MINIMIZE CHALCOGENIDE INTERFACE RESISTANCE < RTI ID = 0.0 >

Embodiments of the systems and techniques described herein relate to memory devices. More particularly, embodiments of the systems and techniques described herein may be applied to phase-change cross-point memory systems (" MEMS ") including materials that provide reduced electrode- ).

The high resistance at the electrode-chalcogenide interface in the chalcogenide-based phase change memories requires that a higher operating voltage be used or a reduced driving voltage be available for the chalcogenide phase change. In addition, the high local temperatures (in excess of 600 C) associated with the operation of the phase change memory make the electrode-chalcogenide reaction likely to adversely affect device performance.

The embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals designate like elements.
Figure 1 depicts a perspective view of one exemplary embodiment of a portion of a chalcogenide-based phase change cross-point memory including tungsten and molybdenum carbide and boride interface layers according to the subject matter disclosed herein;
2 is a flow diagram of an exemplary embodiment for forming a chalcogenide-based phase change crosspoint memory including interface layers according to the subject matter disclosed herein;
3A-3B illustrate a chalcogenide-based phase change cross-point memory structure (not shown) according to the subject matter disclosed herein before forming a cross point memory column array, and after forming a cross point memory column array, ≪ / RTI >
4 depicts a schematic diagram of an exemplary embodiment of a cross-point memory array including a plurality of chalcogenide-based phase change memory cells according to the subject matter disclosed herein;
FIG. 5 illustrates a functional block diagram of an exemplary embodiment of an electronic system including a chalcogenide-based phase change cross-point memory array according to the subject matter disclosed herein.
It will be appreciated that for simplicity and / or clarity of illustration, the components shown in the figures are not necessarily drawn to scale. For example, the dimensions of some components may be exaggerated relative to other components for clarity. The scale of the drawings does not represent exact dimensions and / or dimensional ratios of the various components shown herein. Also, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and / or similar elements.

Embodiments of the techniques described herein relate to semiconductor memories, and more particularly, the systems and techniques described herein include a phase change memory that includes a material that provides reduced electrode-chalcogenide interface resistance To cross-point memory systems. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments disclosed herein. However, those skilled in the relevant art will recognize that the embodiments disclosed herein may be practiced without one or more of these specific details, or with other methods, components, materials, and so forth will be. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification.

Reference throughout this specification to "one embodiment" or "one embodiment " means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, certain features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration. &Quot; Any embodiment described herein as "exemplary " is not necessarily to be construed as preferred or advantageous over other embodiments.

Various operations may be described in turn as a number of discrete operations, and in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. The operations described may be performed in a different order than the illustrated embodiment. Various additional operations may be performed and / or the operations described may be omitted in further embodiments.

The subject matter disclosed herein relates to methods, materials, and structures that provide reduced electrode-chalcogenide interface resistance and are suitable for phase change operation of chalcogenide memory. More specifically, the subject matter disclosed herein provides an interface layer between the electrode layer and the chalcogenide layer that provides a reduced resistance compared to the electrode-chalcogenide interface without the interface layer of the subject matter disclosed herein Materials, and structures that may be involved. Embodiments of the subject matter disclosed herein include carbides and / or borides of tungsten (W) and / or molybdenum (Mo) (W / Mo) formed between the composite electrodes and the chalcogenide memory cell layers Lt; / RTI > In one exemplary embodiment, the W / Mo carbide and / or boride interface layers are formed by a reactive physical vapor deposition (PVD) technique using tungsten and / or molybdenum with unsaturated organic carbon compounds such as benzene and acetylene , Reactive sputtering). In other exemplary embodiments, the W / Mo carbide and / or boride interface layers are formed by non-reactive sputtering from W / Mo carbide and / or boride targets.

Chalcogenides such as tellurium (Te) and selenium (Se) readily react with tungsten (W) and molybdenum (Mo) at high temperatures. Tungsten (W) is known to reduce the interface resistance between C and various GST-based (germanium-antimony-tellurium) phase change memory materials. Molybdenum also exhibits similar properties. However, the reactivity with Se and Te makes basic tungsten and molybdenum unsuitable as electrode-chalcogenide interface layers because the high local temperatures (in excess of 600 C) associated with the operation of the phase change memory are due to the electrode-chalcogenide reaction . Thus, refractory materials, including high melting temperatures, such as conductive carbides and borides, which melt at temperatures above 1200C, are suitable for such high temperature applications.

Techniques for depositing tungsten and molybdenum carbides include organic compounds such as benzene (C 6 H 6 ), acetylene (C 2 H 2 ), or organic compounds such as ethane, propene, dicyanoacetylene, and cyanogens, And reactive sputtering with Ar and tungsten (W) and / or molybdenum (Mo) (W / Mo) targets, or direct sputtering from a carbide target. Similarly, tungsten and molybdenum borides can be reactive sputtered from similar targets or deposited from boride targets using diborane / Ar. According to the subject matter disclosed herein, W / Mo carbide and boride interface layers are not simple mixtures of W, Mo and carbon or boron. Instead, the W / Mo carbide and boride layers are bonded materials and deposited as such because the temperatures required to form the interface layers on the wafer using simple anneals are not practical, , Because silicon melts. In addition, relatively thick interface layers of carbides and borides of tungsten and molybdenum may be harsh; Thus, embodiments of the subject matter disclosed herein utilize thin layers between electrodes and a chalcogenide memory cell in a thickness range of about 1 nm to 10 nm. In one exemplary embodiment, the reactive sputtered films from W / acetylene are smooth (and amorphous), the hardness exceeds the basic tungsten and the stoichiometry matches the tungsten carbide (WC).

FIG. 1 is a perspective view of one exemplary embodiment of a portion of a chalcogenide-based phase change cross-point memory array 100 that includes tungsten and / or molybdenum carbide and / or boride interface layers according to the subject matter disclosed herein. . According to the subject matter disclosed herein, the interface layers are formed between the electrode layers and the chalcogenide layers and provide a reduced resistance compared to the electrode-chalcogenide interface without carbide and / or boride-based interface layers . The crosspoint memory 100 may be part of a solid-state memory array or a solid-state driver, but is not limited thereto. The cross-point memory 100 includes a plurality of memory cells 101 arranged in columns (or columns), of which only a few are shown. In addition, it should be appreciated that the dielectric material typically between memory cells 101 is not shown in FIG. 1 for clarity.

Each memory cell 101 includes an electrode 104 formed on the wordline metallization 102. On the electrode 104, an electrode-chalcogenide interface layer 105 is formed. A switching device (SD) 106 is formed on the interface layer 104. The electrode-chalcogenide interface layer 107 is formed on the SD 106. An electrode 108 is formed on the interface layer 107. An electrode-chalcogenide interface layer 109 is formed on the electrode 108. A chalcogenide memory cell (MC) (110) is formed on the interface layer (109). An electrode-chalcogenide interface layer 111 is formed on the MC 110. An electrode 112 is formed on the interface layer 111. A bit line metallization layer (113) is formed on the electrode (112).

In embodiments of the subject matter disclosed herein, the wordline metallization layer 102 and the bitline metallization layer 113 are formed of, for example, tungsten, copper, and / or aluminum. In one exemplary embodiment, the electrode layers 104, 108, and 112 are composite electrodes formed, for example, of carbon (C) and / or titanium nitride (TiN). In one exemplary embodiment, the switching device (SD) 106 may be formed of a mixture of chalcogenides, such as, but not limited to, Te and Se, arsenic (As), germanium (Ovonic Threshold Switch) comprising a glassy mixture of glass forming additives such as, but not limited to, silicon (Si). Note that this is not a comprehensive list of chalcogenides or glass forming additives. In one exemplary embodiment, the chalcogenide memory cell 110 is formed of, for example, Ge 2 Sb 2 Te 5 (GST) and In 3 SbTe 2 (IST), but is not limited thereto.

In one exemplary embodiment, the electrode-chalcogenide interface layers 105, 107, 109, and 111 are formed of carbides and / or borides of tungsten (W) and / or molybdenum (Mo). In one exemplary embodiment, the interface layers 105,107, 109 and 111 are formed by reactive physical vapor deposition (PVD) from W / Mo targets with unsaturated organic carbon compounds, such as, for example, benzene and acetylene ) (E. G., Reactive sputtering). In other exemplary embodiments, the interface layers 105, 107, 109, and 111 are formed unreactively by being sputtered from the W / Mo carbide and boride targets. Although the interface layers 105, 107, 109, and 111 are depicted in FIG. 1, it should be appreciated that alternative exemplary embodiments may have fewer interface layers. That is, alternative exemplary embodiments may not have an interface layer between the respective electrode layers and the chalcogenide layer according to the subject matter disclosed herein.

Deposited tungsten and / or molybdenum carbide and / or boride layers can be highly conductive and refractory materials (when sputtered from carbide / boride targets and reactive sputtered from W / C 6 H 6 ); Thus, embodiments of the subject matter disclosed herein utilize thin layers in the range of about 1 nm to 10 nm formed between the composite electrode stacks of carbon (C) or titanium nitride (TiN) and the chalcogenide memory cells.

Also, since graphitic carbon conduction is often filamentary, thin or even discontinuous, interface tungsten and / or molybdenum carbide and / or boride layers are suitable for reducing electrode / chalcogenide contact resistance .

FIG. 2 is a flow diagram 200 of an exemplary embodiment for forming a chalcogenide-based phase change crosspoint memory including interface layers according to the subject matter disclosed herein. 3A-3B illustrate a chalcogenide-based phase change cross-point memory structure (not shown) according to the subject matter disclosed herein before forming a cross point memory column array, and after forming a cross point memory column array, Lt; RTI ID = 0.0 > 300 < / RTI >

At 201, word lines 302 are formed and patterned in a known manner on a substrate (not shown in Figs. 3A and 3B). In one exemplary embodiment, the word lines 302 may be formed of, for example, tungsten, copper, and / or aluminum. A dielectric material 303, such as silicon dioxide (SiO x ), silicon nitride (SiN x ), or other electrically insulating material is formed on the word lines 302 in a known manner.

At 202, the first electrode layer 304 is formed on the word lines 302 in a known manner. In one exemplary embodiment, the first electrode layer 304 is formed of, for example, carbon (C) and / or titanium nitride (TiN). At 203, a first electrode-chalcogenide interface layer 305 is formed on the first electrode layer 304 in contact therewith. In one exemplary embodiment, the first interface layer 305 is formed by reactive physical vapor deposition (PVD) from W / Mo targets using unsaturated organic carbon compounds, such as, for example, benzene and acetylene Reactive sputtering). In another exemplary embodiment, the first interface layer 305 is formed unreactively by being sputtered from W / Mo carbide and / or boride targets.

At 204, a switching device (SD) layer 306 is formed in contact with and on the first interface layer 305 in a known manner. In one exemplary embodiment, the switching device (SD) layer 306 is formed of a mixture of chalcogenides, such as, for example, Te and Se, and arsenic (As), germanium (Ge) And OTS (Ovonic Threshold Switch), which includes a glassy mixture of glass forming additives such as, but not limited to, silicon (Si). At 205, a second electrode-chalcogenide interface layer 307 is formed on the SD layer 306 in contact therewith. In one exemplary embodiment, the second interface layer 307 may comprise reactive physical vapor deposition (PVD) from W / Mo targets with unsaturated organic carbon compounds, such as, for example, benzene and acetylene Reactive sputtering). In another exemplary embodiment, the second interface layer 307 is formed unreactively by being sputtered from W / Mo carbide and / or boride targets.

At 206, a second electrode layer 308 is formed in contact with and on the second interface layer 307 in a known manner. In one exemplary embodiment, the second electrode layer 308 is formed of, for example, carbon (C) and / or titanium nitride (TiN). At 207, a third electrode-chalcogenide interface layer 309 is formed on the second electrode layer in contact therewith. In one exemplary embodiment, the third interface layer 309 is formed by reactive physical vapor deposition (PVD) from W / Mo targets using unsaturated organic carbon compounds, such as, for example, benzene and acetylene Reactive sputtering). In another exemplary embodiment, the third interface layer 307 is formed unreactively by being sputtered from W / Mo carbide and / or boride targets.

At 208, a chalcogenide memory cell (MC) layer 310 is formed in contact with and on the third interface layer 309 in a known manner. In one exemplary embodiment, the chalcogenide memory cell (MC) layer 310 may be formed of, for example, Ge 2 Sb 2 Te 5 (GST) and In 3 SbTe 2 (IST) But is not limited to. At 209, a fourth electrode-chalcogenide interface layer 311 is formed on the memory cell layer 310 in contact therewith. In one exemplary embodiment, the fourth interface layer 311 is formed by reactive physical vapor deposition (PVD) from W / Mo targets using unsaturated organic carbon compounds, such as, for example, benzene and acetylene Reactive sputtering). In another exemplary embodiment, the fourth interface layer 311 is formed unreactively by being sputtered from W / Mo carbide and / or boride targets.

At 210, a third electrode layer 312 is formed in contact with and on the fourth interface layer 311 in a known manner. In one exemplary embodiment, the third electrode layer 312 is formed of, for example, carbon (C) and / or titanium nitride (TiN). At 211, a hard mask 315 is formed in a known manner on the third electrode layer 312 and is patterned in a known manner to form a columnar array to be a cross-point memory including an arrangement similar to that depicted in FIG. The structure 300 is etched. FIG. 3A depicts a structure 300 formed prior to etching.

FIG. 3B depicts the structure 300 after etching to form a cross-point memory column (column) array. At 212, a bit line metallization layer 313 is formed on the electrode 312. It should also be appreciated that Figure 3b also depicts dielectric material 316 formed in a known manner between the dielectric material 314 formed on each column and the columns (columns) of structure 300. The dielectric materials used for 314 may be formed of non-conductive oxides and nitrides that are insulating and include, but are not limited to, SiO x and SiN x to force electrical conduction through the chalcogenide layers. Although the interface layers 305, 307, 309, and 311 are depicted in FIGS. 3A and 3B, it should be appreciated that alternative exemplary embodiments may have fewer interface layers. That is, alternative exemplary embodiments may not have an interface layer between the respective electrode layers and the chalcogenide layer according to the subject matter disclosed herein. Alternatively, the interface layers according to the subject matter disclosed herein may also be used in single chalcogenide devices.

FIG. 4 depicts a schematic diagram of an exemplary embodiment of a crosspoint memory array 400 including a plurality of chalcogenide-based phase change memory cells 401 according to the subject matter disclosed herein. In one exemplary embodiment, the at least one memory cell 401 comprises tungsten and / or molybdenum carbide and / or boride interface layers according to the subject matter disclosed herein. 4, memory cells 401 may be formed at intersections of column signal lines 402 (e.g., bit lines) and row signal lines 403 (e.g., word lines) . The individual column and / or row signal lines are electrically connected to a memory controller (not shown) in a known manner to selectively operate the memory cells 401 in a known manner. It should be appreciated that the memory array 400 may include portions of a solid-state memory array or solid-state drive coupled in a known manner to a computer system or an information processing system (not shown).

FIG. 5 depicts a functional block diagram of an exemplary embodiment of an electronic system 500 including a chalcogenide-based phase change crosspoint memory array according to the subject matter disclosed herein. The system 500 includes a processor 501 coupled to a memory device 510 via control / address lines 503 and data lines 504. In some exemplary embodiments, data and control may use the same physical lines. In some exemplary embodiments, the processor 501 may be an external microprocessor, microcontroller, or some other type of external control circuitry. In other exemplary embodiments, the processor 501 may be integrated in the same package as the memory device 510, or even on the same die. In some exemplary embodiments, the processor 501 may be integrated with the control circuit 511, such that a portion of the same circuitry is used for both functions. Processor 501 may have an external memory, such as random access memory (RAM) (not shown) and / or read only memory (ROM) (not shown), used for program storage and intermediate data. Alternatively, the processor 501 may have internal RAM or ROM. In some exemplary embodiments, the processor 501 may use the memory device 510 for program or data storage. A program executing on the processor 501 may implement many different functions including, but not limited to, an operating system, a file system, defective chunk remapping, and error management.

In some exemplary embodiments, an external connection 502 is provided that allows the processor 501 to communicate with external devices (not shown). Additional I / O circuits (not shown) may be used to couple the external connection 502 to the processor 501. If the electronic system 500 is a storage system, then the external connection 502 can be used to provide non-volatile storage for external devices. In one exemplary embodiment, the electronic system 500 may be a solid-state drive (SSD), a USB thumb drive, a secure digital card (SD card), or any other type of Storage system, but is not limited thereto. An external connection 502 may be used to connect to a computer or other intelligent device, such as, for example, a cell phone or a digital camera, using a standard or proprietary communication protocol. Exemplary computer communication protocols that may be compatible with external connection 502 include, but are not limited to, any version of the following protocols: Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), SCSI Small Computer System Interconnect), Fiber Channel, Parallel Advanced Technology Attachment (PATA), Integrated Drive Electronics (IDE), Ethernet, IEEE-1394, Secure Digital Card Interface (SD card), CompactFlash Interface, , Peripheral Component Interconnect (PCI), or PCI Express.

If the electronic system 500 is a computing system, such as a mobile phone, tablet, notebook computer, set top box, or some other type of computing system, then the external connection 502 may be implemented as any of the following protocols, Digital television standards such as 802.3, IEEE 802.11, Data Over Cable Service Interface Specification (DOCSIS), and Digital Video Broadcasting (DVB) - Terrestrial Mobile telephony communication protocols such as Terrestrial, DVB-cable, Advanced Television Committee Standard (ATSC), and Global System for Mobile Communication (GSM), protocols based on code division multiple access (CDMA) Long Term Evolution).

The memory device 510 may include an array 517 of memory cells. The memory cell array 517 may be organized as a two-dimensional or three-dimensional crosspoint array and may include a phase change memory (PCM), a phase change memory (PCMS) with a switch, a resistive memory, a nanowire memory, (MRAM), including spin-transfer-torque (STT) -MRAM, or any other type of memory configured as a cross-point array. have. In one exemplary embodiment, the memory cell array 517 comprises a chalcogenide-based phase change cross-point memory array comprising tungsten and / or molybdenum carbide and / or boride interface layers according to the subject matter disclosed herein . Crosspoint array 517 may be coupled to word line drivers 514 and / or bit line drivers 515, and / or sense amplifiers 516 in a known manner. The address lines and control lines 503 can be received and decoded by the control circuit 511, the I / O circuit 513 and the address circuit 512, which control the memory array 517 . I / O circuit 513 may be coupled to data lines 504 and thereby cause data to be received from processor 501 and transmitted to it. The data read from the memory array 517 may be temporarily stored in the read buffers 519. [ The data to be written to the memory array 517 may be temporarily stored in the write buffers 518 before being transferred to the memory array 517. [

It should be appreciated that the electronic system 500 shown in FIG. 5 has been simplified to facilitate a basic understanding of the features of the system. Many different embodiments are possible, including using a single processor 501 to control a plurality of memory devices 510 to provide more storage space. Additional functionality, such as a video graphics controller to drive the display, and other devices for human-oriented I / O, may be included in some exemplary embodiments.

These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed as limiting the scope of the specific embodiments disclosed in the specification and claims. Rather, the scope of the embodiments disclosed herein should be determined by the following claims, which should be construed in accordance with established policies of claim interpretation.

Claims (25)

  1. As a phase change memory cell,
    A chalcogenide-based phase change memory layer;
    A first electrode layer;
    A first interface layer between the chalcogenide-based phase change memory layer and the first electrode layer and in contact with each of the chalcogenide-based phase change memory layer and the first electrode layer, A boron that reduces the resistance between the first electrode layer and the coganide-based phase change memory layer;
    A second interface layer between the chalcogenide-based phase change memory layer and the second electrode layer, the second interface layer contacting the chalcogenide-based phase change memory layer and the second electrode layer, A boride that reduces the resistance between the second base layer and the second electrode layer;
    A switching device layer comprising an Ovonic Threshold Switch (OTS);
    A third electrode layer;
    A third interface layer between the switching device layer and the second electrode layer and in contact with the switching device layer and the second electrode layer, respectively; And
    A fourth interface layer between the switching device layer and the third electrode layer and in contact with each of the switching device layer and the third electrode layer,
    / RTI >
  2. The method according to claim 1,
    Wherein the first interface layer comprises tungsten boride, or molybdenum boride, or combinations thereof.
  3. The method according to claim 1,
    Wherein the first interface layer comprises a thickness between 1 nm and 10 nm.
  4. delete
  5. The method according to claim 1,
    Wherein the second interface layer comprises tungsten boride, or molybdenum boride, or combinations thereof.
  6. The method according to claim 1,
    Wherein the second interface layer comprises a thickness between 1 nm and 10 nm.
  7. The method according to claim 1,
    Wherein the third interface layer comprises tungsten boride, or molybdenum boride, or a combination thereof,
    Wherein the fourth interface layer comprises tungsten boride, or molybdenum boride, or a combination thereof,
    Wherein the chalcogenide-based phase change memory layer comprises Ge 2 Sb 2 Te 5 or In 3 SbTe 2 .
  8. delete
  9. A method of forming a phase change memory cell,
    Forming a chalcogenide-based phase change memory layer, wherein the chalcogenide-based phase change memory layer comprises a first side and a second side;
    Forming a first interface layer comprising a first side and a second side, the first side of the first interface layer contacting a first side of the chalcogenide-based phase change memory layer;
    Forming a first electrode layer comprising a first side and a second side, the first side of the first electrode being in contact with a second side of the first interface layer, A boride that reduces the resistance between the first electrode layer and the first electrode layer;
    Forming a second interface layer comprising a first side and a second side, the first side of the second interface layer contacting a second side of the chalcogenide-based phase change memory layer;
    Forming a second electrode layer comprising a first side and a second side, the first side of the second electrode being in contact with a second side of the second interface layer, A boride that reduces the resistance between the second base layer and the second electrode layer;
    Forming a third interface layer comprising a first side and a second side, the first side of the third interface layer contacting a second side of the second electrode layer;
    Forming a switching device layer comprising a first side and a second side, the first side of the switching device contacting a second side of the third interface layer;
    Forming a fourth interface layer comprising a first side and a second side, the first side of the fourth interface layer contacting a second side of the switching device layer; And
    Forming a third electrode layer comprising a first side and a second side, the first side of the third electrode layer contacting a second side of the fourth interface layer,
    / RTI > A method of forming a phase change memory cell,
  10. 10. The method of claim 9,
    Wherein the first interface layer comprises tungsten boride, or molybdenum boride, or combinations thereof.
  11. 10. The method of claim 9,
    Wherein forming the first interface layer comprises reactively sputtering a tungsten target or a molybdenum target, or a combination thereof, using an unsaturated carbon compound.
  12. delete
  13. 10. The method of claim 9,
    Wherein the first interface layer comprises a thickness between 1 nm and 10 nm.
  14. delete
  15. 10. The method of claim 9,
    Wherein the second interface layer comprises tungsten boride, or molybdenum boride, or a combination thereof.
  16. 10. The method of claim 9,
    Wherein the second interface layer comprises a thickness between 1 nm and 10 nm.
  17. 10. The method of claim 9,
    Wherein the third interface layer comprises tungsten boride, or molybdenum boride, or a combination thereof,
    Wherein the fourth interface layer comprises tungsten boride, or molybdenum boride, or a combination thereof,
    Wherein the chalcogenide-based phase change memory layer comprises Ge 2 Sb 2 Te 5 or In 3 SbTe 2 .
  18. 10. The method of claim 9,
    Wherein forming the interface layers comprises reactively sputtering a tungsten target or a molybdenum target, or a combination thereof, using an unsaturated carbon compound.
  19. 10. The method of claim 9,
    Wherein forming the interface layers comprises sputtering a tungsten carbide target, a molybdenum carbide target, a tungsten boride target, or a molybdenum boride target, or a combination thereof in a non-reactive manner. .
  20. 10. The method of claim 9,
    Wherein the phase change memory cell comprises a portion of a solid-state memory array or a solid-state drive.
  21. delete
  22. delete
  23. delete
  24. delete
  25. delete
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EP3066687B1 (en) 2019-05-08
EP3066687A1 (en) 2016-09-14
US9716226B2 (en) 2017-07-25
JP2016540370A (en) 2016-12-22
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KR20160051865A (en) 2016-05-11

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