JP5364407B2 - Nonvolatile memory device and manufacturing method thereof - Google Patents

Nonvolatile memory device and manufacturing method thereof Download PDF

Info

Publication number
JP5364407B2
JP5364407B2 JP2009071543A JP2009071543A JP5364407B2 JP 5364407 B2 JP5364407 B2 JP 5364407B2 JP 2009071543 A JP2009071543 A JP 2009071543A JP 2009071543 A JP2009071543 A JP 2009071543A JP 5364407 B2 JP5364407 B2 JP 5364407B2
Authority
JP
Japan
Prior art keywords
element
wiring
main component
intermediate layer
rectifying element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009071543A
Other languages
Japanese (ja)
Other versions
JP2010225850A (en
Inventor
和人 西谷
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP2009071543A priority Critical patent/JP5364407B2/en
Publication of JP2010225850A publication Critical patent/JP2010225850A/en
Application granted granted Critical
Publication of JP5364407B2 publication Critical patent/JP5364407B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To suppress operation failure and variation of a characteristic in a nonvolatile storage device. <P>SOLUTION: A plurality of unit storage cells are laminated in the nonvolatile storage device. The respective unit storage cells are each provided with a first wiring extending in a first direction, a second wiring extending in a second direction that is not parallel to the first direction, a storage element arranged between the first wiring and second wiring and a rectifier element which is disposed between the first wiring or second wiring and the storage element and is connected in series to the storage element. An intermediate layer comprising a main component of the rectifier element is installed between the storage element and the rectifier element in the nonvolatile storage device. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a nonvolatile memory device and a manufacturing method thereof.

  Non-volatile storage devices represented by NAND flash memory are widely used in mobile phones, digital still cameras, USB (Universal Serial Bus) memories, silicon audio, etc. for storing large volumes of data, and are rapidly miniaturized. Continues to expand the market by reducing manufacturing costs per bit. New applications are also emerging rapidly, and a virtuous cycle of finding new markets through miniaturization and reduced manufacturing costs has been realized.

  In particular, NAND flash memory realizes a substantial cross-point cell by sharing a gate conductor (“GC”) with a plurality of active areas (“AA”), and due to its simple structure, it is rapidly miniaturized. Is underway. For this reason, in recent years, NAND flash memories have led the fine processing of semiconductors, and the minimum processing dimension has reached 60 nm or less even at the mass production level.

  However, the NAND flash memory uses a transistor operation for storing information by threshold fluctuation, and there is a limit to further uniform characteristics, high reliability, high speed operation, and high integration in the future. It is said that development of a new nonvolatile memory device is desired.

  Among them, for example, a nonvolatile memory device using a resistance change element or a phase change memory element (hereinafter referred to as a resistance change element) operates using a variable resistance state of a resistance material. Therefore, the transistor operation becomes unnecessary. Further, since the device characteristics are improved as the size of the resistance material is made finer, it is expected to realize high uniformity of characteristics, high reliability, high speed operation, and high density.

  Since the memory cell (memory unit element) of the memory unit of such a nonvolatile memory device is a cross-point cell, after processing the first wiring in the first direction in the plane of the nonvolatile memory It is necessary to process the second wiring in the second direction rotated substantially at a right angle from the first direction. And in order to insulate between each cell, the element isolation layer is arrange | positioned between cells. Furthermore, in the cell, a structure in which a variable resistance element or the like and a rectifying element are connected in series is disclosed (for example, see Patent Document 1).

JP 2008-235637 A

  However, in a structure in which the variable resistance element and the rectifying element are connected in series, the main component of the rectifying element (the main component element of the rectifying element) may diffuse into the variable resistance element or the like.

  For example, since the rectifying element is formed by film formation, activation processing (for example, annealing treatment) of the rectifying element is necessary after film formation. When such a process is performed, in the structure in which the variable resistance element and the rectifying element are connected in series, the main component (for example, a semiconductor material) of the rectifying element diffuses into the variable resistance element and the like. As a result, there has been a problem that non-volatile memory devices malfunction and cause variations in characteristics.

  The present invention solves the above problems.

According to one aspect of the present invention, there is provided a nonvolatile memory device in which a plurality of unit memory cells are stacked, each of the unit memory cells including a first wiring extending in a first direction and the first memory cell. A second wiring extending in a second direction non-parallel to the first direction, a memory element provided between the first wiring and the second wiring, and the first wiring or the A rectifying element disposed between the second wiring and the memory element and connected in series to the memory element, and the rectifying element between the memory element and the rectifying element. An intermediate layer containing a main component is provided , the main component is contained in the intermediate layer below the solid solution limit of the intermediate layer, and the concentration distribution of the main component in the intermediate layer is the rectification The concentration of the main component decreases according to the direction from the element toward the memory element. The nonvolatile memory device, characterized in that is is provided.

Further, according to one embodiment of the present invention, a first wiring extending in a first direction, a second wiring extending in a second direction non-parallel to the first direction, A method of manufacturing a nonvolatile memory device having a memory element and a rectifying element connected in series to the memory element between the first wiring and the second wiring, wherein a metal film is formed on the rectifying element. Forming the intermediate layer containing the main component of the rectifying element on the metal film, and forming the memory element on the intermediate layer, The non-volatile memory device manufacturing method is characterized in that the concentration distribution of the main component is formed to have a slope in which the concentration of the main component decreases in the direction from the rectifying element toward the memory element. Is done.

  According to the present invention, malfunction of the nonvolatile memory device and variation in characteristics are suppressed.

It is a principal part cross-sectional schematic diagram of the memory cell part of a non-volatile memory device (the 1). It is a principal part cross-sectional schematic diagram of the memory cell part of a non-volatile memory device (the 2). It is a flowchart of the manufacturing process of the memory cell part of a non-volatile memory device. It is a principal part cross-sectional schematic diagram of the memory cell part of a non-volatile memory device (the 3).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view of an essential part of a memory cell portion of a nonvolatile memory device. FIGS. 1A and 1B illustrate ReRAM memory cell arrays 1a and 1b of a ReRAM (Resistance Random Access Memory) memory having a cross-point structure as an example of a nonvolatile memory device. 1A and 1B show a structure in which ReRAM memory cells are stacked in a plurality of stages.

  As shown in FIG. 1A, in each cell (unit storage cell) 80 of the ReRAM memory cell array 1a, a wiring BL1 (lower wiring) which is a first bid line is used as a base, and from a lower layer to an upper layer, The first barrier metal film 10, the diode 20 as the first rectifying element, the first metal film 30 for ohmic contact, the second barrier metal film 40 as the intermediate layer, and the resistance change as the first memory element A film 50 and a second metal film 60 are disposed. A stopper wiring film 70 for CMP (Chemical Mechanical Polishing) is disposed on the metal film 60, and the stopper wiring films 70 in each cell 80 are connected to each other by a wiring WL1 (upper wiring) which is a first word line. doing.

  Here, the wiring WL1 extends in the first direction (X-axis direction in the drawing), and the wiring BL1 extends in the second direction (Y-axis direction in the drawing) that is non-parallel to the first direction. ). That is, the resistance change film 50 is disposed between the wiring BL1 and the wiring WL1 that cross each other. In each cell 80, the first diode 20 and the resistance change film 50 are connected in series so that a current flows in one direction of the cell 80.

  Further, in the ReRAM memory cell array 1a, an interlayer insulating film 90 is disposed on the wiring WL1, and a wiring BL2 that is a second bid line is disposed on the interlayer insulating film 90. Further, the above-described cell 80 is arranged on the wiring BL2.

  That is, on the wiring BL2, the third barrier metal film 10, the diode 20 as the second rectifying element, the third metal film 30 for ohmic contact, the fourth barrier metal film 40, and the second memory element. A variable resistance film 50 and a fourth metal film 60 are disposed. Then, the stopper wiring film 70 is disposed on the metal film 60, and the stopper wiring films 70 in each cell 80 are connected to each other by the wiring WL2 that is the second word line.

As described above, the ReRAM memory cell array 1a has a structure in which the cells 80 are stacked in a plurality of stages via the wiring. In addition, element isolation layers are periodically arranged (not shown) between adjacent cells in order to ensure insulation between the cells.
When a current is supplied to each resistance change film 50 via the word line and the bid line, the resistance change film 50 reversibly transitions between the first state and the second state. be able to.

In addition to the ReRAM memory cell array 1a shown in FIG. 1A, such a ReRAM memory cell array may be a ReRAM memory cell array 1b shown in FIG. 1B.
In the structure of the ReRAM memory cell array 1b, the wirings WL1 which are word lines are not arranged independently for each stage, but the wirings WL1 are shared and the cells 80 are stacked in a plurality of stages.

That is, the cell 80 and the wiring BL1 below the wiring WL1 are arranged in the same manner as in FIG. 1A. However, on the wiring WL1, the metal film 60 and the resistance change film as a memory element are formed from the lower layer. 50, a barrier metal film 40, an ohmic contact metal film 30, a diode 20, and a barrier metal film 10 are disposed. A wiring BL2 that is a bid line is disposed on the barrier metal film 10.
According to such a structure, in addition to the improvement of the storage density, the common use of the wiring WL1 is expected to suppress the applied voltage delay to the wiring WL1, to speed up the write operation and the erase operation, and to reduce the element area. The

For example, tungsten (W), tungsten nitride (WN), or tungsten carbide (WC) is applied as the material of the wirings WL1, WL2, BL1, and the stopper wiring film 70.
Further, as the material of the barrier metal film 10 and the metal film 60, for example, titanium (Ti), titanium nitride (TiN), or the like is applied.

  In the present embodiment, a resistance change element is used as an example of the memory element. However, a phase change film may be used instead of the resistance change film 50 as a phase change memory element. .

Next, the structure of the cell 80 described above will be described in more detail.
FIG. 2 is a schematic cross-sectional view of an essential part of a memory cell portion of the nonvolatile memory device. FIG. 2 shows an enlarged view of the cell 80 including the wirings BL1 and WL1.
As shown in FIG. 2, the cell 80 includes metal films 30 and 60 that are electrodes on the upper and lower layers of the resistance change film 50. By disposing the metal films 30 and 60, electrical connection with the resistance change film 50 through the metal films 30 and 60 can be achieved.

In order to ensure a stable ohmic contact between the metal film 30 and the diode 20, a layer having a component different from that of the metal film 30 may be formed at the interface between the metal film 30 and the diode 20. An example of the layer is a metal silicide film. Such a metal silicide film is formed by annealing the metal film 30 and the diode 20 (for example, 550 ° C.).
Further, the metal films 30 and 60 may have a function as a barrier layer that prevents diffusion of impurities into the resistance change film 50.

  In the resistance change film 50, the voltage applied between the main surfaces of the resistance change film 50 changes depending on the combination of potentials applied to the wiring WL1 and the wiring BL1, and the characteristic (for example, resistance value) of the resistance change film 50 changes. Can store or erase information. For this reason, the variable resistance film 50 can be made of any material whose characteristics change depending on the applied voltage.

  For example, the material of the resistance change film 50 may be a variable resistance layer whose resistance value can be reversibly transitioned by an applied voltage, or a phase change layer capable of reversibly transition between a crystalline state and an amorphous state. Etc. apply.

As the material of the specific resistance change film 50, ZnMn x O y, ZnFe x O y, NbO x, Cr -doped SrTiO 3-x, Pr x Ca y MnO z, ZrO x, NiO x, Ti -doped NiO x film , ZnO x , TiO x , TiO x N y , CuO x , GdO x , CuTe x , HfO x , HfAlOx, C (carbon), CN (carbon nitride), resistance due to Joule heat generated by the voltage applied to both ends state changes of chalcogenide GST (Ge x Sb y Te z ), N doped subjected to doping GST GST, O doped GST, Ge x Sb y, at least one selected from in x Ge y Te z, etc. The containing material is applied.

Furthermore, as a configuration of the resistance change film 50, the MIM (Metal-Insulator-Metal) structure itself may be used.
For example, the above-described oxide film or chalcogenide-based material is disposed in the middle, and tungsten nitride (WN), titanium nitride (TiN), titanium aluminum nitride (AlTiN), tantalum nitride (TaN), titanium nitride silicide (TiNSi) are disposed above and below the oxide film or chalcogenide material. ), Tantalum carbide (TaC), titanium silicide (TiSi), tungsten silicide (WSi), cobalt silicide (CoSi), nickel silicide (NiSi), nickel platinum silicide (NiPtSi), platinum (Pt), ruthenium (Ru), platinum A structure in which a material containing at least one selected from rhodium (PtRh), iridium (In), and the like is disposed may be used.

  The cell 80 includes a diode 20 as a rectifying element. Thereby, even if an arbitrary cell 80 is selected by the combination of the wiring WL1 and the wiring BL1, the direction of the current flowing in the cell 80 is regulated.

  The material of the diode 20 is mainly composed of, for example, polysilicon (poly-Si). As the diode 20, for example, a PIN diode, a PN junction diode, a Schottky diode, a Zener diode, or the like is applied.

In the cell 80 of the present embodiment, a barrier metal film 40 as an intermediate layer is provided between the metal film 30 and the resistance change film 50.
Here, the material of the barrier metal film 40 is platinum (Pt), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbide. (TaC), nickel (Ni), tungsten nitride (WN), tungsten (W), molybdenum (Mo), ruthenium (Ru), ruthenium oxide (RuO2), the main component of the diode 20 (for example, silicon ( A material in which Si)) is doped below the solid solubility limit is applied. The material of the barrier metal film 40 may be a material including at least one of the above materials.

  By interposing such a barrier metal film 40 between the diode 20 and the resistance change film 50, mutual diffusion between the component constituting the resistance change film 50 and the component constituting the diode 20 is suppressed.

That is, when the main component of the diode 20 is contained in the barrier metal film 40, the diode 20 and the resistance change film 50 are compared with the case where the main component of the diode 20 is not contained in the barrier metal film 40. In the meantime, the concentration difference of the main component of the diode 20 is small. With such a configuration, in order to activate the diode 20, even if the diode 20 is subjected to an annealing process (for example, a heat treatment at 750 ° C.), the diode 20 enters the resistance change film 50. Diffusion is suppressed.
As a result, the composition change of the resistance change film 50 and the diode 20 is less likely to occur, and the malfunction of the nonvolatile memory device and the variation in characteristics are less likely to occur.

  The diode 20 may be a combination of a semiconductor material such as germanium (Ge) or a metal oxide semiconductor material such as NiO, TiO, CuO, or InZnO in addition to silicon (Si). In this case, the barrier metal film 40 is doped with the material below its solid solubility limit.

2 illustrates a two-layer structure in which the metal film 30 and the barrier metal film 40 are interposed in the gap between the resistance change film 50 and the diode 20, but the gap between the resistance change film 50 and the diode 20 is illustrated. The number of layers of the coating interposed between the two is not limited to this number. For example, the barrier metal film 40 may be a stack of a plurality of the above materials.
In order to efficiently heat the resistance change film 50 in the reset (erase) operation, a heat sink layer may be provided near the resistance change film 50 (not shown).

  Next, a manufacturing process of the memory cell portion of the nonvolatile memory device will be described. Here, a manufacturing process in which the diode 20, the metal film 30, the barrier metal film 40, and the resistance change film 50 are stacked will be described.

FIG. 3 illustrates a flow of the manufacturing process of the memory cell portion of the nonvolatile memory device.
First, the diode 20 is formed in the upper layer of the wiring BL1 under the condition of about 500 ° C. by using low pressure CVD (Chemical Vapor Deposition) method using silane (SiH4) or the like and doping gas (PH3, B2H6) or the like (step) S1).
In this step, for example, a PIN diode mainly composed of silicon (Si) is formed. The thickness (length) of the diode 20 is, for example, 100 nm.

  Next, the metal film 30 is formed on the diode 20 by sputtering or CVD (step S2). The film thickness of the metal film 30 is, for example, 5 nm.

  Note that as described above, the metal film 30 may be annealed (for example, at 550 ° C.) to form a silicide film at the interface between the metal film 30 and the diode 20. Note that silicidation of the metal film 30 is promoted also in the activation process of the diode 20 described later.

  Next, 20 wt% of silicon (Si) is doped on the metal film 30 using a tantalum nitride (TaN) target containing 20 wt% or more of the main component (for example, silicon (Si)) of the diode 20. The barrier metal film 40 is formed by sputtering (step S3).

  In addition, the barrier metal film 40 doped with silicon (Si) is formed by using the above-described target, or by a binary sputtering method using a silicon (Si) target and a tantalum nitride (TaN) target. Also good. Alternatively, after forming a tantalum nitride (TaN) film, silicon (Si) may be implanted into the tantalum nitride (TaN) film by an ion implantation method.

  However, silicon (Si) at this stage is doped below the solid solution limit of the barrier metal film 40. This is because, if silicon (Si) exceeds the solid solution limit of the barrier metal film 40, a solid solution different from the barrier metal film 40 is deposited. That is, the barrier metal film 40 of the present embodiment has a structure in which silicon (Si) elements are uniformly dispersed in the barrier metal film 40. The barrier metal film 40 is formed to a thickness of 10 nm, for example.

Next, the resistance change film 50 is formed on the barrier metal film 40 by sputtering or CVD (step S4).
For example, a ZnMn x O y film or the like is formed on the barrier metal film 40. The film thickness of the resistance change film 50 is, for example, 20 nm.

  In this embodiment, the structure in which the diode 20 is arranged on the wiring BL1 side and the resistance change film 50 is arranged on the wiring WL1 side is illustrated. However, this arrangement may be reversed depending on the driving conditions of the device. May be. In this case, after the resistance change film 50 is formed, the barrier metal film 40, the metal film 30, and the diode 20 are formed in this order.

  Then, in order to activate the diode 20 immediately after film formation, a high-temperature annealing process (for example, 750 ° C.) is performed (step S5). As a result, the main component of the diode 20 is in the form of polysilicon (poly-Si).

  Even when such an annealing process is performed, silicon (Si), which is a main component of the diode 20, is uniformly dispersed in the barrier metal film 40. Therefore, the mutual diffusion between the component constituting the resistance change film 50 and the component constituting the diode 20 is suppressed, and the composition change of the resistance change film 50 and the diode 20 hardly occurs. As a result, both the variable resistance element and the rectifying element function normally, and the malfunction of the nonvolatile memory device and the variation in characteristics are less likely to occur.

  By such a process, the cell 80 in which the diode 20 and the resistance change film 50 are connected in series through the metal film 30 and the barrier metal film 40 is formed.

Next, a modified example of the cell configuration will be described.
FIG. 4 is a schematic cross-sectional view of the relevant part of the memory cell portion of the nonvolatile memory device.
As shown in FIG. 4A, the cell 81 includes metal films 30 and 60 that are electrodes on the upper layer and the lower layer of the resistance change film 50. By disposing the metal films 30 and 60, electrical connection with the resistance change film 50 through the metal films 30 and 60 can be achieved.

  Further, in order to ensure a stable ohmic contact between the metal film 30 and the diode 20, a metal silicide film may be formed at the interface between the metal film 30 and the diode 20. Further, the metal films 30 and 60 may have a function as a barrier layer that prevents diffusion of impurities into the resistance change film 50.

  The cell 81 includes a diode 20 as a rectifying element. Thereby, even if an arbitrary cell 81 is selected by the combination of the wiring WL1 and the wiring BL1, the direction of the current flowing in the cell 81 is regulated.

  In the cell 81 of the present embodiment, the barrier metal film 40 is provided between the metal film 30 and the resistance change film 50. The silicon (Si) contained in the barrier metal film 40 has an inclination in the direction from the diode 20 toward the resistance change film 50 as shown in FIG. 4B.

  Specifically, the interface side (position A) between the barrier metal film 40 and the metal film 30 has the highest silicon (Si) concentration, and the concentration gradually decreases, and the barrier metal film 40 and the resistance change film 50 The interface side (position B) has a structure in which the concentration of silicon (Si) is the lowest.

  By interposing such a barrier metal film 40 between the diode 20 and the resistance change film 50, mutual diffusion between the component constituting the resistance change film 50 and the component constituting the diode 20 is suppressed.

  That is, when the main component of the diode 20 is contained in the barrier metal film 40, the diode 20 and the resistance change film 50 are compared with the case where the main component of the diode 20 is not contained in the barrier metal film 40. In the meantime, the concentration difference of the main component of the diode 20 is small. In particular, in this modification, the concentration of silicon (Si) on the diode 20 side is higher than the concentration of silicon (Si) on the resistance change film 50 side in the barrier metal film 40.

Therefore, in the vicinity of the interface between the barrier metal film 40 and the metal film 30, the concentration difference is smaller than that in the configuration shown in FIG. 2, and diffusion of the main component of the diode 20 into the resistance change film 50 is further suppressed.
As a result, the composition change of the resistance change film 50 and the diode 20 is less likely to occur, and the malfunction of the nonvolatile memory device and the variation in characteristics are less likely to occur.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the present invention as long as they have the characteristics of the present invention. For example, the elements included in each of the specific examples described above and their arrangement, materials, conditions, shapes, sizes, and the like are not limited to those illustrated, but can be changed as appropriate.
In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the present invention as long as they include the features of the present invention.
In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  1a, 1b memory cell array, 10, 40 barrier metal film, 20 diode, 30, 60 metal film, 50 resistance change film, 70 stopper wiring film, 80, 81 cell, 90 interlayer insulating film, WL1, WL2, BL1, BL2 wiring

Claims (7)

  1. A non-volatile memory device in which a plurality of unit memory cells are stacked,
    Each of the unit storage cells is
    A first wiring extending in a first direction;
    A second wiring extending in a second direction non-parallel to the first direction;
    A memory element provided between the first wiring and the second wiring;
    A rectifying element disposed between the first wiring or the second wiring and the memory element and connected in series to the memory element;
    Have
    An intermediate layer containing the main component of the rectifying element is provided between the memory element and the rectifying element ,
    The main component is contained in the intermediate layer below the solid solution limit of the intermediate layer,
    The nonvolatile memory device according to claim 1, wherein the concentration distribution of the main component in the intermediate layer has a slope in which the concentration of the main component decreases in a direction from the rectifying element toward the storage element .
  2.   The nonvolatile memory device according to claim 1, wherein a metal layer that is in ohmic contact with the rectifying element is provided between the rectifying element and the intermediate layer.
  3. The nonvolatile memory device according to claim 2 , wherein a layer including the main component of the rectifying element is formed between the metal layer and the rectifying element.
  4. The memory element is a nonvolatile memory device according to any one of claims 1-3, characterized in that a resistance variable memory element or phase change memory element.
  5. A first wiring extending in a first direction;
    A second wiring extending in a second direction non-parallel to the first direction;
    A method of manufacturing a nonvolatile memory device having a memory element and a rectifying element connected in series to the memory element between the first wiring and the second wiring,
    Forming a metal film on the rectifying element;
    Forming an intermediate layer containing the main component of the rectifying element on the metal film;
    Forming the memory element on the intermediate layer;
    Equipped with a,
    A non-volatile memory device , wherein the concentration distribution of the main component in the intermediate layer is formed so as to have a slope in which the concentration of the main component decreases in a direction from the rectifying element toward the memory element . Production method.
  6. 6. The method of manufacturing a nonvolatile memory device according to claim 5 , wherein after the memory element is formed on the intermediate layer, the rectifying element is activated.
  7. The intermediate layer,
    a) a method of forming by a sputtering method using a target material having a main component of the intermediate layer and a main component of the rectifying element;
    b) A method of forming by sputtering using a target material composed of the main component of the intermediate layer and another target material composed of the main component of the rectifying element,
    c) a method of forming a film composed of the main component of the intermediate layer and then injecting the main component of the rectifying element;
    The method of manufacturing a nonvolatile memory device according to claim 5 , wherein the nonvolatile memory device is formed by any one of the above.
JP2009071543A 2009-03-24 2009-03-24 Nonvolatile memory device and manufacturing method thereof Active JP5364407B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009071543A JP5364407B2 (en) 2009-03-24 2009-03-24 Nonvolatile memory device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009071543A JP5364407B2 (en) 2009-03-24 2009-03-24 Nonvolatile memory device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2010225850A JP2010225850A (en) 2010-10-07
JP5364407B2 true JP5364407B2 (en) 2013-12-11

Family

ID=43042725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009071543A Active JP5364407B2 (en) 2009-03-24 2009-03-24 Nonvolatile memory device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5364407B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9640586B2 (en) 2014-06-18 2017-05-02 Samsung Electronics Co., Ltd. Semiconductor diodes, and variable resistance memory devices

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5555136B2 (en) * 2010-11-02 2014-07-23 株式会社東芝 Storage device and manufacturing method thereof
JP5591676B2 (en) * 2010-12-14 2014-09-17 株式会社東芝 Semiconductor memory device
CN102610748B (en) * 2011-01-25 2014-02-12 中国科学院微电子研究所 Nonvolatile memory unit and memory
JP2013069922A (en) 2011-09-22 2013-04-18 Toshiba Corp Manufacturing method of nonvolatile semiconductor storage device and nonvolatile semiconductor storage device
JP2013122985A (en) * 2011-12-12 2013-06-20 Toshiba Corp Semiconductor memory device
US9543515B2 (en) * 2013-11-07 2017-01-10 Intel Corporation Electrode materials and interface layers to minimize chalcogenide interface resistance
KR20170059971A (en) * 2014-09-25 2017-05-31 인텔 코포레이션 1s1r memory cells incorporating a barrier layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6614116B1 (en) * 2002-06-04 2003-09-02 Micron Technology, Inc. Buried digit line stack and process for making same
JP4657016B2 (en) * 2004-06-14 2011-03-23 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
KR100689831B1 (en) * 2005-06-20 2007-03-08 삼성전자주식회사 Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same
US20070132049A1 (en) * 2005-12-12 2007-06-14 Stipe Barry C Unipolar resistance random access memory (RRAM) device and vertically stacked architecture
KR100883412B1 (en) * 2007-05-09 2009-02-11 삼성전자주식회사 Method of fabricating phase change memory device having self-aligned electrode, related device and electronic system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9640586B2 (en) 2014-06-18 2017-05-02 Samsung Electronics Co., Ltd. Semiconductor diodes, and variable resistance memory devices

Also Published As

Publication number Publication date
JP2010225850A (en) 2010-10-07

Similar Documents

Publication Publication Date Title
JP5042233B2 (en) Deposited semiconductor structure and fabrication method for minimizing n-type dopant diffusion
US8067815B2 (en) Aluminum copper oxide based memory devices and methods for manufacture
US8410582B2 (en) 3D polysilicon diode with low contact resistance and method for forming same
JP5044586B2 (en) Semiconductor memory device
US7426128B2 (en) Switchable resistive memory with opposite polarity write pulses
US7932506B2 (en) Fully self-aligned pore-type memory cell having diode access device
US8895949B2 (en) Nonvolatile memory device using a varistor as a current limiter element
US7534625B2 (en) Phase change memory with damascene memory element
KR20130036279A (en) Memory cell with resistance- switching layers and lateral arrangement
US9203021B2 (en) Resistance change memory and manufacturing method thereof
JP5488458B2 (en) Resistance change element and manufacturing method thereof
US8995172B2 (en) Nonvolatile memory device having a current limiting element
US8013317B2 (en) Nonvolatile storage device and method for manufacturing same
EP2697839B1 (en) Vertical memory cell for high-density memory
US8599603B2 (en) Resistive-switching nonvolatile memory elements
JP5553285B2 (en) Memory architecture using resistance change with multiple memory cells per access element
US9093368B2 (en) Nonvolatile memory cells and arrays of nonvolatile memory cells
US8513636B2 (en) Vertical diodes for non-volatile memory device
US8541765B2 (en) Resistance variable memory cell structures and methods
KR101039923B1 (en) Nonvolatile memory device and method for manufacturing same
US8772751B2 (en) Variable resistance semiconductor memory device
US9275727B2 (en) Multi-level memory array having resistive elements for multi-bit data storage
KR101390341B1 (en) Phase-changeable memory devices
US9825223B2 (en) Fin selector with gated RRAM
EP3178113B1 (en) Fully isolated selector for memory device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110325

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130522

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130527

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130726

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130819

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130909

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350