KR101873502B1 - Light emitting diode chip and method of fabricating the same - Google Patents

Abstract

A light emitting diode chip and a method for manufacturing the same are disclosed. The light emitting diode chip comprises a substrate; A light emitting structure disposed on the substrate, the active layer including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; An alternating layered structure for reflecting light emitted from the light emitting structure; And an interfacial layer positioned between the substrate and the alternating laminate structure, wherein the alternating laminate structure comprises a plurality of dielectric pairs each comprising a first material layer of high refractive index and a second material layer of low refractive index, Wherein the plurality of dielectric pairs comprise a plurality of first dielectric pairs of a first material layer and a second material layer having an optical thickness less than? / 4, with respect to a central wavelength? Of a visible light region; Wherein at least one of the first material layer and the second material layer comprises a first material layer having an optical thickness less than lambda / 4 and an optical thickness greater than lambda / 4, pair; And a plurality of third dielectric pairs of a first material layer and a second material layer having an optical thickness greater than? / 4.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode chip,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode chip and a method of manufacturing the same. More particularly, the present invention relates to a light emitting diode chip with improved light emitting efficiency and a method of manufacturing the same.

Gallium nitride series light emitting diodes emitting blue or ultraviolet rays have been applied to various applications. In particular, various kinds of light emitting diode packages which emit mixed color light such as white light required for a backlight unit or general illumination are commercially available.

Since the light output of the light emitting diode package depends mainly on the light efficiency of the light emitting diode chip, efforts to improve the light efficiency of the light emitting diode chip are continuing. For example, efforts have been made to improve the light extraction efficiency by forming a rough surface on the light emitting surface, or adjusting the shape of the epilayer or the shape of the transparent substrate.

On the other hand, a metal reflector such as Al is provided on the opposite side of the light emitting surface to reflect light traveling toward the chip mounting surface, thereby improving the light efficiency. By reflecting light using a metal reflector, the light loss can be reduced and the luminous efficiency can be improved. However, the reflective metal is generally oxidized to tend to degrade reflectance, and the reflectivity of the metal reflector is not relatively high.

Recently, a technique of achieving a high reflectance and achieving a relatively stable reflection characteristic by using a structure in which materials having different refractive indices are alternately laminated is being studied.

However, such an alternately laminated structure generally has a high reflectance in a narrow wavelength range and a low reflectance in other wavelength ranges. Therefore, the light-emitting diode package which realizes white light by using wavelength-converted light by a phosphor or the like does not exhibit an effective reflection characteristic for the wavelength-converted light, and thus there is a limit to the improvement of the light efficiency in the package. In addition, the alternately laminated structure has a high reflectance for vertically incident light, but tends to exhibit a relatively low reflectance for light having a relatively large incident angle.

On the other hand, it is possible to extend the wavelength range in which the reflectance is high by increasing the total number of layers of the alternately laminated structure and adjusting the thickness of each layer. However, since the number of total layers of the alternately laminated structure is large, it is not easy to adjust the thickness of each layer, and the thickness of each layer is changed every time the total number of layers is changed. It is difficult.

A problem to be solved by the present invention is to provide a light emitting diode chip improved in luminous efficiency.

Another object of the present invention is to provide a light emitting diode chip capable of improving light efficiency in a package.

Another object to be solved by the present invention is to provide a light emitting diode chip and a method of manufacturing the same which are easy to set the thicknesses and the stacking order of each layer of the alternate laminated structure.

According to one aspect of the present invention, there is provided a light emitting diode chip comprising: a substrate; A light emitting structure disposed on the substrate, the active layer including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; And an alternately laminated substructure located below the substrate. The substructure includes a plurality of dielectric pairs each comprising a first material layer of high refractive index and a second material layer of low refractive index. Furthermore, the plurality of dielectric pairs may include a plurality of first dielectric pairs, each of the first dielectric layer and the second material layer having a first material layer and a second material layer having an optical thickness of less than? / 4, for a center wavelength of the visible light region; Wherein at least one of the first material layer and the second material layer comprises a first material layer having an optical thickness less than lambda / 4 and an optical thickness greater than lambda / 4, pair; And a plurality of third dielectric pairs of a first material layer and a second material layer both having an optical thickness greater than? / 4.

The first dielectric pairs and the second dielectric pairs can be disposed based on the second dielectric pair so that the order of stacking of the plurality of dielectric pairs can be easily set. For example, the plurality of first dielectric pairs may be located closer or further to the substrate relative to the plurality of third dielectric pairs. Further, the at least one second dielectric pair may be disposed near the center of the substructure.

Wherein at least a majority of the plurality of first dielectric pairs may be located closer to the substrate than a second dielectric pair closest to the substrate and at least a majority of the plurality of third dielectric pairs is located farther from the substrate than the second dielectric ≪ RTI ID = 0.0 > substrate. ≪ / RTI > For example, at least 80% of the plurality of first dielectric pairs are located closer to the substrate than the second dielectric pair closest to the substrate, and at least 80% of the plurality of third dielectric pairs are the most distant from the substrate And may be located further from the substrate than the second dielectric pair. Further, the plurality of first dielectric pairs may be located closer to the substrate than the plurality of third dielectric pairs.

Alternatively, at least a majority of the plurality of third dielectric pairs are located closer to the substrate than a second dielectric pair closest to the substrate, and at least a majority of the plurality of first dielectric pairs are located in a second dielectric Lt; RTI ID = 0.0 > substrate. ≪ / RTI > Further, the plurality of first dielectric pairs may be located further away from the substrate than the plurality of third dielectric pairs.

On the other hand, the light emitting diode chip is disposed above the light emitting structure, and transmits light generated in the active layer, and alternately stacks a light emitting layer, which reflects light in at least a partial region of a visible light ray having a longer wavelength than a wavelength of light generated in the active layer, And may further include a superstructure. It is possible to prevent light that has been wavelength-converted by the upper structure, that is, light having a relatively long wavelength, from being incident into the light emitting diode chip.

The transmittance of the upper structure with respect to the light generated in the active layer may be 90% or more, and may be 98% or more.

The light emitting diode chip may further include: an electrode pad electrically connected to the second conductivity type semiconductor layer; And an alternating layered under structure interposed between the second conductive type semiconductor layer and the electrode pad. The under structure reflects light generated in the active layer. Accordingly, light generated in the active layer can be prevented from being absorbed by the electrode pad and lost.

Furthermore, the light emitting diode chip may further include a metal reflector located under the lower structure. The combination of the lower structure or the lower structure and the metal reflector may exhibit a reflectance of 90% or more with respect to light generated in the active layer and incident at an incident angle of 0 to 60 degrees.

According to another aspect of the present invention, there is provided a method of manufacturing a light emitting diode chip, comprising: preparing a substrate including at least one light emitting structure on a substrate; and forming an alternate stacked structure on the substrate lower surface. The substructure includes a plurality of dielectric pairs each comprising a first material layer of high refractive index and a second material layer of low refractive index. Further, the plurality of dielectric pairs may include a plurality of first dielectric pairs, each of the first dielectric layer and the second material layer having a first material layer and a second material layer having an optical thickness smaller than? / 4, for a center wavelength of the visible light region; Wherein at least one of the first material layer and the second material layer comprises a first material layer having an optical thickness less than lambda / 4 and an optical thickness greater than lambda / 4, pair; And a plurality of third dielectric pairs of a first material layer and a second material layer both having an optical thickness greater than? / 4.

On the other hand, forming the substructure can include setting the optical thickness of each layer in the plurality of dielectric pairs and the stacking order of the plurality of dielectric pairs, and sequentially forming each layer on the substrate in accordance with the order have. At this time, the stacking order may be set such that the plurality of first dielectric pairs are arranged closer or further to the substrate relative to the plurality of third dielectric pairs. The combination of the plurality of dielectric pairs can be easily extracted by predetermining the stacking order of the first dielectric pairs and the third dielectric pairs.

Furthermore, the stacking order can be set so that the at least one second dielectric pair is disposed near the center of the lower structure. Thus, first dielectric pairs and second dielectric pairs may be positioned relative to the second dielectric pair.

Wherein at least a majority of the plurality of first dielectric pairs is located closer to the substrate than a second dielectric pair nearest to the substrate and at least a majority of the plurality of third dielectric pairs is located closer to the substrate than a second dielectric pair farthest from the substrate The stacking order can be set to be further away from the substrate. Alternatively, at least a majority of the plurality of third dielectric pairs is located closer to the substrate than a second dielectric pair closest to the substrate, and at least a majority of the plurality of first dielectric pairs is a second dielectric pair The stacking order can be set so as to be located further from the substrate than the stacking order.

Furthermore, a metal reflector may be formed on the plurality of dielectric pairs.

In addition, the method of fabricating the LED chip may further include forming an alternating layered superstructure on the light emitting structure. The upper structure transmits light generated in the active layer and reflects light in at least a part of a visible light region having a wavelength longer than the wavelength of light generated in the active layer.

According to the embodiments of the present invention, it is possible to provide a light emitting diode chip in which the luminous efficiency is improved by adopting the alternate laminated substructure, the metal reflector, the alternate laminated superstructure and / or the alternately laminated under structure. Further, by adopting the above-mentioned alternately laminated superstructure, it is possible to reflect the wavelength-converted light while transmitting the light generated in the active layer, thereby improving the light efficiency in the package.

On the other hand, the dielectric layer pairs in which the optical thickness is less than 1/4 of all at the center wavelength of 1/4, the dielectric layer pairs in which both layers are larger than 1/4, and one is smaller than 1/4, The thickness of each layer of the alternately laminated substructure and the stacking order can be easily set.

1 is a cross-sectional view illustrating a light emitting diode chip according to an embodiment of the present invention.
2 is a graph for explaining the optical thickness and order of the alternately stacked substructure according to an embodiment of the present invention.
Fig. 3 is a graph for explaining the reflectance of the alternately laminated substructure of Fig. 2. Fig.
4 is a graph illustrating the transmittance of the alternately stacked superstructure according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating a package including a light emitting diode chip according to an embodiment of the present invention. Referring to FIG.
6 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention.
7 is a cross-sectional view illustrating a light emitting diode chip according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is a cross-sectional view illustrating a light emitting diode chip 100 according to an embodiment of the present invention.

1, a light emitting diode chip 100 includes a substrate 21, a light emitting structure 30, an alternating stacked structure 43, an alternate stacked structure 37, and an alternating stacked under structure 39 . The light emitting diode chip 100 includes a buffer layer 23, a transparent electrode 31, a first electrode pad 33, a second electrode pad 35, an interface layer 41, and a metal reflector 45 can do.

The substrate 21 is not particularly limited as long as it is a transparent substrate, and may be, for example, a sapphire or SiC substrate. The substrate 21 may also have a predetermined pattern, such as a sapphire substrate (PSS) patterned on the top surface. The substrate 21 may be a growth substrate suitable for growing gallium nitride-based compound semiconductor layers.

A light emitting structure 30 is disposed on the substrate 21. The light emitting structure 30 includes a first conductive semiconductor layer 25, a second conductive semiconductor layer 29 and an active layer 27 interposed between the first and second conductive semiconductor layers 25 and 29. ). Here, the first conductivity type and the second conductivity type may be opposite to each other, the first conductivity type may be n-type, the second conductivity type may be p-type, or vice versa.

The first conductive semiconductor layer 25, the active layer 27 and the second conductive semiconductor layer 29 may be formed of a gallium nitride compound semiconductor material, that is, (Al, In, Ga) N. The compositional element and the composition ratio are determined so that the active layer 27 emits light of a desired wavelength, for example, ultraviolet light or blue light. As shown in the figure, the first conductive semiconductor layer 25 and / or the second conductive semiconductor layer 29 may be formed as a single layer or may have a multi-layer structure. In addition, the active layer 27 may be formed in a single quantum well structure or a multiple quantum well structure. In addition, a buffer layer 23 may be interposed between the substrate 21 and the first conductivity type semiconductor layer 25.

The semiconductor layers 25, 27, and 29 may be formed using MOCVD or MBE techniques, and may be patterned to expose a portion of the first conductive semiconductor layer 25 using a photolithography and etching process. have.

On the other hand, the transparent electrode layer 31 may be formed of ITO or Ni / Au on the second conductivity type semiconductor layer 29, for example. The transparent electrode layer 31 has a lower resistivity than the second conductivity type semiconductor layer 29, and thus the current is dispersed. A first electrode pad 33 such as an n-electrode pad 33 is formed on the first conductive semiconductor layer 25 and a second electrode pad 35 such as a p- An electrode pad 35 is formed. The p-electrode pad 35 may be electrically connected to the second conductive semiconductor layer 29 through the transparent electrode layer 31 as shown in the figure.

(Alternately stacked bottom structure 43)

The lower structure 43 is located below the substrate 21. The lower structure 43 is formed by alternately laminating a first material layer having a first refractive index, such as TiO2 (n: about 2.4) and a second material layer having a second refractive index, such as SiO2 (n: about 1.5) do. The lower structure 43 has a plurality of dielectric pairs in order to exhibit a reflectance of 90% or more in a range of 0 to 60 degrees of incidence angle of the incident light generated in the active layer. Furthermore, the plurality of dielectric pairs are formed to have a high reflectance in a wavelength range of 400 to 700 nm, for example.

For example, as shown in Fig. 2, the plurality of dielectric pairs may be formed of a first material layer having an optical thickness smaller than? / 4 (0.25?) And a second material layer having a second wavelength One of the first and second material layers being a first material layer having an optical thickness less than lambda / 4 and the other having an optical thickness greater than lambda / 4; At least one second dielectric pair of two material layers, and a plurality of third dielectric pairs of a first material layer and a second material layer both having an optical thickness greater than? / 4.

As can be seen in the graph of FIG. 2, the plurality of first dielectric pairs may be located further to the substrate 21 relative to the plurality of third dielectric pairs. Conversely, the plurality of first dielectric pairs may be located closer to the substrate 21 relative to the plurality of third dielectric pairs.

In addition, the at least one second dielectric pair (circled circle) is disposed near the center of the lower structure. The first dielectric pairs of the majority (more than half, preferably more than 80% of them) and the second dielectric pairs of the majority (more than half, preferably more than 80%) are opposed to each other on the basis of the second dielectric pairs Can be located. In Figure 2, there are 20 total dielectric pairs, 9 first dielectric pairs and 3 second dielectric pairs, and 2 second dielectric pairs. However, the present invention is not particularly limited to the number of pairs, but the number of first dielectric pairs and third dielectric pairs is relatively more than the number of second dielectric pairs.

On the other hand, a small number of third dielectric pairs may be present between the second dielectric pair and most of the first dielectric pairs, and a small number of second dielectric pairs may be interposed between the second dielectric pair and most of the third dielectric pairs have.

Fig. 3 illustrates a result of simulating reflectance by disposing a plurality of dielectric pairs shown in Fig. 2 on a glass (n: ~ 1.5). In Figure 3, a plurality of dielectric pairs are arranged in the order illustrated in Figure 2, the first layer being TiO2 and the last layer being SiO2.

As shown in FIG. 3, the plurality of dielectric pairs exhibit a reflectance of 98% or more over a wide visible light wavelength range of 400 to 700 nm. Such a reflectance can be expected to be sufficiently high even if the incident angle of the blue light (for example, 460 nm) generated in the active layer 27 is increased close to 60 degrees.

1, a metal reflector 45 such as Al is disposed under the lower structure 43, so that the metal reflector 45 and the lower structure (see FIG. 1) 43), it is possible to maintain a high reflectance of 90% or more with respect to light having an incident angle of 0 to 60 degrees. The metal reflector 45 also helps dissipate the heat generated from the light emitting diode to the outside when the light emitting diode chip 100 is driven.

The lower structure 43 is formed on the lower surface of the substrate 21 on which the light emitting structure 30 is formed. The underlying structure 43 may be formed using, for example, ion assist deposition (SOA) equipment, and the optical thickness and order of each layer of the underlying structure 43 may be set prior to formation using the deposition equipment .

The optical thickness and order of each layer of the lower structure 43 may be set using a simulation tool. However, it is difficult to set an appropriate number of dielectric pairs having a reflectance of 98% or more with the simulation tool alone, and work such as adding the number of total dielectric pairs and adding dielectric pairs to increase the reflectance must be performed by the operator. At this time, since the optical thickness of the entire dielectric pair is changed according to the position and optical thickness of one pair to be added, it is difficult to set the position and the optical thickness, and the target thickness varies depending on the operator.

The present invention is characterized in that the first dielectric pairs are divided into first dielectric pairs, second dielectric pairs and third dielectric pairs in a plurality of dielectric pairs, and the second dielectric pairs are arranged near the center, 2 < / RTI > dielectric pairs are spaced apart from each other, thereby facilitating the task of setting the optical thickness and order of each layer. For example, if the first dielectric pairs are located so as to be located further from the substrate 21 than the second dielectric pairs, if the newly added dielectric pair belongs to the first dielectric pair, its position is set in the first dielectric pairs . This makes it easy to set the optical thicknesses of the plurality of dielectric pairs and their order.

On the other hand, as the plurality of dielectric pairs are formed by using the ion assist deposition equipment, relatively high density layers are formed, and stress may be generated between the substrate 21 and the lower structure 43. Therefore, the interface layer 41 may be formed to improve the adhesion of the lower structure 43 to the substrate 21 before the lower structure 43 is formed. The interface layer 41 may be formed of the same material as the SiO 2 of the lower structure 43.

(Alternately stacked upper structure 37)

Referring again to FIG. 1, an alternating stacked structure 37 is located on top of the light emitting structure 30. The upper structure 37 may cover the transparent electrode layer 31 and cover the exposed surface of the first conductive type semiconductor layer 25, as shown in the figure.

The upper structure 37 transmits the light generated in the active layer 27 and reflects light emitted from the outside into the LED chip 100, for example, light emitted from the phosphor. Therefore, the upper structure 37 transmits light in the blue or short-wavelength ultraviolet region generated in the active layer 27, and reflects light in the green to red region, particularly, in the yellow region.

4 is a simulation graph showing the transmittance of the upper structure 37 in which TiO2 and SiO2 are alternately stacked. Here, it was simulated that 14 layers of TiO 2 and SiO 2 were arranged on the glass substrate, respectively. As shown in FIG. 4, by controlling the optical thicknesses of TiO 2 and SiO 2, it is possible to provide a superstructure 37 that exhibits a transmittance of 98% or more for near-ultraviolet or blue light of less than 500 nm and blocks light above about 500 nm have. Accordingly, the upper structure 37 transmits the light emitted from the active layer 27 and can reflect light emitted from the phosphor, that is, light in the green to yellow region.

The upper structure 37 may also cover the mesa sidewalls and cover the upper surface of the LED chip 100 except for the upper surface of the electrode pads 33 and 35 to protect the LED chip 100 Can be performed.

(Alternating laminated under structure 39)

The alternating layered under structure 39 is located between the electrode pad 35 and the second conductivity type semiconductor layer 29. The under structure 39 may be positioned below the transparent electrode 39, but it is not limited thereto and may be located on the transparent electrode 39. The electrode pad 35 can be electrically connected to the transparent electrode 39 through an extended portion (not shown) when the transparent electrode 39 is located between the under structure 39 and the transparent electrode 39 and the electrode pad 35. [

The under structure 39 reflects light generated in the active layer 27 and traveling toward the electrode pad 35 side. The under structure 39 is formed to have a high reflectivity with respect to light generated in the active layer 27, and may be formed by alternately laminating TiO2 and SiO2, for example. Accordingly, light is absorbed by the electrode pad 35 and is prevented from being lost, thereby improving the luminous efficiency.

5 is a cross-sectional view illustrating a light emitting diode package in which the light emitting diode chip 100 according to the embodiment of the present invention is mounted.

Referring to FIG. 5, the light emitting diode package includes a package body 60, leads 61a and 61b, a light emitting diode chip 100, and a molding part 63. The package body 60 may be formed of a plastic resin.

The package body 60 may have a mounting surface M for mounting the light emitting diode chip 100 and may have a reflecting surface R on which light emitted from the light emitting diode chip 100 is reflected. Meanwhile, the LED chip 100 is mounted on the mount M and is electrically connected to the leads 61a and 61b through bonding wires. The light emitting diode chip 100 may be attached to the mounting surface M by an adhesive 62, and the adhesive may be formed by curing an Ag epoxy paste, for example.

The light emitting diode chip 100 may have a lower structure 43 and an upper structure 37, an under structure 39 and / or a metal reflector 45, as described with reference to FIG.

The light emitting diode package may emit a mixed color light, for example, white light, and may include a phosphor for wavelength conversion of the light emitted from the light emitting diode chip 100. The phosphor may be contained in the molding part 63, but is not limited thereto.

The light emitting diode chip 100 may include a lower structure 43 and a circumference structure 39 to emit light generated in the active layer 27 to the outside with high efficiency. Also, since the LED chip 100 includes the upper structure 37, it is possible to reflect the wavelength-converted light from the phosphor into the LED chip 100 again. Accordingly, a light emitting diode package having higher light efficiency than the conventional light emitting diode package can be provided.

In this embodiment, a package including a phosphor together with the light emitting diode chip 100 for realizing white light is described, but the present invention is not limited thereto. Various packages for emitting white light are known, and the light emitting diode chip 100 is applicable to any package.

6 is a cross-sectional view illustrating a light emitting diode chip 200 according to another embodiment of the present invention.

6, the light emitting diode chip 200 includes a plurality of light emitting cells on a substrate 21 and includes a lower structure 43, a metal reflector 45, and a superstructure 37 .

Since the substrate 21 and the lower structure 43 are the same as those described with reference to FIG. 1, detailed description thereof will be omitted. However, the substrate 21 is preferably an insulator for electrically isolating a plurality of light emitting cells, and may be, for example, a patterned sapphire substrate.

The plurality of light emitting cells 30 are spaced apart from each other. Each of the plurality of light emitting cells 30 is the same as the light emitting structure 30 described with reference to FIG. 3, and thus a detailed description thereof will be omitted. In addition, a buffer layer 23 may be interposed between the light emitting cells 30 and the substrate 21, and the buffer layer 23 may be spaced apart from each other.

The first insulating layer 36 covers the entire surface of the light emitting cells 30. The first insulating layer 36 has openings on the first conductivity type semiconductor layers 25 and also has openings on the second conductivity type semiconductor layers 29. The sidewalls of the light emitting cells 30 are covered with a first insulating layer 36. The first insulating layer 36 also covers the substrate 21 in regions between the light emitting cells 30. The first insulating layer 36 may be formed of a silicon oxide film (SiO ₂ ) or a silicon nitride film, and may be formed at a temperature ranging from 200 to 300 ° C. by a plasma CVD method.

On the other hand, wirings 51 are formed on the first insulating layer 36. The wirings 51 are electrically connected to the first conductive type semiconductor layers 25 and the second conductive type semiconductor layers 29 through the openings. The transparent electrode layers 31 may be positioned on the second conductive type semiconductor layers 29 and the wirings may be connected to the transparent electrode layers 31. The wires 51 electrically connect the first conductivity type semiconductor layers 25 and the second conductivity type semiconductor layers 29 of the adjacent light emitting cells 30 to form a series of the light emitting cells 30. [ An array can be formed. A plurality of such arrays may be formed, and a plurality of arrays may be connected in antiparallel to each other and connected to an AC power source to be driven. Further, a bridge rectifier (not shown) connected to the serial array of the light emitting cells may be formed, and the light emitting cells may be driven by the bridge rectifier under the AC power. The bridge rectifier can be formed by connecting the light emitting cells having the same structure as the light emitting cells 30 by using the wirings 51.

Alternatively, the wirings may connect the first conductive semiconductor layers 25 of adjacent light emitting cells to each other or connect the second conductive semiconductor layers 29 to each other. Accordingly, a plurality of light emitting cells 30 connected in series and in parallel can be provided.

The wirings 51 may be formed of a conductive material, for example, a doped semiconductor material such as polycrystalline silicon, or a metal. In particular, the wirings 51 may be formed in a multilayer structure, for example, a lower layer of Cr or Ti and an upper layer of Cr or Ti. Further, a metal layer of Au, Au / Ni or Au / Al may be interposed between the lower layer and the upper layer.

An alternate stacked top structure 37 may cover the wires 51 and the first insulating layer 36. The upper structure 37 transmits light generated in the active layer 27 and reflects relatively long wavelength visible light as described with reference to Fig.

On the other hand, the phosphor layer 53 may be positioned on the light emitting diode chip 200. The phosphor layer 53 may be a layer in which phosphors are dispersed in a resin or a layer deposited by an electrophoresis method. The phosphor layer 53 covers the upper structure 37 to wavelength-convert the light emitted from the light emitting cells 30. The phosphor layer 53 may be provided at a package level as described with reference to FIG. 5, and thus may be omitted from the light emitting diode chip 200.

Meanwhile, an under structure may be formed between the wires 51 and the light emitting cells 30 as shown in FIG.

7 is a cross-sectional view illustrating a light emitting diode chip 200a having a plurality of light emitting cells according to another embodiment of the present invention.

7, the light emitting diode chip 200a according to the present embodiment is substantially similar to the light emitting diode chip 200 described above. However, the shape of the light emitting cells 30 is different, The portion of the first conductivity type semiconductor layer 25 is different.

The upper surface of the first conductivity type semiconductor layer 25 is exposed in the light emitting cells 30 of the light emitting diode chip 200 and the wiring 51 is formed on the upper surface of the first conductivity type semiconductor layer 25 . The light emitting cells 30 of the light emitting diode chip 200a according to the present embodiment are formed to have inclined sides so that the inclined side surfaces of the first conductivity type semiconductor layer 25 are exposed, Is connected to the inclined side surface of the first conductivity type semiconductor layer (25).

Therefore, according to the present embodiment, it is not necessary to separately perform the step of exposing the upper surface of the first conductivity type semiconductor layer 25 in addition to the step of separating the light emitting cells, thereby simplifying the process. Furthermore, since it is not necessary to expose the upper surface of the first conductivity type semiconductor layer 25, the area of the active layer 27 can be prevented from being reduced. In addition, since the wiring 51 is connected along the inclined surface of the first conductivity type semiconductor layer 25, the current dispersion performance of the light emitting cell 30 can be improved, thereby improving the forward voltage and reliability.

Claims (16)

Board;
A light emitting structure disposed on the substrate, the active layer including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
An alternating layered structure for reflecting light emitted from the light emitting structure; And
An interfacial layer positioned between the substrate and the alternating layered structure,
Wherein the alternating laminate structure comprises a plurality of dielectric pairs each comprising a first material layer of high refractive index and a second material layer of low refractive index,
The plurality of dielectric pairs are arranged such that, with respect to a central wavelength lambda of a visible light region,
a plurality of first dielectric pairs of a first material layer and a second material layer having an optical thickness less than lambda / 4;
Wherein at least one of the first material layer and the second material layer comprises a first material layer having an optical thickness less than lambda / 4 and an optical thickness greater than lambda / 4, pair; And
and a plurality of third dielectric pairs made up of a first material layer and a second material layer having an optical thickness greater than? / 4. The method according to claim 1,
Wherein the plurality of first dielectric pairs are located closer or further to the substrate relative to the plurality of third dielectric pairs. The method of claim 2,
Wherein the at least one second dielectric pair is disposed near the center of the alternating laminated structure. The method according to claim 1,
Wherein at least a majority of the plurality of first dielectric pairs is located closer to the substrate than a second dielectric pair closest to the substrate,
Wherein at least a majority of said plurality of third dielectric pairs is located further from said substrate than a second dielectric pair farthest from said substrate. The method of claim 4,
Wherein at least 80% of the plurality of first dielectric pairs are located closer to the substrate than a second dielectric pair closest to the substrate,
Wherein at least 80% of the plurality of third dielectric pairs are located further from the substrate than a second dielectric pair farthest from the substrate. The method of claim 4,
Wherein the plurality of first dielectric pairs are located closer to the substrate than the plurality of third dielectric pairs. The method according to claim 1,
At least a majority of said plurality of third dielectric pairs being located closer to said substrate than a second dielectric pair nearest said substrate,
Wherein at least a majority of said plurality of first dielectric pairs is located further from said substrate than a second dielectric pair farthest from said substrate. The method of claim 7,
Wherein the plurality of first dielectric pairs are located further away from the substrate than the plurality of third dielectric pairs. The method according to claim 1,
And an electrode pad electrically connected to the second conductivity type semiconductor layer. The method according to claim 1,
And a metal reflector in contact with the alternating laminated structure. The method according to claim 1,
Wherein the first layer in contact with the interfacial layer in the alternating laminated structure is a first material layer of high refractive index. The method of claim 11,
Wherein the first material layer in contact with the interface layer is a TiO2 layer. The method of claim 12,
Wherein the interfacial layer improves the adhesion of the alternating laminated structure to the substrate. The method of claim 12,
Wherein the interface layer has a lower refractive index than the first material layer. delete The method according to claim 1,
And the interface layer is in contact with the substrate.

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