KR101873255B1 - Method for manufacturing semiconductor device by epitaxial lift-off using plane dependency of iii-v compound - Google Patents

Abstract

A method of manufacturing a semiconductor device by an epitaxial lift-off (ELO) method includes the steps of: forming a sacrificial layer containing a group III-V compound on a first substrate; Forming an element layer on the sacrificial layer; Patterning the sacrificial layer and the device layer in a shape having a portion extending along a first direction determined based on a crystal plane direction of the III-V group compound of the sacrificial layer; Bonding the patterned element layer onto a second substrate; And etching the sacrificial layer using an etching solution in a state where the device layer is bonded onto the second substrate to remove the sacrificial layer and the first substrate. The method of manufacturing the semiconductor device can improve the process yield and speed up the process speed by using the difference in etch rate according to the cystal orientation which is the intrinsic property of the group III-V compound in the ELO process.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device by epitaxial lift-off using a plane direction dependence of a Group III-V compound,

Embodiments relate to a method of manufacturing a semiconductor device by epitaxial lift-off (ELO) using the plane direction dependence of a group III-V compound.

Silicon (Si) has been applied to various semiconductor devices, and representative examples thereof include solar cells and transistors. However, there has been no report on the efficiency improvement of solar cells since the mid-2000s. In addition, although the transistor is currently undergoing a process of about 20 nanometers (nm) node, problems are caused by the short channel effect. Therefore, next-generation technology that can replace silicon-based devices is required.

One of the alternatives to silicon-based devices is the active use of III-V compounds that have high mobility, have a direct bandgap structure, and are easy to bandgap engineering. III-V compounds such as gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride (GaN) have a variety of advantages. However, the current industry has a silicon-based platform, There is a limit to be overcome.

In order to overcome the above-mentioned problems, a III-V buffer layer growth method for growing a III-V material on a silicon substrate is under study. However, when the III-V buffer layer growth method is used, problems such as lattice mismatch between the silicon substrate and the III-V compound layer, differences in thermal expansion coefficient, There is a problem that the quality of the final device is deteriorated.

Alternatively, III-V compounds may be epitaxially layered on a III-V substrate in order to solve the problem that it is difficult and costly to directly grow III-V compounds on the silicon substrate. A III-V group compound is bonded on a silicon substrate, and a III-V group substrate is removed by an epitaxial lift-off (ELO) method. However, the conventional ELO technique requires a long time for the process using the substrate bonding technique using a thin sacrificial layer, and there is a problem that the substrate is damaged by the etchant on the substrate surface due to a long process time after the bonding.

Patent Registration No. 10-1455724

According to an aspect of the present invention, there is provided a method of manufacturing a III-V compound (III-V) compound in a wafer bonding and an epitaxial lift-off (ELO) It is possible to provide a method of manufacturing a semiconductor device in which the process speed is increased by using a difference in etching rate according to a cystal orientation which is an intrinsic characteristic of the semiconductor device.

According to one embodiment, a method of manufacturing a semiconductor device by an epitaxial lift-off (ELO) method includes: forming a sacrificial layer including a group III-V compound on a first substrate; Forming an element layer on the sacrificial layer; Patterning the sacrificial layer and the device layer in a shape having a portion extending along a first direction determined based on a crystal plane direction of the III-V group compound of the sacrificial layer; Bonding the patterned element layer onto a second substrate; And etching the sacrificial layer using an etching solution in a state where the device layer is bonded onto the second substrate to remove the sacrificial layer and the first substrate.

The III-V compound has a different etch rate for each crystal plane direction. In one embodiment, the first direction is a direction orthogonal to the lattice direction in which the etching rate of the III-V compound in the sacrificial layer is the fastest.

In one embodiment, the step of etching the sacrificial layer includes etching the side of the sacrificial layer from a second direction orthogonal to the first direction.

In one embodiment, the III-V compound of the sacrificial layer has a (100) crystal face, and the first direction is a <001> lattice direction. In another embodiment, the Group III-V compound of the sacrificial layer has a (110) crystal face, and the first direction is a <-100> lattice direction.

In one embodiment, the etching solution comprises hydrogen fluoride (HF) and deionized water. For example, the volumetric ratio of hydrogen fluoride (HF) and deionized water in the etching solution may be 1: 3.

The method of manufacturing a semiconductor device by ELO according to an embodiment further includes forming an etch stop layer on the first substrate before forming the sacrificial layer.

In one embodiment, the first substrate comprises a Group III-V compound, and the sacrificial layer is formed on the first substrate in an epitaxial growth manner.

In one embodiment, the second substrate comprises silicon (Si).

According to one aspect of the present invention, a method of manufacturing a semiconductor device by an epitaxial lift-off (ELO) method can be applied to wafer bonding for integration of a III-V compound and a silicon (Si) ) And ELO process, the process yield can be improved and the process speed can be made faster than the conventional ELO process by using the difference in etch rate according to the cystal orientation, which is an intrinsic property of the group III-V compound.

A method of manufacturing a semiconductor device by ELO according to an aspect of the present invention is a method of manufacturing a semiconductor device having a high etching rate in a patterning process before bonding with a silicon (Si) substrate, regardless of the orientation of a wafer on which a group III- It is possible to improve the process speed by patterning to select the surface.

In addition, the method of manufacturing a semiconductor device by ELO according to an aspect of the present invention can be utilized in the formation of various platforms in which a group III-V compound is located on silicon (Si) in the current non-memory semiconductor field Since the wafer can be reused, it is possible to reduce the cost, which is an entry barriers to the use of the III-V compound, and solve the problem of the area limitation of the wafer, which is a barrier to commercialization of the conventional ELO technology.

In addition, the method of manufacturing a semiconductor device by ELO according to one aspect of the present invention is not limited to a silicon (Si) junction and can be widely used in the heterojunction bonding of a substrate made of III-V compound and another material , And can be applied to the fabrication of multi-junction devices (e.g., solar cells, etc.) having a large material mismatch.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conceptual diagram for explaining a difference in etching rate according to an etching surface of a group III-V compound. FIG.
FIGS. 2A to 2C are conceptual diagrams for explaining a direction in which the etching rate is fast according to the surface orientation of a group III-V compound.
3 is a flowchart of a method of manufacturing a semiconductor device by an epitaxial lift-off (ELO) method according to an embodiment.
4A and 4B are a cross-sectional view and a plan view for explaining one step of a method of manufacturing a semiconductor device according to an embodiment.
5A and 5B are cross-sectional views and plan views for explaining still another step of the method of manufacturing a semiconductor device according to an embodiment.
6A and 6B are cross-sectional views and plan views for explaining still another step of the method of manufacturing a semiconductor device according to an embodiment.
7A and 7B are a cross-sectional view and a plan view for explaining another step of the method of manufacturing a semiconductor device according to an embodiment.
8A and 8B are cross-sectional views and plan views for explaining still another step of the method of manufacturing a semiconductor device according to an embodiment.
9A and 9B are a plan view and a flowchart for explaining another step of the method of manufacturing a semiconductor device according to an embodiment.
10 is an image showing an etched surface of a sacrifice layer in an ELO process according to a conventional technique.
11 is an image showing an etched surface of a sacrifice layer in a method of manufacturing a semiconductor device by ELO according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conceptual diagram for explaining a difference in etching rate according to an etching surface of a group III-V compound. FIG.

1 shows a surface of a gallium arsenide (GaAs) substrate 1 having a (100) crystal plane. As shown, a sacrificial layer 10, 30 made of GaAs is grown in an epitaxy manner on the surface of the substrate 1 in different directions, and the sacrificial layers 10, It is assumed that photoresist patterns 20 and 40 are formed on the sacrificial layer 10 and patterned in a shape elongated in one direction by etching the sacrificial layer 10 and 20 using the sacrificial layer 10 and 20 as a mask.

In this case, the sacrificial layer 10 is etched with respect to the (111) crystal face of the sacrificial layer 10 and the sacrificial layer 10 is etched at a (111) B The facet of the sacrificial layer 10 not covered by the photoresist 20 is removed at a high speed because the photoresist 20 is disposed in a shape in which the sacrificial layer 10 is etched from the surface direction, The sacrificial layer 10 can be patterned in the same manner as the shape of the resist 20. On the other hand, in the case of the sacrificial layer 30, the photoresist 40 is arranged in a shape in which the sacrificial layer 40 is etched from the (111) A-plane direction where the crystal plane end is a group III element and the etching rate is relatively slow , It takes a relatively long time to remove the portion of the sacrificial layer 30 not covered by the photoresist 40.

FIGS. 2A to 2C are conceptual diagrams for explaining a direction in which the etching rate is fast according to the surface orientation of a group III-V compound.

2A shows a surface of a gallium arsenide (GaAs) substrate having a (100) crystal plane. As shown in FIG. 2A, the (100) crystal face of gallium arsenide (GaAs) exhibits a relatively fast etch rate when etched in the <001> lattice direction as compared to the other directions. Therefore, when the device is patterned so as to extend in the direction perpendicular to the <001> lattice direction as shown in FIG. 2A, most of the etching is performed from a direction orthogonal to the extending direction (that is, a direction in which the etching rate is fast) The etching rate can be increased.

In this specification, patterning an element so as to extend in a direction orthogonal to a specific lattice direction does not necessarily mean that the entire element extends linearly in the corresponding direction, and it does not mean that the entirety of the element to be patterned is in the main extension direction, This high extension direction is orthogonal to the lattice direction. If the device is patterned so as to extend perpendicularly to the direction of the etching speed, the etching is performed from the side of the pattern to be patterned, so that the etching rate can be increased from the fast etching direction to increase the process speed.

2B shows a surface of a gallium arsenide (GaAs) substrate having a (110) crystal plane. As shown, the (110) crystal face of gallium arsenide (GaAs) exhibits a relatively fast etch rate when etched in the lattice direction, such as in the [-100] or [00-1] direction. Therefore, the etching rate can be increased by patterning the element so as to extend in the direction orthogonal to the <-100> lattice direction as shown in FIG. 2B.

On the other hand, FIG. 2C shows the surface of a gallium arsenide (GaAs) substrate having a (111) crystal plane. Since the (111) crystal planes of gallium arsenide (GaAs) have three etching planes located in the [1-10], [10-1] and [0-11] directions, .

Using the dependency of the etch rate of the gallium arsenide (GaAs) described above on the plane direction, the arrangement of the pattern to be patterned is determined in consideration of the direction in which the etching rate is high in etching the gallium arsenide (GaAs) The yield and speed of the etching process can be improved. In FIGS. 2A to 2C, the direction of the etch rate is fast along the crystal plane of gallium arsenide (GaAs). However, other III-V compounds have a similar planar direction dependence of etch rate, It has been known that it has a rapid etching rate in the direction of Therefore, the crystallization of the patterning direction by applying the above-described principle can be applied not only to gallium arsenide (GaAs) but also to other III-V compounds.

3 is a flow chart of a method of manufacturing a semiconductor device by an epitaxial lift-off (ELO) method according to an embodiment, and Figs. 4A to 9B are cross- And FIG. Hereinafter, each step of the method of manufacturing a semiconductor device according to the embodiment shown in FIG. 3 will be described with reference to cross-sectional views and plan views shown in FIGS. 4A to 9B.

4A and a corresponding plan view of FIG. 4B, a sacrificial layer 101 including a group III-V compound is formed on the first substrate 100 (S1), and a sacrificial layer 101 is formed on the sacrificial layer 101 The element layer 102 can be formed (S2). The first substrate 100 is made of a group III-V compound such as gallium arsenide (GaAs), indium phosphide (InP) or gallium nitride (GaN), and is epitaxially grown from the first substrate 100 The sacrificial layer 101 may be formed. However, this is exemplary and the first substrate 100 may be made of a different material than the Group III-V compound.

In one embodiment, an etch stop layer (not shown) may be further formed before forming the sacrificial layer 101 on the first substrate 100. The etch stop layer may be made of a material that is not dissolved in the etching process of the sacrificial layer 101 described later.

The sacrificial layer 101 is formed by joining the element layer 102 to the silicon substrate and then removing the sacrificial layer 101 to separate the first substrate 100 and the sacrificial layer 101 from the silicon substrate It is used for the purpose. For example, the sacrificial layer 101 may be a III-V compound containing a high concentration of aluminum (Al) that is easily etched into a solution such as hydrogen fluoride (HF) or hydrogen chloride (HCl) But is not limited thereto.

The element layer 102 is a layer made of a semiconductor material necessary for the construction of a semiconductor device to be manufactured through this embodiment. In one embodiment, the device layer 102 is comprised of a Group III-V compound as well as the sacrificial layer 101 and may be formed from the sacrificial layer 101 in an epitaxial manner. However, this is exemplary, and the device layer 102 may be made of a different material than the III-V compound. Also, the device layer 102 may be at least partially doped n-type or p-type.

Referring to FIG. 5A and a corresponding plan view of FIG. 5B, the sacrifice layer 101 and the device layer 102 may be patterned according to the shape of the semiconductor device to be manufactured (S3). At this time, as described above with reference to FIGS. 2A to 2C, the sacrifice layer 101 and the device layer 102 are patterned to extend in either direction along the crystal plane direction of the group III-V compound constituting the sacrifice layer 101 Is determined. That is, in order for the sacrificial layer 101 to be etched from the direction in which the group III-V compound constituting the sacrificial layer 101 exhibits a rapid etching rate, the sacrificial layer 101 may be formed in a shape extending orthogonally to the direction, (101) and the element layer (102) are patterned.

In the patterning process, the mask corresponding to the device shape to be manufactured is rotated so that the III-V compound extends orthogonally with respect to the direction in which the rapid etching rate is indicated, thereby forming the sacrifice layer 101 and the device layer 102 The photoresist previously applied on the element layer 102 is partially exposed and removed by using a mask and then exposed to the etching solution to remove the sacrifice layer 101 and the element layer 102 may be etched. The etching may be performed by a wet etching method using an etching solution based on phosphoric acid (H ₃ PO ₄ ), but is not limited thereto. After etching the photoresist and mask are removed.

Because of the patterned shape of the sacrificial layer 101, etching is performed from a direction in which the etching rate is fast, so that a high processing speed can be obtained in the etching process of the sacrifice layer 101. Further, after the etching process of the sacrifice layer 101, the device may be rotated by a certain angle as needed for a subsequent process such as coupling with other devices.

6A and 6B are a cross-sectional view and a plan view showing a form in which the sacrifice layer 101 is partially removed after patterning of the device layer 102 for comparison with a conventional ELO process, and Figs. 7A and 7B are cross- Sectional view and a plan view showing a mode in which the device layer 102 is removed for observation from the structure of FIG.

The etching of the sacrificial layer 101 may be performed using an etching solution containing hydrogen fluoride (HF) and deionized water. For example, etching of the sacrificial layer 10 can be performed by supporting the structure for 10 seconds in an etching solution mixed with hydrogen fluoride (HF) and deionized water at a volume ratio of 1: 3. The etching of the element layer 102 can be performed using citric acid as an etching solution. For example, the element layer 102 can be removed by supporting the structure in the citric acid solution for 5 seconds. However, the above-described etching solutions and processes are illustrative, and the reaction materials and conditions for the etching may differ depending on the material and thickness of the sacrifice layer 101 and / or the device layer 102 and the like.

FIG. 10 is an image of an etched surface of a sacrifice layer obtained after the structure shown in FIGS. 7A and 7B is obtained by using an ELO process according to a conventional technique, and FIG. 7A and 7B are obtained by the method of manufacturing a device, and then the etched surface of the sacrificial layer is photographed.

As shown in FIG. 10, in the conventional ELO process, the patterning direction was not specifically controlled according to the crystal plane direction of the sacrifice layer, and the etching result was that the edge of the sacrifice layer was etched inward by a length of about 2 μm.

On the other hand, as shown in FIG. 11, in the method of manufacturing a semiconductor device according to the present embodiment, the sacrifice layer is patterned so that the sacrifice layer has a shape orthogonal to the direction of 45 degrees in which the sacrifice layer is etched at a high speed. The etched length of the edge of the sacrificial layer was increased to about 5 탆 when the etching was performed under the same process conditions and time as the result of the etching. That is, it can be seen that etching is further performed for the same time, and the etching yield and speed are increased.

3, after the sacrifice layer 101 and the device layer 102 are patterned in consideration of the crystal plane direction of a group III-V compound constituting the sacrifice layer 101, a cross-sectional view of FIG. 8A and a cross- The patterned element layer 102 may be bonded to the surface of the second substrate 200 as shown in the plan view of FIG. 8B (S4). The second substrate 200 is made of silicon (Si).

In one embodiment, a process of removing the native oxide film formed on the surface of the element layer 102 and the second substrate 200 before bonding is further performed. Also, in one embodiment, activation is achieved by treatment with the plasma of the element layer 102 and / or the second substrate 200 prior to bonding.

Next, the sacrifice layer 101 is etched in a state where the element layer 102 is bonded to the second substrate 200. When the sacrifice layer 101 is completely removed by etching, 2 substrate 200 to obtain a device structure as shown in a cross-sectional view of FIG. 9A and a corresponding plan view of FIG. 9B (S5). According to the method for manufacturing a semiconductor device according to the embodiments described above, the etching is performed from a direction in which the etching rate is fast in consideration of the difference in the etching speed depending on the cystal orientation, which is a characteristic of the III-V group compound The patterning of the device and the sacrifice layer is performed. Therefore, the process yield can be improved and the process speed can be increased faster than the conventional ELO process.

While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. However, it should be understood that such modifications are within the technical scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

A method of manufacturing a semiconductor device for improving an etching rate using a crystal structure of a group III-V compound,
Forming a sacrificial layer on the first substrate, the sacrificial layer comprising a Group III-V compound having an etch rate different for each crystal plane direction;
Forming an element layer on the sacrificial layer;
Patterning the sacrificial layer and the device layer in a shape having a portion extending along a first direction determined based on a crystal plane direction of the III-V group compound of the sacrificial layer;
Bonding the patterned element layer onto a second substrate; And
And removing the sacrificial layer and the first substrate by etching the sacrificial layer using an etching solution while the element layer is bonded onto the second substrate. &Lt; / RTI &gt;
The method according to claim 1,
Wherein the first direction is a direction orthogonal to a lattice direction in which the etching rate of the III-V compound of the sacrificial layer is the fastest.
The method according to claim 1,
Wherein the step of etching the sacrificial layer comprises etching the side surface of the sacrificial layer from a second direction orthogonal to the first direction.
The method according to claim 1,
The III-V compound of the sacrificial layer has a (100) crystal face,
Wherein the first direction is a < 001 > lattice direction.
The method according to claim 1,
The III-V compound of the sacrificial layer has a (110) crystal face,
Wherein the first direction is a < -100 > lattice direction.
The method according to claim 1,
Wherein the etchant solution comprises an epitaxial lift-off comprising hydrogen fluoride (HF) and deionized water.
The method according to claim 6,
Wherein the volume ratio of hydrogen fluoride (HF) and deionized water in the etching solution is 1: 3.
The method according to claim 1,
Further comprising forming an etch stop layer on the first substrate before forming the sacrificial layer. &Lt; Desc / Clms Page number 25 &gt;
The method according to claim 1,
Wherein the first substrate comprises a group III-V compound,
Wherein the sacrificial layer is formed on the first substrate in an epitaxial growth manner.
The method according to claim 1,
Wherein the second substrate comprises silicon (Si).

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