KR101855339B1 - DC-DC converter having a device to cope with change of input voltage - Google Patents

Abstract

The present invention relates to a technology of correcting an output voltage in accordance with a change in an input voltage of a DC-DC converter. The DC-DC converter comprises: a switching-type DC voltage converting unit; a PWM waveform signal control unit for generating a PWM waveform signal provided for an operation of a switch included in the DC voltage converting unit, wherein a duty of the PWM waveform signal is determined by a feedback voltage input to the PWM waveform signal control unit; and a feedback circuit unit for generating the feedback voltage. The feedback voltage is generated by subtracting a value proportional to a DC input voltage input to the DC voltage converting unit from a value proportional to an error voltage proportional to the difference between a value of a DC output voltage output by the DC voltage converting unit and a predetermined reference voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a DC-DC converter having a device for coping with a change in an input voltage.

The present invention relates to a DC-DC converter, and relates to a technique for correcting an output voltage using a change value of an input voltage of a DC-DC converter.

In order to provide the DC voltage to be input to the AMOLED panel, it is necessary to change the level of the DC input voltage provided from the battery or a predetermined DC power supply to convert it into a DC output voltage suitable for the AMOLED panel. DC converter.

In order to provide the DC output voltage to be input to the battery cell to be charged in the wireless charging, it is necessary to change the DC input voltage supplied from the wireless charging device to a DC output voltage suitable for the battery cell. Can also be performed by a DC-DC converter.

There are many other applications where DC-DC converters are used. DC-DC converters are primarily used in portable electronic devices such as cell phones and laptop computers powered by batteries. These electronic devices often include several subcircuits, each of which has its own voltage level requirement, which is different from that provided by the battery.

For example, mobile display devices use batteries as a power source. The battery voltage gradually drops as you use the device. This causes a change in the input voltage of the DC-DC converter, that is, a line change. For example, particularly in the case of a DC-DC converter for an AMOLED, a DC-DC converter for an AMOLED panel preferably provides good line regulation characteristics because a slight fluctuation of the DC output voltage causes a flicker of the screen.

The DC-DC converter can accept a DC input voltage and provide a DC output voltage. At this time, when the DC input voltage varies, the value of the DC output voltage may not be accurately fixed to the set target value, and a value indicating a predetermined error may be generated. There is a problem that the operating characteristics of the device that receives the voltage can be changed.

In order to solve the above-described problems, the present invention provides a technique for minimizing the variation of the DC output voltage provided from the DC output terminal of the DC-DC converter according to the change of the DC input voltage. That is, a technique for improving the line regulation characteristic of the DC-DC converter is provided.

According to an aspect of the present invention, a change in DC input voltage input to a DC-DC converter having a PWM waveform signal controller is detected, and a change in the sensed DC input voltage is used for PWM control. Thus, even when the DC input voltage fluctuates, it is possible to improve the line regulation characteristic of the DC-DC converter by preventing the DC output voltage from fluctuating.

A DC-DC converter provided according to an aspect of the present invention includes: a switching type DC voltage converting unit; A PWM waveform signal control unit for generating a PWM waveform signal for controlling operation of a switch included in the DC voltage conversion unit, the duty of the PWM waveform signal being determined by a feedback voltage (V _C ) input to the PWM waveform signal control unit A PWM waveform signal controller; And a feedback circuit portion for generating an error voltage. At this time. Wherein the feedback voltage V _C is a ratio of the error voltage V _ERR which is proportional to a difference between a value V _SENSE related to the DC output voltage V _OUT and a predetermined reference voltage V _REF , (B * V _BAT ) that is proportional to the DC input voltage (V _BAT ) input to the DC voltage converting unit from a value (a * V _ERR ) proportional to the DC input voltage

Here, the feedback voltage generator may further include a feedback voltage generator for generating the feedback voltage. The feedback voltage generator may include a first current mirror, a second current mirror, and a third current mirror. And the first current mirror mirrors the error current I _ERR proportional to the error voltage to produce a duplicated error current I _ERR , and the third current mirror has an input proportional to the DC input voltage V _BAT generating a current (I _BAT) for mirroring the replicated input current (I _BAT) and the second current mirror generates a second input current replicated mirrors the duplicated input current (I _BAT) (I _BAT) And output a feedback current I _{C obtained} by subtracting the replicated second input current I _BAT from the replicated error current I _ERR . And to generate the feedback voltage (V _C ) from the feedback current (I _C ).

At this time, the feedback voltage V _C may be inversely proportional to the DC input voltage V _BAT .

At this time, the magnitude of the feedback voltage and the duty value of the PWM waveform signal may be proportional.

In this case, the first current mirror may include an eleventh PMOS transistor and a twelfth PMOS transistor. And a source terminal of the eleventh PMOS transistor and a source terminal of the twelfth PMOS transistor may be connected to a supply terminal. And a gate terminal of the eleventh PMOS transistor may be connected to a gate terminal of the twelfth PMOS transistor and a drain terminal of the eleventh PMOS transistor, respectively. And the second current mirror may include a thirteenth PMOS transistor and a fourteenth PMOS transistor. And a source terminal of the thirteenth PMOS transistor and a source terminal of the fourteenth PMOS transistor may be connected to the supply terminal. And a gate terminal of the thirteenth PMOS transistor may be connected to a gate terminal of the fourteenth PMOS transistor and a drain terminal of the fourteenth PMOS transistor, respectively. And the third current mirror may include an eleventh NMOS transistor and a twelfth NMOS transistor. And a source terminal of the 11 < th > NMOS transistor and a source terminal of the 12 < th > NMOS transistor may be connected to a first reference potential. And a gate terminal of the 11th NMOS transistor may be connected to a gate terminal of the 12th NMOS transistor and a drain terminal of the 12th NMOS transistor, respectively. The drain terminal of the 11th NMOS transistor may be connected to the drain terminal of the 12th PMOS transistor. The drain terminal of the 12 < th > NMOS transistor may be connected to the drain terminal of the 13 < th > PMOS transistor.

In this case, the DC voltage converting unit may include an inductor, a first NMOS transistor, and a first PMOS transistor. A first terminal of the inductor is connected to a drain terminal of the first NMOS transistor and a drain terminal of the first PMOS transistor, and a source of the first PMOS transistor is connected to a drain of the first PMOS transistor, Terminal may be connected to an output terminal of the DC-DC converter.

In this case, the PWM waveform signal control unit may include a gate driving unit, and may control the first NMOS transistor and the first PMOS transistor using the PWM voltage value of the gate driving unit.

At this time, the PWM waveform signal control unit may further include a current sensing unit and a slope compensation unit. The current sensing unit senses a current of a source terminal of the first NMOS transistor, and detects and outputs a peak value of the sensed current. The slope compensating unit may receive the sawtooth voltage having the predetermined period and the output value of the current sensing unit to output the compensation voltage.

In this case, the PWM waveform signal controller may further include a comparator, a latch part, and a gate driver. The comparator may receive the compensation voltage and the feedback voltage to output a logical value and the latch unit may receive the logical value and the clock signal and output the PWM voltage value to the gate driver .

At this time, the feedback circuit section may include a first resistor, a second resistor, and an error amplifier. And one terminal of the first resistor is connected to an output terminal of the DC-DC converter, and the other terminal of the first resistor and one terminal of the second resistor are commonly connected to the inverting input terminal of the error amplifier . And the other terminal of the second resistor is connected to the first reference potential, and the non-inverting input terminal of the error amplifier is connected to the second reference potential.

According to the present invention, it is possible to detect a change in the DC input voltage (ex: voltage of the battery or output voltage of the rectifier at the next stage of the wireless charging coil) input to the DC-DC converter, By using the DC-DC converter for PWM control, it is possible to improve the line regulation characteristic of the DC-DC converter, thereby improving the operation quality of the device receiving the DC output voltage of the DC-DC converter.

Therefore, by designing, for example, a converter used in a device sensitive to a change in voltage input to a device using a battery or the like according to the present invention, a product with improved line regulation characteristics can be obtained.

FIGS. 1A and 1B show an internal structure of a DC-DC converter according to a conventional example.
FIG. 2 is a graph showing the current value of the inductor 50, the voltages of the nodes N2 to N4, and the voltage of the PWM signal according to the conventional art.
FIG. 3A is a configuration diagram of a DC-DC converter 200 according to an embodiment of the present invention, and FIG. 3B is a circuit diagram of a DC-DC converter according to an embodiment of the present invention.
4 shows an internal circuit of the feedback voltage generator 60 according to an embodiment of the present invention.
5 is a diagram for explaining a difference in feedback voltage according to the magnitude of an input current according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, but may be implemented in various other forms. The terminology used herein is for the purpose of understanding the embodiments and is not intended to limit the scope of the present invention. Also, the singular forms as used below include plural forms unless the phrases expressly have the opposite meaning.

FIGS. 1A and 1B show an internal structure of a DC-DC converter according to a conventional example.

FIG. 1A is a block diagram illustrating a schematic configuration of a DC-DC converter.

The DC-DC converter 100 shown in FIG. 1A includes a DC voltage conversion unit 30, a PWM waveform signal control unit 10, and a feedback circuit unit 20 therein.

The DC voltage converting section 30 may include, for example, two transistors. The current input through the direct current voltage converter 30 may flow through the first transistor of the two transistors or may be controlled to flow through the second transistor of the two transistors when not. The two transistors can be controlled to perform a switching operation in which the on and off are periodically repeated. Also, the two transistors can be controlled so as not to be in the ON state at the same time. The second transistor may be turned off when the first transistor is on, and may be turned on when the first transistor is off. The output voltage of the DC-DC converter may vary according to the duty ratio of the switching clock of each transistor. The 'duty ratio' may be defined as a ratio between a time length of an ON interval and a time interval of an OFF interval of a switching clock provided to the gates of the first transistor or the second transistor. Alternatively, the 'duty ratio' may be defined as a time ratio between a time period during which the first transistor maintains the on state and a period during which the second transistor maintains the on state.

The first transistor and the second transistor may be, for example, NMOS transistors and PMOS transistors, respectively.

The DC input voltage V _IN of the DC-DC converter may be provided at the input terminal TI1 = IN of the DC voltage converting section 30. [ The DC voltage converting unit may be defined including the inductor 50 provided at its input terminal or may be defined excluding the inductor 50. [ The voltage value Vst of the first output terminal TO1 of the DC voltage converting unit 30 or a current value proportional to the voltage value Vst is input to the PWM waveform signal controller 10 and the DC voltage converting unit The voltage value (V _OUT ) of the second output terminal (TO2 = OUT) of the feedback circuit section (30) can be input to the input terminal (TI2) of the feedback circuit section.

The feedback circuit unit 20 receives the output voltage of the DC-DC voltage converting unit 30, that is, the output voltage of the DC-DC converter 100, and amplifies the difference value between the scaled value of the input output voltage and a predetermined reference value Thereby providing an error voltage (V _ERR ). 1A and 1B, the error voltage V _ERR is equal to the feedback voltage V _C.

The PWM waveform signal controller 10 may compare the compensation voltage generated using the values input from the DC voltage converter 30 or the like with the feedback voltage V _C to output the PWM voltage corresponding thereto, The output voltage of the DC-DC converter 100 can be compensated by providing the gate voltages of the two transistors (for example, NMOS transistor and PMOS transistor) of the DC voltage converting section 30 based on the PWM voltage.

FIG. 1B shows the internal circuit of the DC-DC converter shown in FIG. 1A.

FIG. 2 is a graph showing the current value of the inductor 50, the voltages of the nodes N2 to N4, and the voltage of the PWM signal according to the conventional art.

Hereinafter, FIG. 1B and FIG. 2 will be described together.

The DC-DC converter 100 illustrated in FIG. 1B includes a DC voltage converting unit 30, a PWM waveform signal control unit 10, and a feedback circuit unit 20 therein.

The DC voltage converting unit 30 may include an inductor 50, an NMOS transistor 31, and a PMOS transistor 32. The PWM waveform signal control unit 10 may include a current sensing unit 11, a slope compensation unit 12, a comparison unit 13, a latch 14, and a gate driving unit 15. The feedback circuit portion 20 may include a first resistor 23, a second resistor 24, a reference potential portion 22, and an error amplifier 21.

<DC voltage conversion unit>

The DC input voltage V _IN may be provided to the input terminal IN of the DC voltage converting unit 30. [ The DC input voltage V _IN may be provided, for example, from a Rectifier of the next stage of a battery or a wireless charging power providing coil of wireless charging. One terminal of the inductor 50 may be connected to the Rectifier of the next stage of the battery or the wireless charging power providing coil and the other terminal N1 of the inductor 50 may be connected to the LX terminal. The LX terminal may be connected to the drain terminal of the NMOS transistor 31 and the drain terminal of the PMOS transistor 32, respectively. The gate terminal of the NMOS transistor 31 and the gate terminal of the PMOS transistor may be respectively connected to the first terminal and the second terminal of the gate driver 15, respectively. The source terminal of the NMOS transistor 31 may be connected to one terminal of the resistor 33 and the other terminal of the resistor 33 may be connected to the reference potential GND. And the drain terminal of the PMOS transistor 32 may be connected to the output terminal OUT.

1B, the two transistors included in the DC voltage converting unit 30 are the NMOS transistor 31 and the PMOS transistor 32, respectively, but the present invention is not limited thereto.

When the DC input voltage V _IN is provided to the input terminal IN of the DC voltage conversion unit, the value of the current flowing through the inductor 50 by the switching operation of the NMOS transistor and the PMOS transistor is represented by the graph (111) &lt; / RTI &gt; The NMOS transistor and the PMOS transistor may be alternately turned on and off. A resistor 33 may be connected between the source of the NMOS transistor 31 and the reference potential. The switching operation may be provided by a separate gate driver 15.

<PWM waveform signal controller>

The current sensing unit 11 of the PWM waveform signal control unit 10 can sense the value of the current flowing through the resistor 33 and output it as a voltage. At this time, the voltage V _N2 at the node N2 may be the same as the graph 112 of FIG. 2 (b). The reason why the voltage of the node N2 drops to 0 in the interval between T1 and T3 is that the NMOS transistor is closed at the beginning of each period of Tl, T2 and T3 and the PMOS transistor is operated and the current flowing in the inductor 50 is PMOS Because it flows into the transistor. That is, since the current does not flow to the NMOS transistor in each of the sections T1, T2, and T3, the voltage falls to zero.

The current detection unit 11 is configured to detect a peak value of the current I _L flowing through the inductor 50. The time point of detection of the peak value may be provided to the slope compensating unit 12. For example, the time points at which the inductor 50 has the peak values may be t1, t2, and t3, and the values of t1, t2, and t3 may be provided to the slope compensation unit 12. [

The voltage V _N2 at the node _N2 and the sawtooth voltage V _N3 having a predetermined period may be input to the slope compensation unit 12 of the PWM waveform signal controller 10. [ The sawtooth voltage may be the same as the graph 113 of FIG.

The slope compensation unit 12 may output the compensation voltage V _N4 which is the sum of the voltage V _N2 of the node N2 and the sawtooth voltage V _N3 . However, the slope compensating unit 12 compensates for the compensations at the time t11, t12, and t13 when the sawtooth voltage V _N3 falls from the time t1, t2, t3 when the peak value is detected to the lowest value The voltage V _N4 can be forcibly controlled to be a constant value such as a reference potential value. That is, the compensation voltage V _N4 may be the same as the graph 114 of FIG. 2 (d). Oscillation of the output voltage can be prevented by using the slope compensating unit 12. [

The comparator 13 of the PWM waveform signal controller 10 outputs a logical '1' value when the compensation voltage V _N4 is greater than the feedback voltage V _C provided by the feedback circuit 20, , Or outputs a logical '0' value when the compensation voltage V _N4 is greater than the feedback voltage V _C provided by the feedback circuit section 20, and outputs a logical '0' The value of the logical '1' can be output.

The latch unit 14 of the PWM waveform signal controller 10 receives the clock signal and the value output to the comparator 13 and outputs the PWM voltage V _PWM provided to the gate driver 15 . The period of the clock signal has a predetermined value, and the period of the sawtooth voltage and the period of the inductor current may be the same as the period of the clock signal.

The gate drive unit 15 of the PWM waveform signal controller 10 receives the PWM voltage V _PWM and provides the gate voltages of the NMOS transistor 31 and the PMOS transistor 32 based on the received PWM voltage V _PWM .

<Feedback circuit part>

The first resistor 23 and the second resistor 24 of the feedback circuit section 20 may form a voltage divider.

One end of the first resistor R1 23 is connected to the DC output terminal OUT of the DC voltage converting part 30 and the other end of the first resistor Rl 23 is connected to the second resistor R2 24 To the other end. The other end of the second resistor (R2) (24) may be connected to the reference potential.

The sense voltage V _SENSE which is the voltage at the node Nsense defined between the first resistor R1 23 and the second resistor R2 24 and the sense potential V _SENSE provided from the reference potential section 22, (V _REF ) can be amplified by the error amplifier 21.

At this time, the sense voltage V _SENSE may be a value scaled from the DC output voltage, for example, using the voltage divider. For example, the reference potential (V _REF ) may be set to the same value as the sense voltage that occurs when the DC output voltage has a predetermined preferable value. For example, if the predetermined preset value is 4.6V and the circuit is configured so that the sensing voltage is 2.3V, the reference potential may be set to 2.3V.

In this case, the voltage amplified by the error amplifier 21 is the error voltage V _ERR . In the example of FIG. 1B, the error voltage V _ERR is the feedback voltage V _C ).

FIG. 3A is a configuration diagram of a DC-DC converter 200 according to an embodiment of the present invention, and FIG. 3B is a circuit diagram of a DC-DC converter according to an embodiment of the present invention.

The basic internal configuration of the DC-DC converter of FIG. 3A can be the same as the configuration of FIG. 1B as the DC voltage converting unit 30, the PWM waveform signal controlling unit 10, and the feedback circuit unit 20.

3A differs from FIG. 1A in that a feedback voltage generator 60 is added between the output terminal of the feedback circuit 20 and the input terminal of the PWM waveform signal controller 10. Therefore, in FIG. 1B, if the feedback voltage V _C and the error voltage V _ERR have the same value, the feedback voltage V _C and the error voltage V _{ERR in} FIG. Can be different values.

That is, the feedback voltage generating unit 60 detects the input voltage V _IN input to the DC voltage converting unit 30 and outputs the feedback voltage V _C (V) using the sensed input voltage and the error voltage V _ERR ). The feedback voltage V _C is obtained by amplifying a difference between a value V _SENSE obtained by scaling the DC output voltage V _OUT output from the DC voltage converter 30 and a predetermined reference voltage V _REF (B * V _IN = b *) proportional to the DC input voltage (V _BAT = Vi _IN ) input to the DC voltage converter 30 from a value (a * V _ERR ) proportional to the error voltage V _ERR , V _BAT ).

According to embodiments of the present invention, it is possible to reduce the variation of the error voltage (V _ERR ) used to obtain the necessary feedback voltage. That is, the small change in the error voltage V _ERR means that the difference between the output voltage V _OUT and the initially set desired value is small. Therefore, a constant output voltage (V _OUT ) closer to the preset output voltage can be obtained despite the change of the input voltage (V _IN ).

4 shows an internal circuit of the feedback voltage generator 60 according to an embodiment of the present invention.

The feedback voltage generator 60 may include a first current mirror 61, a second current mirror 62, and a third current mirror 63.

When the error voltage V _ERR is input to the feedback voltage generator 60, the first current mirror 61 mirrors the error current I _ERR 611 proportional to the error voltage V _ERR , An error current I _ERR 612 can be generated.

The first current mirror 61 may include two PMOS transistors. The source terminal of the eleventh PMOS transistor PM1 and the source terminal of the twelfth PMOS transistor PM2 may be connected to the supply voltage VDD, respectively. The gate terminal of the eleventh PMOS transistor PM1 may be connected to the gate terminal of the twelfth PMOS transistor PM2 and the gate terminal of the eleventh PMOS transistor PM1 may be connected to the drain terminal of the eleventh PMOS transistor PM1.

The drain terminal of the eleventh PMOS transistor PM1 may be connected to the drain terminal of the NMOS transistor NM0 and the error voltage V _ERR may be input to the gate terminal of the NMOS transistor NM0. One end of a resistor may be connected to the source terminal of the NMOS transistor NM0 and a reference potential GND may be connected to the other end of the resistor.

When the input voltage V _BAT = V _IN is input to the gate terminal of the thirteenth NMOS transistor NM3, the input current I _BAT can flow through the drain terminal of the thirteenth NMOS transistor NM3. At this time, one end of the resistor is connected to the source terminal of the thirteenth NMOS transistor NM3, and a reference potential (GND) is connected to the other end of the resistor. The input voltage V _BAT may flow through the third current mirror 63 in the same manner.

The third current mirror 63 may mirror the input current I _BAT 631 proportional to the DC input voltage V _BAT to produce a duplicated input current I _BAT 632.

The third current mirror 63 may include two PMOS transistors. The source terminal of the thirteenth PMOS transistor PM3 and the source terminal of the fourteenth PMOS transistor PM4 may be connected to the supply voltage VDD, respectively. The gate terminal of the thirteenth PMOS transistor PM3 may be connected to the gate terminal of the fourteenth PMOS transistor PM4 and the gate terminal of the thirteenth PMOS transistor PM3 may be connected to the drain terminal of the fourteenth PMOS transistor PM4.

The replicated input current I _BAT 632 may flow to the second current mirror 62. The second current mirror 62 may mirror the replicated input current I _BAT 632 621 to produce a duplicated second input current I _BAT 622.

The second current mirror 62 may include two NMOS transistors. The source terminal of the eleventh NMOS transistor NM1 and the source terminal of the twelfth NMOS transistor NM2 may be connected to the reference potential GND, respectively. The gate terminal of the eleventh NMOS transistor NM1 may be connected to the gate terminal of the twelfth NMOS transistor NM2 and may also be connected to the drain terminal of the twelfth NMOS transistor NM2.

As a result, the feedback voltage generator 60 outputs the feedback current Ic obtained by subtracting the replicated second input current I _BAT 622 from the replicated error current I _ERR 612 , And can generate the feedback voltage (V _C ) from the feedback current (Ic).

That is, the feedback voltage V _C can be proportional to a value (a * V _ERR ) proportional to the error voltage V _ERR minus a value (b * V _BAT ) proportional to the input voltage V _BAT (V _C ? (A * V _ERR -b * V _BAT )).

5 is a diagram for explaining a difference in feedback voltage according to the magnitude of an input voltage according to an embodiment of the present invention.

FIG. 5 (a) compares patterns of change in inductor current when input voltages of different sizes are applied. 5B is a _graph comparing the magnitudes of the signals of the feedback voltage V _C and the error voltage V _ERR when the input voltages of the different sizes are inputted with time. FIG. 5C shows a signal of the _PWM voltage V _PWM according to the respective feedback voltages V _{C with} time.

In FIG. 5A, for example, if the change in the inductor current when the input voltage of the first level is input shows a graph according to the reference numeral 211, the input voltage of the second level having a level higher than the first level The change in inductor current may follow the graph according to reference numeral 212. &lt; RTI ID = 0.0 &gt;

At this time, when the input voltage of the first level is applied, the magnitude of the error voltage (V _ERR ) 215 output from the feedback circuit unit 20 is larger than the magnitude of the input voltage of the second level May be greater than the error voltage (V _ERR ) 216 output from the feedback circuit section 20.

The present invention is to maintain the value of the feedback voltage (V _C ) as it is in the prior art (i.e., to adjust the duty ratio of the PWM conventionally), but further to improve the line regulation by sensing the change of the input voltage. This will be described with reference to this.

3B, the magnitude of the error voltage (V _ERR ) 215 generated when the first input voltage is input corresponds to the magnitude of the error voltage V _ERR generated when the second input voltage is input (V _ERR ) &lt; RTI ID = 0.0 &gt; 216 &lt; / RTI &gt; When the error voltage V _ERR 215 is input to the feedback voltage generator 60, the feedback voltage V _c 213 may be output. When the error voltage V _ERR 216 is input to the feedback voltage generator 60, the feedback voltage V _c 214 may be output. 2, since the error voltage is equal to the feedback voltage, the change value of the error voltage according to the different input voltage is equal to the change value of the feedback voltage according to the different input voltage Do. 5, according to an embodiment of the present invention, a change value of an error voltage according to different input voltages (for example, a difference value between an error voltage 215 and an error voltage 216) It can be seen that the change value of the feedback voltage according to the input voltage (e.g., the feedback voltage 213 is smaller than the difference value of the feedback voltage 214).

The present invention, an error voltage (V _ERR) to in generating a feedback voltage (V _C) in the present invention in requiring the same feedback voltage (V _C) and the feedback voltage (V _C) obtained in the above-described comparison techniques situation error voltage at the input, so the voltage used to compensate for changes in (V _iN), throwing an identical feedback voltage (V _C) value of the prior art the difference (input voltage of the error voltage (V _ERR) differ from each other (V _ERR )) can be reduced. That is, decreasing the difference value of the error voltage (V _ERR ) means that the line regulation is improved.

That is, conventionally, if the feedback voltage V _C and the error voltage V _ERR have the same value, the feedback voltage V _C and the error voltage V _ERR are different values (for example, V _C = k 1 * V _ERR + k2 * V _IN ). Where k1 and k2 may be real numbers.

The above-mentioned error voltage (V _ERR ) is a value reflecting the DC Variation of the output voltage. Therefore, in order to reduce the DC variation of the output voltage, a method of reducing the change of the error voltage (V _ERR ) must be found. In the prior art, the duty ratio has to be adjusted by using the error voltage (V _ERR ). In the present invention, the change of the error voltage (V _ERR ) under the same condition can be reduced by adopting a configuration for sensing and compensating for a change in the input voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the essential characteristics thereof. The contents of each claim in the claims may be combined with other claims without departing from the scope of the claims.

Claims (11)

A switching type DC voltage converting unit 30;
A PWM waveform signal control unit (10) for generating a PWM waveform signal for controlling operation of a switch included in the DC voltage conversion unit, wherein the duty of the PWM waveform signal is a feedback voltage (V _C ) input to the PWM waveform signal control unit A PWM waveform signal controller; And
A feedback circuit section (20) for generating an error voltage;
/ RTI &gt;
Wherein the feedback voltage V _C is a ratio of the error voltage V _ERR which is proportional to a difference between a value V _SENSE related to the DC output voltage V _OUT and a predetermined reference voltage V _REF , (B * V _BAT ) proportional to the DC input voltage (V _BAT ) input to the DC voltage converting unit from a value (a * V _ERR ) proportional to the DC input voltage
DC-DC converter. The method according to claim 1,
Further comprising a feedback voltage generator (60) for generating the feedback voltage,
The feedback voltage generating unit 60 includes a first current mirror 61, a second current mirror 62, and a third current mirror 63,
The first current mirror 61 mirrors the error current I _ERR 611 proportional to the error voltage to generate a duplicated error current I _ERR 612,
The third current mirror 63 mirrors the input current I _BAT 631 proportional to the DC input voltage V _BAT to generate a replicated input current I _BAT 632,
The second current mirror 62 mirrors the replicated input current I _BAT 632 and 621 to produce a duplicated second input current I _BAT 622,
And outputs the feedback current I _{C obtained} by subtracting the replicated second input current I _BAT 622 from the replicated error current I _ERR 612,
And to generate the feedback voltage (V _C ) from the feedback current (I _C )
DC-DC converter. 2. The DC-DC converter of claim 1, wherein the feedback voltage (V _C ) is inversely proportional to the DC input voltage (V _BAT ). The DC-DC converter according to claim 1, wherein a magnitude of the feedback voltage is proportional to a duty value of the PWM waveform signal. 3. The method of claim 2,
The first current mirror 61 includes an eleventh PMOS transistor and a twelfth PMOS transistor,
A source terminal of the eleventh PMOS transistor and a source terminal of the twelfth PMOS transistor are connected to a supply terminal,
A gate terminal of the eleventh PMOS transistor is connected to a gate terminal of the twelfth PMOS transistor and a drain terminal of the eleventh PMOS transistor,
The second current mirror 62 includes a thirteenth PMOS transistor and a fourteenth PMOS transistor,
A source terminal of the thirteenth PMOS transistor and a source terminal of the fourteenth PMOS transistor are connected to the supply terminal,
A gate terminal of the thirteenth PMOS transistor is connected to a gate terminal of the fourteenth PMOS transistor and a drain terminal of the fourteenth PMOS transistor,
The third current mirror 63 includes an eleventh NMOS transistor and a twelfth NMOS transistor,
A source terminal of the 11th NMOS transistor and a source terminal of the 12th NMOS transistor are connected to a first reference potential,
A gate terminal of the 11th NMOS transistor is connected to a gate terminal of the 12th NMOS transistor and a drain terminal of the 12th NMOS transistor,
A drain terminal of the 12th NMOS transistor is connected to a drain terminal of the 12th PMOS transistor, and a drain terminal of the 12th NMOS transistor is connected to a drain terminal of the 13th PMOS transistor.
DC-DC converter. The method according to claim 1,
The DC voltage converting unit (30)
An inductor 50, a first NMOS transistor 31, and a first PMOS transistor 32,
One terminal of the inductor 50 is connected to the input terminal of the DC-DC converter, and the other terminal of the inductor is connected to the drain terminal of the first NMOS transistor 31 and the drain terminal of the first PMOS transistor 32 And a source terminal of the first PMOS transistor (32) is connected to an output terminal of the DC-DC converter.
DC-DC converter. The method according to claim 6,
The PWM waveform signal controller 10 includes a gate driver 15,
The first PMOS transistor 32 and the first NMOS transistor 31 are controlled using the PWM voltage value of the gate driver.
DC-DC converter. 8. The method of claim 7,
The PWM waveform signal control unit further includes a current sensing unit 11 and a tilt compensation unit 12,
The current sensing unit senses a current of a source terminal of the first NMOS transistor 31 and detects and outputs a peak value of the sensed current.
Wherein the slope compensation unit is configured to receive a sawtooth voltage having an output value of the current sensing unit and a predetermined period to output a compensation voltage,
DC-DC converter. 9. The method of claim 8,
The PWM waveform signal control unit further includes a comparison unit 13, a latch unit 14, and a gate driver 15,
Wherein the comparator receives the compensation voltage and the feedback voltage to output a logical value,
Wherein the latch unit receives the logical value and the clock signal and outputs the PWM voltage value to the gate driver,
DC-DC converter. The method according to claim 1,
Wherein the feedback circuit portion includes a first resistor, a second resistor, and an error amplifier,
One terminal of the first resistor is connected to an output terminal of the DC-DC converter, one terminal of the first resistor and one terminal of the second resistor are commonly connected to the inverting input terminal of the error amplifier,
The other terminal of the second resistor is connected to the first reference potential,
Inverting input terminal of the error amplifier is connected to a second reference potential,
DC-DC converter. A switching type DC voltage converting unit 30;
A PWM waveform signal control unit (10) for generating a PWM waveform signal for controlling operation of a switch included in the DC voltage conversion unit, wherein the duty of the PWM waveform signal is a feedback voltage (V _C ) input to the PWM waveform signal control unit A PWM waveform signal controller; And
A feedback circuit section (20) for generating an error voltage;
/ RTI &gt;
The error voltage is proportional to a difference between a value V _SENSE proportional to the DC output voltage V _OUT output from the DC voltage converter and a predetermined reference voltage V _REF ,
The feedback voltage V _C is a value (b * V) proportional to the DC input voltage V _BAT input to the DC voltage converter from a value (a * V _ERR ) proportional to the error voltage V _ERR , _BAT ). &_{Lt; / RTI} &gt;
DC-DC converter.

Images