KR101851604B1 - Wafer and method for manufacturing the same - Google Patents

Abstract

In an embodiment, the A mode defect, the B mode defect, the C mode defect, and the C + mode defect are each less than 1% in the time Zero Dielectric Breakdown (TZDB) evaluation, Mode is 4 Mega volts / cm, the B mode defect has a TZDB value of 4 to 8 Mega volt / cm, the C mode defect has a TZDB value of 8 to 10 Mega volt / cm, Lt; / RTI > to 10-12 Mega volts / cm.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer and a manufacturing method thereof, and more particularly to improvement of TZDB characteristics of a wafer.

The silicon wafer includes a single crystal growth step for forming a single crystal ingot, a slicing step for obtaining a thin disk-shaped wafer by slicing the single crystal ingot, a polishing step for mirror-polishing the wafer, The wafer is polished and a cleaning process is performed to remove the abrasive and foreign substances adhered to the wafer, and the wafer is used as a substrate of a semiconductor device.

The growth conditions of the single crystal ingot during the single crystal growth process determine the crystal quality and the crystal defect region of the single crystal silicon. That is, according to the growth conditions of the single crystal ingot, a v-rich region having defects in which supersaturated vacancies predominate and a vacancy type point defect dominates, an O band (Oxidation- Induced Stacking Fault) in which an oxidized organic stacking fault (OSF) induced defect band region, a VDP region that is dominated by a bacillary point defect but has no aggregated defect, an IDP region that is dominated by an interstitial point defect but does not have a coherent defect, and an interstitial silicon that is predominantly dominated by an interstitial point defect An LDP region having aggregated defects, and the like.

The crystal defect region of the single crystal silicon can be distinguished by the Cu-haze method or the like which contaminates the surface of the single crystal silicon with a copper (Cu) contaminated solution and utilizes the haze phenomenon of copper.

Then, when heat treatment is performed on the wafer grown by the above-described process, supersaturated oxygen in the silicon wafer precipitates as oxygen precipitates. Such oxygen precipitates are referred to as BMD (Bulk Micro Defect). If BMD occurs in a device active region in a wafer, it will adversely affect device characteristics such as junction leakage, but if BMD is present in a bulk other than the device active region, capturing metal impurities incorporated into the device process It can act as a turling site.

Therefore, it is necessary to form a BMD in the bulk of the wafer in the wafer manufacturing process, and maintain a denuded zone (hereinafter referred to as a DZ layer) in which the BMD and the like are not present near the surface of the device.

For this, BMD does not occur inside the wafer manufacturing process. However, by performing the heat treatment of the device process and the like, the DZ layer having no BMD is maintained in the vicinity of the wafer surface, which is the device active region, As a method of manufacturing a silicon wafer designed to have a gettering capability by forming a BMD in a bulk, a silicon wafer can be subjected to a rapid thermal process (RTP).

FIG. 1B is a view showing a time zero dielectric breakdown (TZDB) in the case where the rapid thermal annealing is not carried out, FIG. 1C is a cross-sectional view showing a state after the rapid thermal annealing TZDB.

In FIG. 1A, an O band region, an IDP (Interstitial Dominant Point defect zone), and a VDP (Vacancy Dominant Point defect zone) region of the wafer are shown.

1B shows a good TZDB characteristic on the surface of the wafer in the state where the rapid thermal annealing is not performed. The C mode and the B mode are shown on the surface of the wafer after the rapid thermal annealing is performed in FIG. 1C, and the A mode defect is also observed in some areas.

Here, the A mode has a TZDB value of 0 to 4 Mega volt / cm, the B mode has a TZDB value of 4 to 8 Mega volt / cm, the C mode has a TZDB value of 8 to 10 ega volt / cm, The TZDB value may be in the range of 10 to 12 Mega Volt / cm and the steady state Pass may be in the region of 12 Mega Volt / cm or more.

The embodiment attempts to prevent deterioration of TZDB in a rapid thermal annealed wafer.

In an embodiment, the A mode defect, the B mode defect C mode defect and the C + mode defect are each less than 1% in the time Zero Dielectric Breakdown (TZDB) evaluation, wherein the A mode defect has a TZDB value of 0 to 4 Mode defect, the TZDB value is between 4 and 8 Mega volts / cm, the C mode defect is the TZDB value between 8 and 10 Mega volts / cm, and the C + 10 to 12 Mega volt / cm.

The wafer may be removed after a rapid thermal process and may be removed by a thickness of, for example, 5 micrometers to 7 micrometers.

The wafer may have an interstitial dominant point defect zone (IDP) in the plane direction of 40% or more of the total diameter.

The wafer may have an IDP region and a VDP (Vacancy Dominant Point defect zone) region.

Another embodiment is a method of manufacturing a semiconductor device, comprising: preparing a wafer of silicon single crystal; Performing a rapid thermal process on the wafer; And removing the surface of the rapid thermal annealed wafer from 5 micrometers to 7 micrometers.

The rapid thermal annealing may be performed in a nitrogen atmosphere, an argon atmosphere, an ammonia atmosphere, or a mixed atmosphere thereof.

The wafer according to the embodiment and the manufacturing method thereof can be removed by a thickness of 5 to 7 micrometers, for example, 5.5 micrometers from the surface in the bulk direction after the rapid heat treatment of the polycide wafer. In addition, the wafer manufactured by this method can exhibit improved TZDB characteristics as described above. Further, it can be seen that the TZDB characteristics are improved when the width of the IDP region on the surface is 40% or more of the entire width of the wafers.

FIG. 1A is a view showing a crystal region divided by a Cu haze characteristic of a wafer,
FIG. 1B is a view showing the TZDB in the case where the rapid thermal annealing is not performed,
1C is a view showing the TZDB after the rapid thermal annealing process,
2 is a diagram showing the density or size of nanoballs from the surface of the wafer to the bulk region,
FIGS. 3A to 3E are diagrams showing crystal regions according to Cu haze characteristics of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2,
4A to 4E show TZDB characteristics after removing the surface of the wafer of 4 micrometers in Comparative Examples 1 to 3 and Examples 1 and 2,
Figs. 5A to 5E show TZDB characteristics after the surface of the wafer of Comparative Examples 1 to 3 and Examples 1 and 2 was removed by 5.5 micrometers,
6A to 6C show TZDB characteristics after removing the surface of the wafer of 7 micrometers in Comparative Examples 1 to 2 and Example 1,
7A to 7E are graphs showing TZDB characteristics according to the removal amounts of the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2. FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention.

However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the embodiment according to the present invention, in the case of being described as being formed on the "upper" or "on or under" of each element, on or under includes both elements being directly contacted with each other or one or more other elements being indirectly formed between the two elements.

Also, when expressed as "on" or "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

It is also to be understood that the terms "first" and "second", "upper" and "lower", etc., as used below, do not necessarily imply or imply any physical or logical relationship or order between such entities or elements And may be used only to distinguish one entity or element from another entity or element.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

In the method of manufacturing a wafer according to the embodiment, a silicon single crystal polished wafer is prepared and the wafer is subjected to a rapid thermal process, and then the surface of the rapidly heat-treated wafer is removed by 5 to 7 micrometers. In the silicon single crystal wafer manufactured by the above-described process, A mode defects, B mode defects, C mode defects, and C + mode defects can each be measured at less than 1% in TZDB (Time Zero Dielectric Breakdown) evaluation, . ≪ / RTI >

2 is a diagram showing the density or size of nanoballs from the surface of the wafer to the bulk region. The vertical axis represents the depth from the surface of the wafer to the bulk, and the horizontal axis represents the density or size of the nano void.

The ratio of the pulling rate V (mm / min) of the single crystal to the average value G (캜 / mm) of the temperature gradient in the single crystal in the pulling axis direction of the single crystal in the step of growing the silicon single crystal ingot by the CZ method, The vacancy can be determined on the surface of the wafer and in the bulk region according to G. [ In FIG. 2, the initial bacillus concentration by V / G is shown as a dotted line in the vertical axis direction.

Nanoballs are voids with a diameter on the order of a few nanometers and can occur in the rapid thermal processing of wafers, and the frequency of occurrences may vary from wafer to wafer. That is, the vacancies are different for each crystal region of the wafer before the rapid thermal annealing, and thus the nanoballs generated after the rapid thermal annealing of the wafer may be different for each crystal region.

In FIG. 2, the concentration of vacancies gradually decreases from the surface of the wafer to the bulk in the bulk direction, and is almost constant within a certain thickness. The size of the nano voids gradually decreases from the surface of the wafer to the bulk in the bulk direction, and is substantially constant within a certain thickness.

The arrangement of the nanoballs shown in FIG. 2 is difficult to be confirmed by naked eyes or other methods, and can be confirmed through TZDB after rapid thermal annealing of the wafer.

First, prepare a polished wafer. Polished wafers can be prepared by slicing, grinding, lapping and mirror polishing processes of monocrystalline ingots grown by the CZ method.

Then, the wafer can be rapidly heat-treated. The rapid thermal annealing may be performed in a nitrogen atmosphere, an argon atmosphere, an ammonia atmosphere, or a mixed atmosphere thereof. In the rapid thermal annealing, the wafer is rapidly heated, held at a temperature of about 1200 占 폚 for several tens of seconds, and then rapidly cooled again.

In rapid thermal processing, for example, the implantation of nanoballs from the wafer surface can occur during high temperature maintenance at 1200 DEG C in a nitrogen atmosphere, and the nanoballs may be larger in size or density at the surface than the bulk region of the wafer.

Then, the surface of the wafer can be removed at a certain depth and the TZDB can be measured. Table 1 shows the results of measuring the TZDB of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2 after removing the surface by 4 micrometers after the rapid thermal annealing process.

3A to 3E are sectional views of crystal regions according to the Cu haze characteristics of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2, and Figs. 4A to 4E are sectional views of Comparative Examples 1 to 3 and Example 1 2 shows the TZDB characteristics after removing the surface of the wafer by 4 micrometers.

IDP area width (mm) object
TZDB (ratio by mode,%) A mode B mode C mode C + mode yield 37.5 Comparative Example 1 0.56 2.25 23.41 18.91 54.87 45 Comparative Example 2 0 27.72 30.34 14.04 27.9 52.5 Comparative Example 3 1.12 30.15 45.88 14.42 8.43 132 Example 1 0.6 0.2 0.7 3.9 94.6 67.5 Example 2 0.56 0.56 3.56 5.43 89.89

In comparative examples and embodiments, a 300 mm diameter wafer was used, and the width of the IDP region means the width of the IDP region in the radius region. For example, in the case of the wafer of Example 2, the width of the IDP region is 132 millimeters in the radial region of 150 millimeters. Other than the IDP region, a VDP (Vacancy Dominant Point Defect Zone) region or an O-band (Oxidation-Induced Defective Band) region may exist.

The A mode has a TZDB value of less than 0 to 4 Mega volt / cm, the B mode has a TZDB value of less than 4 to 8 Mega volt / cm, the C mode has a TZDB value of less than 8 to 10 ega volt / cm, The C + mode may be a region where the TZDB value is less than 10-12 Mega Volt / cm.

In the wafers of Comparative Examples 1 to 3, the width of the IDP region may be less than 40% of the width of the wafer, and the sum of the A mode, the B mode, the C mode, and the C + mode TZDB value of less than 12 Mega Volt / cm Are 45.13%, 72.1% and 91.57%, respectively. The wafers of Examples 1 and 2 are 5.4% and 10.11% in the sum of the A mode, the B mode, the C mode, and the C + mode TZDB value less than 12 Mega Volt / cm. Thus, the wafers of Comparative Examples 1 to 3 had yields of 54.87% and 27.9% and 8.43%, respectively, and the yields of the wafers of Examples 1 and 2 were 94.6% and 89.89%, respectively.

As described above with reference to FIG. 2, if the removal amount of the wafer surface is increased, the region where the TZDB value of the A mode, the B mode, the C mode, and the C + mode is less than 12 Mega Volt / cm may decrease , And the surface of the wafer was further removed by 1.5 micrometers.

Table 2 shows the results of measuring the TZDB of wafers having a total removal amount of 5.5 micrometers by further removing the surface of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2 by 1.5 micrometers.

5A to 5E show the TZDB characteristics of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2 according to Table 2 and TZDB characteristics after removing the surface of the wafer by 5.5 micrometers.

IDP area width (mm) object
TZDB (ratio by mode,%) A mode B mode C mode C + mode yield 37.5 Comparative Example 1 0.37 1.69 19.1 16.67 62.17 45 Comparative Example 2 94 2.06 24.72 23.6 48.69 52.5 Comparative Example 3 0.4 0.6 11.2 24.7 63.1 132 Example 1 0.19 0 0.19 1.5 98.13 67.5 Example 2 0.4 0.2 0.0 1.5 99.3

As described above, the wafers of Comparative Examples 1 to 3 may have a width of the IDP region of less than 40% of the width of the wafer and a TZDB value of A mode, B mode, C mode, and C + mode of 12 Mega Volt / cm , Respectively, were 37.83%, 51.31% and 36.9%, respectively. The wafers of Embodiments 1 and 2 are 1.87% and 0.7% in the sum of the A mode, the B mode, the C mode, and the C + mode TZDB value less than 12 Mega Volt / cm. Therefore, the wafers of Comparative Examples 1 to 3 had yields of 62.17%, 48.69 and 63.1%, respectively, and the yields of the wafers of Examples 1 and 2 were 98.13% and 99.3%, respectively.

Increasing the removal amount of the wafer surface from Tables 1 and 2 may reduce the area of A mode, B mode, C mode, and C + mode TZDB value less than 12 Mega Volt / cm, The surface of the wafer was removed by 1.5 micrometers.

6A to 6C show the TZDB characteristics of the wafers of Comparative Examples 1 to 2 and Example 1, and are the results of measuring the TZDB of wafers having a total removal amount of 7 micrometers.

6A to 6C, the TZDB characteristics when the removal amount of the surface of the wafer is 7 micrometers are almost the same as the cases where the removal amount of the surface of the wafer in Table 2 and FIGS. 5A to 5E is 5.5 micrometers and the TZDB characteristics are not substantially different .

From Table 1 and Table 2, when the wafer with an IDP area of 40% or more is removed from the surface in the bulk direction by 5.5 micrometers, a yield of 98% or more can be confirmed as a result of TZDB measurement. A mode of less than 1% was also measured for the wafers of Examples 1 and 2, but this may be due to noise occurring during pretreatment for TZDB evaluation. Such noise may be due to defects in the wafering process, particle addition, or contamination / measurement equipment failure.

Thus, in the method of manufacturing a wafer according to the embodiment, the polished wafer can be removed from the surface in the bulk direction by a thickness of 5 to 7 micrometers, for example, 5.5 micrometers after rapid thermal processing. In addition, the wafer manufactured by this method can exhibit improved TZDB characteristics as described above. Further, it can be seen that the TZDB characteristics are improved when the width of the IDP region on the surface is 40% or more of the entire width of the wafers.

7A to 7E are graphs showing TZDB characteristics according to the removal amounts of the surfaces of the wafers of Comparative Examples 1 to 3 and Examples 1 and 2. FIG. The wafers of Comparative Examples 1 to 2 and 7 of FIGS. 7A, 7B, and 7D show data obtained by removing the surfaces by 4 micrometers, 5.5 micrometers, and 7 micrometers, respectively, 3 and the wafer of Example 2 show data obtained by removing the surfaces by 4 micrometers and 5.5 micrometers, respectively.

The TZDB characteristics of the wafers of Comparative Examples 1 to 3 were not significantly improved even when the removal amount was increased in the bulk direction from the surface. The wafers of Examples 1 and 2 were measured to have a C + mode of less than 1%, which is a region where the TZDB value was less than 12 Mega Volt / cm when the removal amount in the bulk direction from the surface was 5.5 micrometers or more. In the case of the first embodiment.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

Claims (11)

delete delete delete delete delete Growing a silicon single crystal by a Czochralski method to prepare a wafer of silicon single crystal;
Rapidly heating the wafer, heating the wafer at a temperature of about 1200 占 폚 for several tens of seconds, rapidly cooling the wafer, and performing a rapid thermal process; And
Removing the surface of the rapid thermal annealed wafer from 5 micrometers to 7 micrometers,
During heating of the wafer, nanoballs are implanted into the surface of the wafer,
Wherein the size and the concentration of the nanovoid gradually decrease from a surface of the wafer to a bulk in a bulk direction and are constant within the predetermined thickness. The method according to claim 6,
Wherein the rapid thermal annealing is performed in a nitrogen atmosphere, an argon atmosphere, an ammonia atmosphere, or a mixed atmosphere thereof. The method according to claim 6,
Wherein the wafer has a surface direction diameter of an interstitial dominant point defect zone (IDP) of 40% or more of the total diameter. The method according to claim 6,
Wherein the wafer has a mixture of an IDP region and a vacancy dominant point defect zone (VDP) region. The method according to claim 6,
Further comprising: evaluating the wafer for Time Zero Dielectric Breakdown (TZDB). 11. The method of claim 10,
Wherein the A mode defect, the B mode defect, the C mode defect and the C + mode defect of the wafer are each less than 1%, wherein the A mode defect has the TZDB value of 0 to 4 Mega volt / cm, Mode defect has a TZDB value of 4 to 8 Mega volt / cm, the C mode defect has a TZDB value of 8 to 10 Mega volt / cm, and the C + mode has a TZDB value of 10 to 12 Mega volt / Gt;

Images