KR101837099B1 - Reconfigurable error correction code device - Google Patents

Abstract

According to the error-correcting encoder of the variable structure of the present invention, the structure driven according to the noise environment can be different, and the number of syndrome generators driven according to the noise size can be varied. In addition, The number of generating units may be different and the number of error evaluating polynomial generating units driven according to the noise size may be different and the amount of power consumed for error correction may be different depending on the noise size.
According to a first aspect of the present invention, there is provided an error-correcting encoder of a variable structure, comprising: a main controller for outputting a selection control signal corresponding to the number of error correction bits; An encoder controlled by the selection control signal and outputting a code word composed of a data bit and a parity bit by multiplying an input data bit by a generator matrix; A syndrome generator which is controlled by the selection control signal and receives a codeword received from the storage unit and outputs a syndrome value; A key assignment solver controlled by the selection control signal and generating an error position detection coefficient for detecting an error position using the syndrome value; An error position detection unit controlled by the selection control signal and outputting an error position detection signal using the error position detection coefficient; And an error correction unit that is controlled by the selection control signal and corrects an error at a corresponding position using the error position detection signal.

Description

RECONFIGURABLE ERROR CORRECTION CODE DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction encoder, and more particularly, to an error correction encoder capable of selectively changing the number of error correction bits.

In the transmission of digital codes, errors may occur in the transmitted data due to external influences (noise on the transmission path, dropout, fading, etc.). Since the transmission system can not request retransmission of data when an error occurs, the receiving side must be able to detect and correct errors in the received information. In this way, correcting the reception information at the reception side is referred to as FEC (Forward Error Correction).

Cyclic codes, Both-Chaudhuri-Hocquenghem (BCH) codes, and Reed-Solomon codes are used to perform the error correction.

Here, the decoding order of the BCH code is as follows.

First, a syndrome value is obtained using a received signal, and an error location polynomial and an error evaluation polynomial are calculated using the syndrome value. The position of the error is determined by substituting the element of the Galois field into the error location polynomial, and the error of the position is corrected.

However, the decoder of the BCH code according to the related art has decoders for correcting error bits of various sizes such as 2-bit error correction, 4-bit error correction, and 8-bit error correction. Therefore, these decoders always decode the same size bits even if they are placed in different environments, so that they are unnecessarily consuming a lot of power when they are designed larger than necessary. Or, if you are in an environment with more noise than the designed level, you are more likely to encounter errors.

The present invention provides a variable-structure error-correcting encoder capable of different structures driven according to a noise environment.

Also, the present invention provides a variable-structure error-correcting encoder capable of changing the number of syndrome generators driven according to the noise size.

In addition, the present invention provides a variable-structure error-correcting encoder capable of changing the number of error locator polynomial generating units driven according to a noise size.

Also, the present invention provides a variable-structure error-correcting encoder capable of changing the number of error evaluation polynomial generation units driven according to a noise size.

Also, the present invention provides a variable-structure error-correcting encoder capable of varying the amount of power consumed for error correction according to the noise size.

According to a first aspect of the present invention, there is provided an error-correcting encoder of a variable structure, comprising: a main controller for outputting a selection control signal corresponding to the number of error correction bits; An encoder controlled by the selection control signal and outputting a code word composed of a data bit and a parity bit by multiplying an input data bit by a generator matrix; A syndrome generator which is controlled by the selection control signal and receives a codeword received from the storage unit and outputs a syndrome value; A key assignment solver controlled by the selection control signal and generating an error position detection coefficient for detecting an error position using the syndrome value; An error position detection unit controlled by the selection control signal and outputting an error position detection signal using the error position detection coefficient; And an error correction unit that is controlled by the selection control signal and corrects an error at a corresponding position using the error position detection signal.

The encoder includes a plurality of error correction encoders capable of correcting other error bits of the document, and the plurality of error correction encoders receive data bits of the same size and receive codewords having parity bits of different sizes .

The syndrome generation unit may include a plurality of syndrome generators, and some or all of the plurality of syndrome generators may be controlled by the selection control signal according to the number of error correction bits.

The key acquisition solver may further include: a temporary storage unit for temporarily storing and outputting the syndrome values sequentially input; A processing module unit controlled by the selection control signal to output an error estimation position value and an error position detection coefficient; A multiplier for multiplying the syndrome value output from the temporary storage unit by the error estimation position value and outputting a plurality of multiplication result values; An adding unit operable to add and output the multiplication result values output from the multiplier; And a control unit for outputting a control signal for controlling the processing module unit by using an addition result value output from the addition unit.

According to a second aspect of the present invention, there is provided an error-correcting encoder of a variable structure, comprising: a main controller for outputting a selection control signal corresponding to the number of error correction bits; An encoder for multiplying an input data bit by a generator matrix and outputting a code word composed of a data bit and a parity bit; A syndrome generation unit for receiving a codeword received from the storage unit and outputting a syndrome value; A key assignment solver for generating an error position detection coefficient for detecting an error position using the syndrome value; An error position detection unit for outputting an error position detection signal using the error position detection coefficient; And an error correcting unit for correcting an error of a corresponding position using the error position detecting signal, wherein the error correcting unit corrects the syndrome generating unit, the key assignment solver, and a part of each of the error position detecting units Or all of them are controlled to the same ratio to the selection control signal.

According to the error-correcting encoder of the variable structure of the present invention, the structure driven according to the noise environment can be different, and the number of syndrome generators driven according to the noise size can be varied. In addition, The number of generating units may be different and the number of error evaluating polynomial generating units driven according to the noise size may be different and the amount of power consumed for error correction may be different depending on the noise size.

1 is an overall block diagram of a variable-structure error-correcting encoder according to an embodiment of the present invention,
2 is a detailed configuration diagram of an encoder in an error-correcting encoder of a variable structure according to an embodiment of the present invention,
3 is a detailed configuration diagram of a syndrome generator in a variable-structure error-correcting encoder according to an embodiment of the present invention,
FIG. 4 is a detailed block diagram of an error location polynomial generation unit in a variable-structure error correction encoder according to an embodiment of the present invention, and FIG.
5 is a detailed configuration diagram of an error evaluating polynomial generating unit in a error-correcting encoder of a variable structure according to an embodiment of the present invention.

Specific features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. Prior to this, terms and words used in the present specification and claims are to be interpreted in accordance with the technical idea of the present invention based on the principle that the inventor can properly define the concept of the term in order to explain his invention in the best way. It should be interpreted in terms of meaning and concept. It is to be noted that the detailed description of known functions and constructions related to the present invention is omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

1 is a block diagram of an error-correcting encoder of a variable structure according to an embodiment of the present invention.

The error-correcting encoder of a variable structure according to an embodiment of the present invention includes an encoder 210 and a decoder 220. The decoder 220 includes a syndrome generating unit 221, a key allocation solver 222, A position detection unit 223, an error correction unit 224, and a first-in-first-out unit 225.

The main control unit 100 generates a control signal for controlling the number of operations of the encoder 210, the syndrome generating unit 221, the keying solver 222, and the error position detecting unit 223.

The encoder 210 is controlled by the selection control signal Ssel of the main control unit 100 and outputs a codeword including a data bit and a parity bit by multiplying a data bit input from the processor 300 by a generator matrix .

The syndrome generation unit 221 is controlled by a selection control signal Ssel of the main control unit 100 and receives a codeword received from a storage unit such as the flash memory 400 to calculate a syndrome value.

The key selection solver 222 is controlled by the selection control signal Ssel of the main control unit 100 and generates an error position detection coefficient for detecting the error position using the syndrome value output from the syndrome generation unit 221 .

The error position detection unit 223 is controlled by the selection control signal Ssel of the main control unit 100 and detects an error position using an error position detection coefficient outputted from the key assignment solver 222 And outputs a signal.

The error correction unit 224 is controlled by the selection control signal Ssel of the main control unit 100 and corrects the error by calculating the error position detection signal output from the error position detection unit 223 and the data bits using the exclusive OR.

The first-in-first-out unit 225 receives a codeword received from the flash memory 400 to compensate for a time delay while passing through the syndrome generating unit 221, the keying solver 222, and the error position detecting unit 223 And outputs them sequentially in a predetermined time delay.

2 is a detailed configuration diagram of an encoder in an error-correcting encoder of a variable structure according to an embodiment of the present invention.

The encoder 210 in the error-correcting encoder of the variable structure according to an embodiment of the present invention includes a selector 211 for outputting a data bit controlled by the selection control signal Ssel and input to one of a plurality of output terminals, And a plurality of error bit correcting encoders 212, 213, and 214 connected in parallel to the output terminals of the error correcting unit 211, respectively.

Here, the plurality of error bit correcting encoders 212, 213, and 214 are used to correct different error bits. Since the number of error bits to be corrected is the same (for example, 128 bits) Are different. For example, the parity bit of the code word output by the 2-bit error correction encoder 212 is 16 bits, the parity bit of the code word output by the 4-bit error correction encoder 213 is 32 bits, and the 8-bit error correction encoder The parity bit of the code word output by the parity checker 214 includes 64 bits.

It should be noted that the detailed structure of the encoder is obvious to those skilled in the art with respect to encoding, and that it can be designed in various ways.

FIG. 3A is a state diagram showing the use of a syndrome generator in an 8-bit error correction mode according to an embodiment of the present invention, FIG. 3B is a state diagram illustrating a syndrome generator in a 4-bit error correction mode according to an embodiment of the present invention, FIG. 4 is a state diagram showing the use of a syndrome generator in a 2-bit error correction mode according to an embodiment of the present invention. FIG.

The syndrome generator 221 in the error-correcting encoder of the variable structure according to the embodiment of the present invention includes 16 syndrome generators (S1, S2, ..., S16) connected in parallel if the maximum error bit that can be corrected is 8 bits , And the individual syndrome generators (S1, S2, ..., S16) may be implemented to satisfy Equation (1).

는 갈로아 필드의 원소이다.Where t is the number of correctable error bits, n is the codeword length and r is the data containing the error,

Is the element of Galois field.

The polynomial for each syndrome generator is, for example, the following equation.

...

According to an embodiment of the present invention, in the 8-bit error correcting mode, all the syndrome generators S1, S2, ..., S16 are used as shown in FIG. 3A, 8 control signals Ssel of the main control section 100 to use eight syndrome generators S1, S2, ..., S8 as shown in Fig. 3B, and a 2-bit error correction mode The four syndrome generators S1, S2, S3, and S4 are used, as shown in Fig. 3C, by being controlled by the selection control signal Ssel of the main control section 100. [ At this time, an enable element (not shown) is disposed at the input terminal of the individual syndrome generator and can be controlled and enabled by the selection control signal Ssel.

Although not shown, the driving of some or all of the plurality of syndrome generators can be controlled by processing the data r to "0 " by using the selection control signal Ssel. For example, when four syndrome generators (S1, S2, S3, S4) are used, a value obtained by performing a logical product of the data control signal Ssel and the data r is used as the input of the remaining syndrome generator The output of the remaining syndrome generator can be controlled.

4A is a specific configuration diagram of a syndrome generator S1 according to an embodiment of the present invention, and Equation 2 is implemented in a fully parallel structure.

That is, although there is an advantage that the operation can be processed quickly by multiplying and adding the right term of the expression (2) in one cycle, there is a problem that a large area is required.

In the meantime, the addition or multiplication referred to throughout the description of the present invention and throughout the drawings refers to an arithmetic addition or multiplication in a Galois Field.

FIG. 4B is a specific configuration diagram of a syndrome generator S1 according to another embodiment of the present invention, and Equation 2 is implemented in a quasi-parallel structure.

That is, 15 of the equations (2) are implemented in parallel and one is implemented in series, and the multiplication and addition processes are performed for 12 cycles, thereby slowing the processing speed compared to the fully parallel structure. On the other hand, 12.

It is apparent to those skilled in the art that the number of serial and parallel lines in the multiplication and addition processes in the internal structure of the syndrome generator can be adjusted to further reduce the area for implementation.

5 is a detailed configuration diagram of a keying solver 222 in a variable-structure error-correcting encoder according to an embodiment of the present invention.

The key assignment solver 222 is controlled by the selection control signal Ssel of the main control unit 100 and generates an error position detection coefficient using the syndrome value Syn output from the syndrome generation unit 221. [

)과 오류 위치 검출 계수(

)를 출력하는 처리식 모듈부(520), 임시 저장부(510)로부터 출력되는 신드롬값(S)과 처리식 모듈부(520)로부터 출력되는 오류 추정 위치값(

)을 승산하여 결과값을 출력하는 승산부(530), 승산부(530)로부터 출력되는 복수의 승산 결과값을 가산하여 결과값을 출력하는 가산부(540), 가산부(540)로부터 출력되는 결과값을 이용하여 복수의 처리식 모듈부(520)를 제어하는 제어신호(cont.)를 출력하는 제어부(550)를 포함한다.The key assignment solver 222 is controlled by a temporary storage unit 510 for temporarily storing and sequentially outputting the sequentially inputted syndrome value Syn and a selection control signal Ssel of the main control unit 100, (Cont.) Output from the unit 550 and outputs an error estimated position value

) And error position detection coefficient (

A syndrome value S output from the temporary storage unit 510 and an error estimation position value S (S) output from the processing module 520

An adder 540 for adding a plurality of multiplication result values output from the multiplier 530 and outputting a result of the multiplication, an adder 540 for outputting the result of multiplication, And a control unit 550 for outputting a control signal cont. For controlling the plurality of processing module units 520 using the result values.

According to an embodiment of the present invention, the temporary storage unit 510 may be implemented with a plurality of registers (Reg0 511, Reg1 512, ..., Reg15 51f) connected in series.

0,

1,

2, ...,

15 )과 오류 위치 검출 계수(

)를 출력하는 복수의 처리식 모듈(PE0(521), PE1(522), ... , PE15(52f))로 구현될 수 있다.According to one embodiment of the present invention, the processing module unit 520 is connected to the control signal cont., Which is controlled by the selection control signal Ssel of the main control unit 100 and is output from the control unit 550, And the error estimated position value (

0,

One,

2, ...,

15) and error position detection coefficient (

(PE0 521, PE1 522, ..., PE15 52f) for outputting a plurality of process modules (PE0 521, PE1 522, ..., PE15 52f).

0,

1,

2, ...,

15 )을 승산하여 결과값(Q0, Q1, Q2, ..., Q15)을 병렬적으로 출력하는 복수의 승산 유닛(531, 532, ..., 53f)으로 구현될 수 있다.The multiplier 530 multiplies the individual syndromes S16, S15, and S155 output from each of the plurality of registers (Reg0 511, Reg1 512, ..., Reg15 51f) ..., S1) output from each of the processing modules (PE0 521, PE1 522, ..., PE15 52f)

0,

One,

2, ...,

..., and 53f that multiply the result values (Q0, Q1, Q2, ..., Q15) in parallel by multiplying the output values Q0,

In the 2-bit error correction mode, the temporary storage unit 510 stores four registers (Reg0 511, Reg1 512, and Reg2 513) adjacent to the syndrome generator 221, And Reg3 514 correspond to the processing module 520. The processing module 520 includes four processing modules (PE0 521, PE1 522, PE2 523 and PE3 524) 530 are used for the four multiplication units 531, 532, 533 and 534 respectively and four multiplication result values Q0, Q1, Q2 and Q3 are inputted to the addition unit 540.

According to another embodiment of the present invention, in the 4-bit error correction mode, the temporary storage unit 510 stores eight registers (Reg0 511, Reg1 512, ..., Reg7 (PE0 521, PE1 522, ..., PE7 528) and the multiplication section 530 corresponds to 8 And the multiplication result values Q0, Q1, Q2, ..., Q7 are input to the adder 540. The adder 540 multiplies the output values Q0, Q1, Q2, ..., Q7 by the multiplication units 531, 532,

According to another embodiment of the present invention, in the 8-bit error correction mode, the temporary storage unit 510 stores 16 registers (Reg0 511, Reg1 512, ..., Reg15 51f) The expression module 520 includes 16 processing modules (PE0 521, PE1 522, ..., PE15 52f), and the multiplier 530 multiplies 16 multiplication units 531, 532,. ..., and 53f, respectively.

6A is a detailed configuration diagram of a fully parallel method error position detector according to an embodiment of the present invention.

,

, ...,

)와 신드롬 제너레이터(221)에서 사용되는 갈로아 필드의 원소(

,

, ... ,

)를 승산 및 가산하여 복수의 오류 위치 검출 신호(

,

, ... ,

)를 출력한다.The error position detection unit 223 receives the error position detection coefficient (

,

, ...,

) And the element of the Galois field used in the syndrome generator 221

,

, ...,

) To multiply and add a plurality of error position detection signals (

,

, ...,

).

,

)를 이용하는 제1 모듈부(611)를 통해 오류 위치 검출 신호(

,

, ... ,

)를 출력할 수 있다. 본 발명의 다른 실시예에 따른 4비트 오류 정정 모드시, 4개의 오류 위치 검출 계수(

,

,

,

)를 이용하는 제2 모듈부(612)를 통해 오류 위치 검출 신호(

,

, ... ,

)를 출력할 수 있다. 본 발명의 또 다른 실시예에 따른 8비트 오류 정정 모드시, 8개의 오류 위치 검출 계수(

,

, ...,

)를 이용하는 제3 모듈부(613)를 통해 오류 위치 검출 신호(

,

, ... ,

)를 출력할 수 있다. For example, in the 2-bit error correction mode according to an embodiment of the present invention, two error position detection coefficients

,

Through the first module unit 611 using the error position detection signal

,

, ...,

Can be output. In the 4-bit error correction mode according to another embodiment of the present invention, four error position detection coefficients (

,

,

,

Through the second module unit 612 using the error position detection signal

,

, ...,

Can be output. In the 8-bit error correction mode according to another embodiment of the present invention, eight error position detection coefficients (

,

, ...,

Through the third module unit 613 using the error position detection signal

,

, ...,

Can be output.

,

, ...,

) 중

...,

를 "0"으로 처리한다. 이를 위하여, 오류 위치 검출 계수(

...,

)와 "0"값의 선택제어신호(Ssel)를 논리곱 연산한 결과값을 오류 위치 검출부(223)의 입력으로 사용한다.Although not shown, whether or not to use the first to third module units 611, 612, and 163 in the error position detection unit 223 can be determined using the selection control signal Ssel. For example, in order to use the first module unit 611 in the 2-bit correction mode, a plurality of error position detection coefficients (

,

, ...,

) Of

...,

Quot; 0 ". To this end, the error position detection coefficient (

...,

) And a selection control signal Ssel of a value of "0 " is used as an input to the error position detection unit 223.

FIG. 6B is a detailed configuration diagram of a quasi-parallel error location detector according to another embodiment of the present invention. In the quasi-parallel method using a multiplexer and a DF / F, On the other hand, the area to be implemented can be reduced to about 1/12.

It is apparent to those skilled in the art that the number of serial and parallel lines in the multiplication and addition processes in the internal structure of the error location detection unit 223 can be adjusted to further reduce the area to be implemented.

,

, ... ,

) 의 결과값이 "0"으로 나타난 위치를 오류가 발생된 위치로 판단하고, 선입선출부(225)를 통해 입력되는 데이터 중 오류 발생 위치와 데이터 비트를 배타적 논리합으로 연산하여 오류를 정정한다.The error correction unit 224 according to an embodiment of the present invention includes an error position detection signal

,

, ...,

) Is determined to be the position where the error is generated, and the error is corrected by calculating the error occurrence position and the data bit among the data input through the first-in-first selection unit 225 as an exclusive OR.

The error-correcting encoder of the variable structure according to the present invention can be widely applied to a data transmission technology. For example, the error-correcting encoder of the present invention can be applied to an SSD (Solid State Drive), an optical communication system, a DVB (Digital Video Broadcasting)

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the true technical protection scope of the present invention should be determined by technical thought.

100: main control unit 200: error correction coder
210: Encoder 220: Decoder
221: syndrome generator 222: keying solver
223: error position detection section 224: error correction section
225: first-in first-out portion 300: processor
400: flash memory

Claims (11)

A main control unit for outputting a selection control signal corresponding to the number of error correction bits;
An encoder controlled by the selection control signal and outputting a code word composed of a data bit and a parity bit by multiplying an input data bit by a generator matrix;
A syndrome generator which is controlled by the selection control signal and receives a codeword received from the storage unit and outputs a syndrome value;
A key assignment solver controlled by the selection control signal to generate an error position detection coefficient for detecting an error position using the syndrome value;
An error position detector which is controlled by the selection control signal and outputs an error position detection signal using the error position detection coefficient; And
And an error correction unit that is controlled by the selection control signal and corrects an error at a corresponding position using the error position detection signal,
Wherein the key assignment solver comprises:
A temporary storage unit for temporarily storing and outputting the syndrome values sequentially input;
A processing module controlled by the selection control signal to output an error estimation position value and the error position detection coefficient;
A multiplier for multiplying the syndrome value output from the temporary storage unit by the error estimation position value and outputting a plurality of multiplication result values;
An adding unit operable to add and output the multiplication result values output from the multiplier; And
And a control unit for outputting a control signal for controlling the process module unit using the addition result value output from the addition unit
And a variable-length error-correcting encoder. The method according to claim 1,
The encoder includes a plurality of error correction encoders capable of correcting different error bits. The plurality of error correction encoders receive a data bit of the same size and output a code word including parity bits of different sizes A variable-structure error-correcting encoder. The method according to claim 1,
Wherein the syndrome generation unit includes a plurality of syndrome generators, and a part or all of the plurality of syndrome generators is controlled by the selection control signal according to the number of error correction bits. The method of claim 3,
Wherein one of the plurality of syndrome generators implements the following equation in a fully parallel manner.

Where t is the number of correctable error bits, n is the codeword length and r is the data containing the error,

Is the origin of Galoa Field. The method of claim 3,
Wherein one of the plurality of syndrome generators implements the following equation in a quasi-parallel manner.

Where t is the number of correctable error bits, n is the codeword length and r is the data containing the error,

Is the origin of Galoa Field. delete The method according to claim 1,
Wherein the processing module unit includes a plurality of processing modules, and the control unit controls the plurality of processing modules synchronously. 8. The method of claim 7,
And a part or all of the plurality of processing modules are controlled by the selection control signal according to the number of error correction bits. delete The method according to claim 1,
Wherein the error position detection unit includes a variable structure error correction unit that multiplies and adds an error position detection coefficient output from the key assignment solver and an element of a Galois field used in the syndrome generation unit to output a plurality of error position detection signals, Encoder. A main control unit for outputting a selection control signal corresponding to the number of error correction bits;
An encoder for multiplying an input data bit by a generator matrix and outputting a code word composed of a data bit and a parity bit;
A syndrome generator for receiving a codeword received from a storage unit and outputting a syndrome value;
A key assignment solver for generating an error position detection coefficient for detecting an error position using the syndrome value;
An error position detection unit for outputting an error position detection signal using the error position detection coefficient; And
And an error correcting unit correcting an error of the corresponding position by using the error position detecting signal,
Wherein the key assignment solver comprises:
A temporary storage unit for temporarily storing and outputting the syndrome values sequentially input;
A processing module controlled by the selection control signal to output an error estimation position value and the error position detection coefficient;
A multiplier for multiplying the syndrome value output from the temporary storage unit by the error estimation position value and outputting a plurality of multiplication result values;
An adding unit operable to add and output the multiplication result values output from the multiplier; And
And a control unit for outputting a control signal for controlling the processing module unit by using an addition result value output from the addition unit,
Wherein the processing module portion comprises a plurality of processing modules,
Wherein a part or all of the plurality of processing modules are controlled by the selection control signal according to the number of error correction bits
Variable Structure Error Correction Coder.

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