KR102118605B1 - Low complexity high order syndrome calculator for block codes and calculating method of high order syndrome - Google Patents

Abstract

Disclosed is a high-order syndrome calculator and a high-order syndrome calculation method for calculating a high-order syndrome with low complexity for a block code. A serial-to-parallel converter that converts serial bit sequences received from a transmitter into multiple parallel streams, an XOR operator that performs an XOR operation on each bit value of multiple streams, and inserts zero values between each bit where an XOR operation is performed. It is possible to provide a high-order syndrome calculator including a zero-interpolation unit and a linear feedback shift register for calculating a high-order syndrome value by a coefficient of the remainder obtained by dividing a polynomial generated from multiple streams with zero values divided by a raw polynomial.

Description

LOW COMPLEXITY HIGH ORDER SYNDROME CALCULATOR FOR BLOCK CODES AND CALCULATING METHOD OF HIGH ORDER SYNDROME}

The following embodiments relate to a high-order syndrome calculator and a high-order syndrome calculation method for calculating a high-order syndrome with low complexity for a block code.

Block codes are widely used among error correcting codes. The block code includes, for example, a Hamming code capable of error correction for one bit, a BCH code capable of error correction for a plurality of bits (Bose-Chadhuri-Hocquenghem code), and a plurality of bits in one Resid-Solomon error correction code (RS code), which is regarded as a symbol and reconstructs errors in units of symbols, may be included.

The block code increases complexity in decoding rather than encoding. In addition, when a reception error occurs, a BCH code or RS code that restores errors in a plurality of bits or symbols is superior in efficiency to a Hamming code having error recovery capability for one bit, but increases computational complexity. .

In low-power transmitters and receivers, since the transmission signal has low power, communication reliability between the transmitter and the receiver may deteriorate. In a communication system requiring low power, calculation of low complexity is required when applying an error correction code. For example, in many small sensors used in various wireless sensor networks and local area networks, calculation of low power and low complexity is basically required to operate for a long time.

According to one embodiment, a high-order syndrome calculator includes a serial-to-parallel converter that converts a series of bit sequences received from a transmitter into multiple parallel streams; An XOR operator that performs an XOR operation on each bit value of the multiple streams; A zero interpolator that inserts zero values between each bit in which the XOR operation is performed; And a linear feedback shift register calculating a higher order syndrome value by a coefficient of the remainder obtained by dividing the polynomial generated from the multiple streams in which the zero values are inserted by a primitive polynomial. shift register).

The serial-to-parallel converter delays the serial bit sequences received from the transmitter by an integer multiple of a specific number of bits (D) satisfying the following Equation (L), a multiple stream of L (natural numbers with L ≥ 1) bits. Can be converted to

<Mathematics>

D = n/j

(Where n is the block size of the block code, j is the order of the syndrome to obtain, and n/j is an integer)

The serial-to-parallel converter includes L-1 delay elements, inputs the bit sequence without delay to the first bit of the multi-stream, and inputs the bit sequence (L-1 to the L-th bit of the multi-stream). ) x D bits can be delayed for input.

The serial-to-parallel converter may transmit the bit sequences received from the transmitter to the zero interpolator without delay when the n/j value is not an integer.

When the n/j value is not an integer, the zero interpolation unit may periodically insert N (N = j-1) zero values between each bit of the multi-stream in which the XOR operation is performed. have.

The zero interpolation unit may periodically insert N (N = L-1) zero values between each bit of the multi-stream in which the XOR operation is performed.

According to one embodiment, a high-order syndrome calculator converts a series of bit sequences received from a transmitter into a parallel multiple stream consisting of symbol units, wherein the symbol units include a plurality of bits. A serial-to-parallel converter; An XOR operator that performs an XOR operation on the bit values of the multiple streams configured in the symbol unit in the symbol unit; A zero interpolator that inserts zero values between each bit of the multi-stream in which the XOR operation is performed; And a linear feedback shift register calculating a higher order syndrome value by a coefficient of the remainder obtained by dividing the polynomial generated from the multiple streams in which the zero values are inserted by a primitive polynomial. shift register).

The serial-to-parallel converter delays the sequence of bit sequences received from the transmitter by an integer multiple of a specific number of bits (D) that satisfies <Equation> below, so that the symbol unit* L (a natural number with L ≥ 1) Can convert to multiple streams of bits.

<Mathematics>

D = n/j

(Where n is the block size of the block code that satisfies the symbol unit, j is the order of the syndrome to be obtained, and n/j is an integer)

When the n/j value is not an integer, the serial-to-parallel converter may transmit the bit sequences received from the transmitter to the zero interpolation unit without delay.

When the n/j value is not an integer, the zero interpolation unit periodically inserts N (N = j-1) zero values in a symbol unit between each bit of the multi-stream in which the XOR operation is performed. can do.

The zero interpolation unit may periodically insert N (N = L-1) zero values in a symbol unit between each bit of the multi-stream in which the XOR operation is performed.

According to an embodiment, a method for calculating a higher order syndrome may include converting a series of bit sequences received from a transmitter into multiple streams in parallel; Performing an XOR operation on each bit value of the multiple streams; Inserting zero values between each bit of the multi-stream in which the XOR operation is performed; And calculating a higher-order syndrome value by a coefficient of the remainder obtained by dividing the polynomial generated from the multiple streams into which the zero values are inserted into a primitive polynomial.

According to an embodiment, a method of calculating a higher order syndrome may include converting a series of bit sequences received from a transmitter into a parallel multiple stream consisting of symbol units, wherein the symbol units include a plurality of bits; Performing an XOR operation in units of the symbols on the bit values of the multiple streams; Inserting zero values between each bit of the multi-stream in which the XOR operation is performed; And calculating a higher order syndrome value by a coefficient of the remainder divided by a polynomial generated from the multiple streams in which the zero values are inserted into a primitive polynomial.

1 is a block diagram of a channel encoder 100 that encodes a block code at the transmitter.
2 is a block diagram of a channel decoder 200 for decoding block codes at a receiver.
FIG. 3 is a diagram illustrating an example of a look-up table (LUT) used for calculation of a primitive polynomial in a Galois field by a general syndrome calculation method.
4 is a diagram illustrating a process of calculating S ₃ when m = 6 and n = 63 by a general syndrome calculation method.
5 is a block diagram of a high-order syndrome calculator according to an embodiment.
FIG. 6 is a diagram specifically showing the structure of the high-order syndrome calculator of FIG. 5.
7 is a view for explaining the operation performed in each part of the high-order syndrome calculator (high-order syndrome calculator) according to an embodiment to obtain the S ₃ in the case of m = 6, n = 63.
8 is a block diagram of a higher-order syndrome calculator according to another embodiment.
9 is a flowchart illustrating a method for calculating a higher order syndrome according to an embodiment.
10 is a flowchart illustrating a high-order syndrome calculation method according to another embodiment.
11 is a view showing a result of comparing the calculation complexity according to a general syndrome calculation method and a high-order syndrome calculation method according to an embodiment.
12 is a view showing a result of comparing the calculation complexity of calculating S ₃ according to a general syndrome calculation method and a high-order syndrome calculation method according to an embodiment when m = 6 and n = 2 ^m -1 = 63.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. In addition, the same reference numerals in each drawing denote the same members.

Error correcting code (error correcting code) is one of techniques that can improve communication reliability in a digital communication system. For example, due to various non-ideal communication channel environments including random noise and the like, errors may occur in bit information received by the receiver. At this time, the receiver detects and corrects the occurrence of an error by an error correction code, thereby improving the reliability of communication by restoring the bit information that the transmitter originally intended to transmit.

The error correction code can be roughly divided into a block code and a convolutional code. The block code is a basic code that is widely used, and coding is performed in units of blocks having a constant length. The block code constructs a sequence of encoded bits of a certain length by adding a redundant bit called a parity bit to the message bit information of a certain length to be transmitted.

Hamming code, the most basic block code, has one bit of error correcting capability. In other words, the Hamming code can be corrected when one bit error occurs in a bit sequence of one block received from a transmitter, but cannot be properly restored when an error occurs in two or more bits.

The BCH code can correct two or more errors by using various parameters. Hamming code can be considered as a type of BCH code.

The RS code considers a plurality of bits as one symbol, and performs signal processing on a symbol basis. The RS code sees a plurality of bits as one symbol and configures a certain number of symbols into one block.

When using the RS code, encoding and decoding are performed on a symbol basis, and error recovery is also performed on a fixed number of symbols basis. The RS code is a robust code to a burst error in which multiple errors exist in a single symbol and errors are recovered in units of symbols, and errors adjacent to each other occur.

1 is a block diagram of a channel encoder 100 that encodes a block code at the transmitter.

Referring to FIG. 1, a structure of a channel encoder 100 for encoding block codes at a transmitter is illustrated.

After the channel encoder 100 appropriately adds nk parity bits corresponding to the redundant bit to k message bits corresponding to the original bit information, , Constructs all n bit sequence blocks and transmits them to the receiver.

In the above-described method, the n bit sequence blocks transmitted by the channel encoder 100 are usually referred to as (n,k) block codes, and the n-bit sequence output from the channel encoder 100 is a'codeword. )'. At this time, in the n-bit sequence (sequence), the k message bits are not changed, and only the parity bits are transmitted, so the n-bit sequence is called a'systematic code'. The receiver receives and decodes the encoded bit sequence from the channel encoder 100. The structure of the channel decoder of the receiver will be described with reference to FIG. 2.

2 is a block diagram of a channel decoder 200 for decoding block codes at a receiver.

Referring to FIG. 2, a structure of a channel decoder 200 for decoding block codes at a receiver is illustrated.

In the receiver, a bit sequence demodulated to '0' or '1' first through a demodulator is input to the channel decoder 200. At this time, an error bit may exist in the demodulated bit sequence due to various non-ideal communication channel environments, such as noise.

As illustrated in FIG. 2, the channel decoder 200 may appropriately process n demodulated bit sequences to recover an error and obtain k decoded output bit sequences. At this time, if an error occurs in more bits than the error recovery capability of the block code in the demodulated bit sequence, the output bit sequence may be different from the bit sequence originally transmitted by the transmitter.

The channel decoder 200 may include a syndrome calculator 210, an error location calculator 230, and an error correction unit 250.

The syndrome calculator 210 may calculate a syndrome value.

The'syndrome' is a value used as a criterion for determining whether there is an error in a bit sequence received from a transmitter to a receiver. For example, if the syndrome value is not zero, it means that an error has occurred, so that the receiver can perform signal processing for error recovery.

In addition, in order to recover the error, it is necessary to know the position of the error bit in the entire received sequence of bits to correct the error bit. The error location calculator 230 may calculate the location of the bit in error. The syndrome value previously obtained can be used to calculate the position of the bit that has an error.

The error correction unit 250 may correct the error of the corresponding bit at the position of the bit where the error occurred, as determined by the error location calculator 230. The error corrector 250 may correct, for example, an error bit from '1' to '0', or from '0' to '1'.

In the case of a Hamming code that has one error recovery capability, only one syndrome value needs to be obtained. When a code having a plurality of error recovery capabilities is used, computational complexity increases because a plurality of syndrome values must also be obtained.

When a plurality of syndrome values are to be obtained, let the order of the syndrome be j, and the jth syndrome is S _j . More detailed definition and mathematical content of S _j will be described later. The complexity of the calculation may increase as the j value, which is the order of the syndrome, increases, that is, as a higher order syndrome value is obtained.

In one embodiment, a method of reducing computational complexity of a high-order syndrome in which a j value is greater than 1 in a block code having a plurality of error correction capabilities is described.

Before explaining the method of calculating the syndrome, the Galois field, which is the basis of the block code, and its operation will be described below.

The Galois field can be expressed as GF(p ^m ) for the prime number p and the positive integer m, and can also be called a'finite field' because it has a finite number of elements.

There are p ^m elements in the Galois field GF (p ^m ). The definitions of primitive elements and primitive polynomials used in the Galois field are as follows.

∈ GF(q)는 GF(q)에서 primitive (q-1)th root of unity를 만족하는 경우, 유한체 GF(q)의 '원시 요소(primitive element)'라고 불린다. 다시 말해, 유한체 GF(q)의 모든 구성 요소들(0는 제외)은 양의 정수 n에 대해 aⁿ 와 같이 표현할 수 있다.Primitive elements:

∈ When GF(q) satisfies the primitive (q-1)th root of unity in GF(q), it is called a'primitive element' of the finite body GF(q). In other words, all the components of the finite field GF(q) (except for 0) can be expressed as a ⁿ for a positive integer n.

를 가지는 경우, '원시 다항식(primitive polynomial)'이라고 불린다. 기약 다항식(irreducible polynomial) f(x)의 차수 m은 f(x) 나누기 (xⁿ + 1)이 n = 2^m - 1을 만족하는 최소 양의 정수 n인 경우, '원시(primitive)'라고 불린다.
ㆍprimitive polynomial: polynomial f(x) with coefficients in GF(p) has a degree ^m , and {0, 1, a, a ² ,… in GF(p ^m ). , root satisfying a^(p ^m -2)}

In the case of having, it is called a'primitive polynomial'. The degree m of the irreducible polynomial f(x) is called'primitive' if the f(x) division (x ⁿ + 1) is the smallest positive integer n satisfying n = 2 ^m -1 Is called.

라고 했을 때,

및

의 등식이 성립함은 이미 알려져 있다.According to the above definition, the primitive element of the Galois field GF(p ^m ) is called a, and the m-th primitive polynomial

When I said,

And

It is already known that the equation of.

가 되며,

이 된다. 갈루아 필드 연산에서는 1+1 = 0,

과 같은 모듈로(modulo) 덧셈 연산이 수행되며, 이를 이용하면,

를 얻을 수 있다. For example, if m=6

Becomes

It becomes. 1+1 = 0 in Galois field operations,

Modulo addition operation is performed.

Can get

와 같은 곱셈 연산이 수행됨을 이용하면,

을 얻을 수 있다. 유사한 갈루아 필드 연산 과정을 이용하면 아래의 [표 1]과 같이 m=6일 경우의 GF(p^m) 원소들을 구성할 수 있다.Also in Galois field operations

Using a multiplication operation such as

Can get Using a similar Galois field operation process, as shown in [Table 1] below, GF(p ^m ) elements when m=6 can be constructed.

Table 1 shows the components of GF(2 ⁶ ) produced by primitive polynomial 1+x+x ⁶ .

로 표현한 polynomial representation에 해당한다. 여기서

은 '0' 혹은 '1'의 값을 가지는 계수(coefficient)에 해당한다. In [Table 1], the first column (column) is a power representation showing the multiplier of the primitive element a, and the second column is for the same element in the first column.

Corresponds to the polynomial representation expressed as. here

Is a coefficient having a value of '0' or '1'.

값들을

와 같은 벡터 형태로 나타낸 vector representation에 해당한다. 여기서,

의 승수에 해당하는 정수를 input index로 하고, vector 값을 output으로 하는 look-up table (LUT)를 구성하면 도 3과 같이 표현할 수 있다.The third column is the coefficient

Values

Corresponds to the vector representation represented in the vector form. here,

When an integer corresponding to the multiplier of is set as an input index and a look-up table (LUT) having a vector value as an output is constructed, it can be expressed as in FIG. 3.

FIG. 3 is a diagram illustrating an example of a look-up table (LUT) used for calculation of a primitive polynomial in a Galois field by a general syndrome calculation method.

Hereinafter, a basic formula for obtaining a syndrome will be described.

로 표현하면, 그 다항식은

로 표현될 수 있다. 이때, j번째 신드롬에 해당하는

는 다음의 <수학식 1>과 같이 구할 수 있다. The received bit vector of n bits containing errors received by the receiver

In terms of, the polynomial

Can be expressed as At this time, it corresponds to the jth syndrome

Can be obtained as <Equation 1> below.

는 위에서 설명한 GF(p^m)의 primitive element에 해당하고, n=2^m-1가 된다.
here,

Is the primitive element of GF(p ^m ) described above, and n=2 ^m -1.

As described above, the process of obtaining a syndrome is a signal processing process that is first performed when decoding a block code. If the syndrome value is not '0', it means that an error has occurred in the received bits and correction is necessary.

The following describes a general syndrome calculation method for obtaining S ₃ .

Using <Equation 1> described above, S ₃ can be expressed as follows.

은 m개의 비트들로 구성된 vector인

의

번째 값에 해당하며,

는 아래와 같이 구할 수 있다.
here,

Is a vector of m bits

of

Corresponds to the first value,

Can be obtained as follows.

는 도 3의 LUT 함수(function)에 해당하며

관계를 만족한다. here,

3 corresponds to the LUT function of FIG. 3,

Satisfy the relationship.

인 경우를 가정하면,

가 얻어진다.To more easily illustrate the above signal processing, m=6, n=2 ^m -1=63,

Assuming that

Is obtained.

값을 구하여 이를 더하는 과정에 해당한다. 일반적인 신드롬 계산 방법에 의해 S₃에 대한 신드롬을 구하는 과정은 도 4와 같이 표현될 수 있다.
As a result, the process of obtaining the syndrome for S ₃ is

It corresponds to the process of obtaining a value and adding it. The process of obtaining a syndrome for S ₃ by a general syndrome calculation method may be expressed as shown in FIG. 4.

4 is a diagram illustrating a process of calculating S ₃ when m=6 and n=63 by a general syndrome method.

의 승수값을 구할 때, 비트 시퀀스의 인덱스(index)에 신드롬의 차수(syndrome order)에 해당하는 값을 곱하는 과정을 수행한다. Referring to Figure 4, the general syndrome method is the first column

When obtaining the multiplier value of, the process of multiplying the index of the bit sequence by the value corresponding to the syndrome order.

의 성질을 만족하고,

의 승수값에 modulo-(2^m-1)를 취해도 동일한 값을 가지므로 modulo-63 연산을 수행하는 것이다. In addition, in the second column, the general syndrome method performs modulo-(2 ^m -1), that is, modulo-63 operation on the multiplier obtained above. In the Galois field as mentioned above

Satisfies the nature of,

Even if modulo-(2 ^m -1) is taken as the multiplier value of, the modulo-63 operation is performed because it has the same value.

승수값 결과를 입력 값으로 했을 때의 룩업 테이블의 출력 벡터(LUT_output_vector)를 찾아서 구하고, 이를 출력으로 내보내는 과정을 수행할 수 있다. The general syndrome method is after modulo-63 operation.

The process of finding and obtaining the output vector (LUT_output_vector) of the lookup table when the multiplier result is an input value and exporting it to the output may be performed.

값들을 계수로 하여 신드롬

를 구할 수 있다. The general syndrome method performs bitwise XOR operation on each output vector obtained in this way, and corresponds to the final value.

Syndrome with values as coefficients

Can be obtained.

However, the above-described general syndrome calculation method requires a multiplication operation, a modulo operation, and the like. In addition, a general syndrome calculation method requires storage space for storing bit information of a large size in order to construct a look-up table (LUT).

In addition, in the case of a general syndrome calculation method, a frequent lookup table function call is made because a continuous search process for finding stored information mapped to an input index must be performed. Frequent lookup table function calls entail increased operational complexity and increased power consumption.

5 is a block diagram of a high-order syndrome calculator according to an embodiment.

Referring to FIG. 5, a high-order syndrome calculator 500 according to an embodiment includes a serial-to-parallel converter 510, an XOR operator 530, and a zero interpolator. ) 550, and a Linear Feedback Shift Register (LFSR) 570.

The serial-parallel converter 510 may convert serial bit sequences received from a transmitter into multiple streams in parallel.

The serial-to-parallel converter 510 delays the sequence of bit sequences received from the transmitter by an integer multiple of a specific number of bits (D) satisfying D = n/j into multiple streams of L (natural numbers with L ≥ 1) bits. Can be converted. Here, n is the block size of the block code, j is the order of the syndrome to be obtained, and n/j is an integer.

이고, 두 번째 다중 스트림이

인 경우,

와 같이 각 비트 값에 대하여 XOR(exclusive OR) 연산을 수행할 수 있다. 여기서,

는 XOR(exclusive OR), 다시 말해 modulo-2 연산을 뜻한다. The XOR operator 530 may perform an XOR (exclusive OR) operation on each bit value of multiple streams in parallel, converted by the serial-to-parallel converter 510. XOR operator 530, for example, the first multiple stream

And the second multiple stream

If it is,

As described above, an XOR (exclusive OR) operation can be performed on each bit value. here,

Means XOR (exclusive OR), that is, modulo-2 operation.

The zero interpolation unit 550 may insert zero values between each bit in which the XOR operation is performed in the XOR operator 530. The zero interpolation unit 550 may periodically insert N (N = L-1) zero values between each bit of the multi-stream in which the XOR operation is performed.

The zero interpolation unit 550 is N number between each bit of a multi-stream in which an XOR operation is performed when a specific number of bits D calculated by the serial-to-parallel converter 510, that is, when an n/j value is not an integer Zero values of (N = j-1) can be inserted periodically.

The linear feedback shift register 570 is higher order by the coefficient of the remainder divided by the polynomial generated from multiple streams in which zero values are inserted in the zero interpolator 550 by the primitive polynomial. The syndrome value can be calculated.

FIG. 6 is a diagram specifically showing the structure of the high-order syndrome calculator of FIG. 5.

Referring to FIG. 6, the high-order syndrome calculator 600 according to an embodiment includes a serial-to-parallel converter 610, an XOR operator 630, and a zero interpolator. ) 650, and Linear Feedback Shift Register (LFSR) 670.

The serial bit sequence received from the transmitter in FIG. 6 first passes through the serial-parallel converter 610. The serial-to-parallel converter 610 may include L-1 delay elements. Here, the delay elements may be, for example, a flip-flop or a register corresponding to a unit-delay element.

The serial-to-parallel converter 610 inputs the bit sequence input to the first bit of the multiple stream without delay, and inputs the bit sequence to the Lth bit of the multiple stream by delaying (L-1) X D bits.

For example, suppose the serial-to-parallel converter 610 converts a series of bit sequences into multiple streams of L bits. At this time, the serial-to-parallel converter 610 is composed of L parallel paths (parallel path), the serial-to-parallel converter 610 is the received bit sequence of the specific number of bits (D) for the L parallel paths It can be input by delaying by an integer multiple of time.

The received bit sequence is input as it is without delay in the first path, the bit sequence delayed by the number of D bits compared to the first path is input in the second path, and the number of 2 x D bits is compared to the first path in the third path. A bit sequence delayed by as much as it can be input. In this way, a bit sequence delayed by (L-1) x D bits compared to the first path may be input to the L-th path.

The XOR operator 630 may perform an XOR operation as described above for each bit value of multiple streams in parallel.

The zero interpolation unit 650 may periodically insert N (N = L-1) zero values between each bit of a multi-stream in which an XOR operation is performed. Here, the method of setting the L, D and N values will be described as an example.

를 구하고자 할 때), 고차 신드롬 계산기(600)는 L = j, D = n/j, N = L-1 과 같은 값을 취할 수 있다. If the block size of the block code is n and the syndrome order to be calculated is j (in other words,

), the higher order syndrome calculator 600 may take values such as L = j, D = n/j, and N = L-1.

If the n/j value does not become an integer value, the higher order syndrome calculator 600 may set each value as L = 1, D = 0, and N = j-1. At this time, in the high-order syndrome calculator 600, the conversion process of the serial-to-parallel converter 610 is not performed, and zero interpolation by the zero interpolation unit 650 may be performed on the received bit sequence. have.

The multiple streams with zero values inserted in the zero interpolation unit 650 may be applied as an input of the linear feedback shift register (LFSR) 670.

The FF 673 illustrated in FIG. 6 may be, for example, a register corresponding to a flip-flop or unit-delay element.

는 '0' 혹은 '1' 값을 가질 수 있다. In the linear feedback shift register (LFSR) 670, FF 673 may exist as many as m corresponding to a relational expression of n=2 ^m -1. In Linear Feedback Shift Register (LFSR) 670

May have a value of '0' or '1'.

이 '0' 값을 가지는 경우에는 XOR 연산기(671)으로 연결되는 선이 존재하지 않고,

이 '1' 값을 가지는 경우에는 XOR 연산기(671)으로 연결되는 선이 존재한다. In the linear feedback shift register (LFSR) 670,

If it has this '0' value, there is no line connected to the XOR operator 671,

In the case of having this '1' value, a line connected to the XOR operator 671 exists.

는 앞서 설명한, 그 차수(degree)가 m인 원시 다항식(primitive polynomial)

의 계수를 뜻하며,

의 관계를 만족한다. At this time,

Is the primitive polynomial whose degree is m, as described above.

Means the coefficient of

Satisfies the relationship.

번째 FF값을

라고 하면, 고차 신드롬(high-order syndrome) 값은 그 계수들로 구성한

에 의해 구할 수 있다. After the input values of the linear feedback shift register (LFSR) 670 are all input, the last stored value

The first FF value

Speaking of, the high-order syndrome value is composed of the coefficients.

Can be obtained by

로 나눈 나머지(remainder)에 해당하는 결과를 출력할 수 있다. The structure of the linear feedback shift register (LFSR) 670 is an input polynomial to a primitive polynomial.

The result corresponding to the remainder divided by (remainder) can be output.

로 나누었을 때의 나머지 다항식의 계수(coefficient)에 해당한다.When the linear feedback shift register (LFSR) 670 accepts all input sequences, the values stored in the FFs 673 are input polynomials.

Corresponds to the coefficient of the remainder polynomial when divided by.

에 대한 신드롬을 구하는 과정을 예를 들어 설명한다. To describe the operation of the syndrome calculator 600 according to an embodiment in more detail

The process of obtaining a syndrome for an example is explained.

For example, in the case of m=6, n=2 ^m -1=63, the overall operation for obtaining S ₃ is expressed as Equation 2 below.

는 전술한 바와 같이 수신된 다항식(received polynomial)을 뜻하고,

및

각각은 수신된 다항식을 원시 다항식(primitive polynomial)인

로 나누었을 때, 몫(quotient)과 나머지(remainder)에 해당한다.
here,

Means the received polynomial as described above,

And

Each received polynomial is a primitive polynomial.

When divided by, it corresponds to quotient and remainder.

에 대해

를 만족하므로 <수학식 2>의 마지막 등호 결과가 유도된다. In the Galois field, it is a primitive element

About

Is satisfied, the result of the last equal sign in <Equation 2> is derived.

를 구하는 방법을 일실시예에 따른 고차 신드롬 계산기와 함께 직관적으로 표현하면 도 7과 같다.
For easier explanation, if n=63

If the method for obtaining is intuitively expressed together with the high-order syndrome calculator according to an embodiment, it is as shown in FIG. 7.

7 is a view for explaining the operation performed in each part of the high-order syndrome calculator (high-order syndrome calculator) according to an embodiment to obtain S ₃ in the case of m=6 and n=63.

와 같이 3개의 값들이 서로 묶어서 한 항으로 표현된 것을 볼 수 있다. 이와 같은 표현 가능한 이유는 앞서 설명한 바와 같이 갈루아 필드에서는

의 성질을 만족하므로, m=6인 경우,

이 만족되고,

이 만족되기 때문이다. In the formula of Figure 7, for example,

You can see that the three values are grouped together and expressed as one term. The reason for this can be expressed in the Galois field, as explained earlier.

Since m = 6,

Is satisfied,

Because it is satisfied.

의 성질을 이용하여 최초 S₃ 수식에서 3개의 값들을 한 항으로 묶어서 701과 같은 두 번째 S₃ 수식을 유도할 수 있다. In the Galois field

By binding by the use of the properties of the three values in the first equation S ₃ with one of the preceding may derive a second equation S _3, such as 701.

As shown in the first S ₃ equation in FIG. 7, a process of delaying an input serial bit sequence by an integer multiple of a specific number of bits and placing it in a parallel path may be performed by the serial-parallel converter 710.

In the second S ₃ equation 701, the XOR operation for each bit value of the multiple streams may be performed by the XOR operator 730.

The explanation is as follows.

이고 가장 나중에 수신된 비트가

라고 가정하자. First, the first bit received in time

And the last received bit

Suppose

로 들어오는 것처럼 처리하고, 두 번째 경로에서는 이보다 21 샘플만큼 시간 지연된

스트림이 들어오는 것처럼 처리할 수 있다. 직렬-병렬 변환기(710)는 세 번째 경로에서는 첫 번째 경로보다 42(21 X 2) 샘플만큼 시간 지연된

스트림이 들어오는 것처럼 처리할 수 있다. At this time, the serial-to-parallel converter 710, the bit stream in the first path in order

It is treated as if it is coming in, and the second path is delayed by 21 samples.

You can treat the stream as if it came in. The serial-to-parallel converter 710 is time delayed by 42 (21 X 2) samples from the first path in the third path.

You can treat the stream as if it came in.

The XOR operator 730 may output the bit values of a stream input in parallel at every instant by performing an XOR operation.

의 승수값이 3만큼 증가하게 되므로, 제로 보간부(750)는 701의 각 값들 사이에 존재하는

의 항들을 703과 같이 인위적으로 삽입하게 된다. 이때, 삽입된

항들의 계수(coefficient)는 제로(zero)('0')로 설정될 수 있다. 제로 보간부(750)가 계수가 제로인 항들을 삽입하는 이유는 다음과 같다. The result of going through the XOR operator 730 is

Since the multiplier value of is increased by 3, the zero interpolation unit 750 exists between each value of 701

The terms of artificially are inserted like 703. At this time, inserted

The coefficient of terms can be set to zero ('0'). The reason why the zero interpolation unit 750 inserts terms with a coefficient of zero is as follows.

을 어떤 다른 다항식

으로 나누었을 때, 나머지(remainder)에 해당하는 다항식

를 구하는 신호 처리는 선형 피드백 쉬프트 레지스터(LFSR)(770)에 의해 쉽게 구할 수 있음이 이미 알려져 있다. Random polynomial in the Galois field

Any other polynomial

Divided by, polynomial corresponding to the remainder

It is already known that signal processing for obtaining can be easily obtained by a linear feedback shift register (LFSR) 770.

의

항의 계수들로 구성된 시퀀스이다. At this time, the sequence applied to the input of the linear feedback shift register (LFSR) 770 (multi-stream) is a polynomial

of

This is a sequence of terms coefficients.

가 변화함에 따라

항의 계수에 해당하는 시퀀스가 중간에 빠짐없이 입력되어야 최종적으로 FF에 저장된 값으로 나머지 다항식(R(a))을 구할 수 있다. 일실시예에서는

항의 계수에 해당하는 시퀀스가 중간에 빠짐없이 입력될 수 있도록, 제로 보간부(750)에 의해 703과 같이 인위적으로 제로(zero)를 계수로 설정한

항들을 삽입할 수 있다. The linear feedback shift register (LFSR) 770 corresponds to a multiplier

As it changes

The sequence corresponding to the coefficient of the term must be entered without fail in the middle to finally obtain the remaining polynomial (R(a)) as the value stored in FF. In one embodiment

The zero interpolation unit 750 artificially sets zero as a coefficient, such as 703, so that a sequence corresponding to the coefficient of the term can be inputted without interruption in the middle.

You can insert terms.

When a polynomial generated from multiple streams with zero values inserted is applied as an input, the linear feedback shift register (LFSR) 770 can obtain S ₃ using the last values stored in FFs.

As described above, the linear feedback shift register (LFSR) 770 divides the input polynomial (the polynomial with zero values) into a primitive polynomial, and then the polynomial information corresponding to the remainder (remainder) ( The coefficient of the polynomial corresponding to the rest can be obtained.

항의 계수에 해당하는 비트 시퀀스이다. 이러한 비트 시퀀스가 모두 입력되고 난 후, 선형 피드백 쉬프트 레지스터(LFSR)(770)에 저장된

번째 FF 값을

라고 하면,

와 같이 구할 수 있다. The value applied to the input of the linear feedback shift register (LFSR) 770 is in the polynomial form.

A bit sequence corresponding to the coefficient of the term. After all of these bit sequences are input, they are stored in the linear feedback shift register (LFSR) 770.

The first FF value

Speaking of,

Can be obtained as

이고,

가 되므로, 선형 피드백 쉬프트 레지스터(LFSR)(770)에서

에 해당하는 라인은 연결되고,

에 해당하는 라인은 연결되지 않는다.
When m=6, the primitive polynomial

ego,

In the linear feedback shift register (LFSR) 770

The line corresponding to is connected,

The line corresponding to is not connected.

So far, the operation of the high-order syndrome calculator in the case of using a binary block code has been described, but the high-order syndrome calculator according to an embodiment is the same for non-binary codes such as, for example, RS codes. Can be utilized. In the case of non-binary code, the only difference is that signal processing is performed in a symbol unit composed of a plurality of (m) bits instead of one bit unit.

For example, in the serial-to-parallel converter 710, a signal is input in units of symbols, and the zero interpolation unit 750 may also insert N zero symbols. At this time, one zero symbol may be composed of m zero bits. Also, symbols composed of m bits may be stored in the FFs included in the linear feedback shift register (LFSR) 770.

A high-order syndrome calculator that calculates syndrome values for bit sequences composed of symbol units will be described with reference to FIG. 8.

8 is a block diagram of a higher-order syndrome calculator according to another embodiment.

Referring to FIG. 8, a structure of a higher-order syndrome calculator for calculating syndrome values for bit sequences composed of symbol units is illustrated.

The higher order syndrome calculator 800 includes a serial-to-parallel converter 810, an XOR operator 830, a zero interpolator 850, and a linear feedback shift register ( Linear Feedback Shift Register (LFSR) 870.

The serial-to-parallel converter 810 may convert serial bit sequences received from a transmitter into multiple parallel streams composed of symbol units. Here, the symbol unit may include a plurality of bits.

The serial-to-parallel converter 810 delays the sequence of bit sequences received from the transmitter by an integer multiple of a specific number of bits (D) that satisfies D = n/j so that the symbol unit x L (natural number with L ≥ 1) bits. Can be converted to multiple streams. Here, n is a block size of a block code that satisfies the symbol unit, j is an order of a syndrome to be obtained, and n/j may be an integer.

When the n/j value is not an integer, the serial-to-parallel converter 810 may transmit the bit sequences received from the transmitter to the zero interpolator 850 without delay.

The XOR operator 830 may perform an XOR operation on a symbol-by-symbol basis for bit values of a parallel multi-stream composed of symbol units.

The zero interpolation unit 850 may insert zero values between each bit of the multi-stream in which the XOR operation is performed in the XOR operator 830. The zero interpolation unit 850 may periodically insert N (N = L-1) zero values in symbol units between each bit of the multi-stream in which the XOR operation is performed.

When the n/j value is not an integer, the zero interpolation unit 850 may periodically insert N (N = j-1) zero values in symbol units between each bit of the multi-stream in which the XOR operation is performed. have.

The linear feedback shift register 870 is ordered by the coefficient of the remainder divided by the polynomial generated from multiple streams in which zero values are inserted in the zero interpolator 850 as a primitive polynomial. The syndrome value can be calculated.

9 is a flowchart illustrating a method for calculating a higher order syndrome according to an embodiment.

Referring to FIG. 9, a high-order syndrome calculator (hereinafter, a calculator) according to an embodiment may convert serial bit sequences received from a transmitter into multiple parallel streams (910).

The calculator may perform an XOR operation on each bit value of the multiple streams converted in step 910 (920).

In operation 920, the calculator may insert zero values between each bit of the multi-stream in which the XOR operation is performed (930).

The calculator may calculate a higher order syndrome value by a coefficient of the remainder divided by a polynomial generated from multiple streams with zero values divided into a primitive polynomial (940).

10 is a flowchart illustrating a high-order syndrome calculation method according to another embodiment.

Referring to FIG. 10, a calculator according to an embodiment may convert serial bit sequences received from a transmitter into multiple streams in parallel composed of symbol units. The symbol unit may include a plurality of bits (1010).

The calculator may perform an XOR operation on the bit values of the multiple streams converted in step 1010 on a symbol basis (1020). Here, the symbol-based XOR operation may also be performed for each bit of the symbol in the same manner as described in FIG. 5.

The calculator may insert zero values between each bit of the multi-stream where the XOR operation is performed (1030).

The calculator may calculate a higher order syndrome value by a coefficient of the remainder divided by a polynomial generated from multiple streams with zero values divided into a primitive polynomial (1040).

11 is a view showing a result of comparing the calculation complexity according to a general syndrome calculation method and a high-order syndrome calculation method according to an embodiment.

Referring to FIG. 11, a result of calculating a syndrome by a general syndrome calculation method and a high-order syndrome calculation method according to an embodiment of a (n,k) linear block code based on the Galois field GF(2 ^m ) is illustrated. do. Here, the relational expression of n = 2 ^m -1 is satisfied.

In FIG. 11, when the syndrome is calculated using the general syndrome calculation method, it can be seen that the number of multiplication operations and modulo operations is n, and the number of registers required to store information and the number of XOR operations are m x n, respectively. In addition, you can see that the general syndrome calculation method also calls the lookup table (LUT) function to retrieve the output value n times.

The high-order syndrome calculation method according to an embodiment does not require a storage space of a register for configuring a lookup table (LUT), and a lookup table (LUT) function call for retrieving an output value is also not required. The high-order syndrome calculation method according to an embodiment only includes m registers for constructing a linear feedback shift register (LFSR) and (L-1) x (n/L) + m'xn (m' is nonzero coefficients of primitive polynomial You only need to perform f(x)-1) XOR operations.

12 is a view showing a result of comparing the calculation complexity of calculating S ₃ by a general syndrome calculation method and a high-order syndrome calculation method according to an embodiment when m=6 and n=2 ^m −1=63.

Referring to FIG. 12, when the syndrome is calculated using the general syndrome calculation method, the number of multiplication operations and modulo operations is 63 times, and the number of registers required to store information and the number of XOR operations are 6 x 63 = You can see that it is 378. In addition, you can see that the general syndrome calculation method also calls the lookup table (LUT) function to retrieve the output value 63 times.

The high-order syndrome calculation method according to an embodiment does not require a storage space of a register for configuring a lookup table (LUT), and a lookup table (LUT) function call for retrieving an output value is also not required. The high-order syndrome calculation method according to an embodiment only needs to perform 6 registers and 42+126=168 XOR operations to construct a linear feedback shift register (LFSR).

The apparatus described above may be implemented with hardware components, software components, and/or combinations of hardware components and software components. For example, the devices and components described in the embodiments include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor (micro signal processor), a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose computers or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may run an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For convenience of understanding, a processing device may be described as one being used, but a person having ordinary skill in the art, the processing device may include a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include. For example, the processing device may include a plurality of processors or a processor and a controller. In addition, other processing configurations, such as parallel processors, are possible.

The software may include a computer program, code, instruction, or a combination of one or more of these, and configure the processing device to operate as desired, or process independently or collectively You can command the device. Software and/or data may be interpreted by a processing device, or to provide instructions or data to a processing device, of any type of machine, component, physical device, virtual equipment, computer storage medium or device. , Or may be permanently or temporarily embodied in the transmitted signal wave. The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, or the like alone or in combination. The program instructions recorded in the medium may be specially designed and configured for the embodiments or may be known and usable by those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs, DVDs, and magnetic media such as floptical disks. -Hardware devices specifically configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language code that can be executed by a computer using an interpreter, etc., as well as machine language codes produced by a compiler. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

As described above, although the embodiments have been described by a limited embodiment and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques are performed in a different order than the described method, and/or the components of the described system, structure, device, circuit, etc. are combined or combined in a different form from the described method, or other components Alternatively, even if replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

500: higher order syndrome calculator
510: serial-to-parallel converter
530: XOR operator
550: zero interpolator
570: Linear Feedback Shift Register (LFSR)

Claims (14)

A serial-to-parallel converter that converts serial bit sequences received from a transmitter into multiple parallel streams;
An XOR operator that performs an XOR operation on each bit value of the multiple streams;
A zero interpolator that inserts zero values between each bit in which the XOR operation is performed; And
A linear feedback shift register that calculates a higher order syndrome value by a coefficient of the remainder divided by a polynomial generated from the multiple streams in which the zero values are inserted is divided into a primitive polynomial. register)
Higher order syndrome calculator, which includes. According to claim 1,
The serial-to-parallel converter,
A high-order syndrome calculator that converts serial bit sequences received from the transmitter into multiple streams of L (L ≥ 1 natural number) bits by delaying by an integer multiple of a certain number of bits (D) satisfying <Equation> below. .
<Mathematics>
D = n/j
(Where n is the block size of the block code, j is the order of the syndrome to obtain, and n/j is an integer) According to claim 2,
The serial-to-parallel converter,
L-1 delay elements,
A high-order syndrome calculator that inputs the bit sequence without delay to the first bit of the multi-stream and delays the bit sequence by (L-1) x D bits to the L-th bit of the multi-stream. According to claim 2,
The serial-to-parallel converter,
When the n/j value is not an integer,
A higher order syndrome calculator that delivers the bit sequences received from the transmitter to the zero interpolator without delay. The method of claim 4,
The zero interpolation unit,
When the n/j value is not an integer,
A high-order syndrome calculator that periodically inserts N (N = j-1) zero values between each bit of the multi-stream in which the XOR operation is performed. According to claim 2,
The zero interpolation unit,
A high-order syndrome calculator that periodically inserts N (N = L-1) zero values between each bit of the multi-stream in which the XOR operation is performed. A serial-to-parallel converter for converting serial bit sequences received from a transmitter into a parallel multiple stream consisting of symbol units, wherein the symbol units include a plurality of bits;
An XOR operator that performs an XOR operation on the bit values of the multiple streams configured in the symbol unit in the symbol unit;
A zero interpolator that inserts zero values between each bit of the multi-stream in which the XOR operation is performed; And
A linear feedback shift register that calculates a higher order syndrome value by a coefficient of the remainder divided by a polynomial generated from the multiple streams in which the zero values are inserted is divided into a primitive polynomial. register)
Higher order syndrome calculator, which includes. The method of claim 7,
The serial-to-parallel converter,
Delay the serial bit sequences received from the transmitter by an integer multiple of a certain number of bits (D) satisfying the following <Equation> to convert into multiple streams of the symbol unit * L (natural number with L ≥ 1) bits , Higher order syndrome calculator.
<Mathematics>
D = n/j
(Where n is the block size of the block code that satisfies the symbol unit, j is the order of the syndrome to obtain, and n/j is an integer) The method of claim 8,
The serial-to-parallel converter,
When the n/j value is not an integer,
A higher order syndrome calculator that delivers the bit sequences received from the transmitter to the zero interpolator without delay. The method of claim 9,
The zero interpolation unit,
When the n/j value is not an integer,
A high-order syndrome calculator that periodically inserts N (N = j-1) zero values in a symbol unit between each bit of the multi-stream in which the XOR operation is performed. The method of claim 8,
The zero interpolation unit,
A high-order syndrome calculator that periodically inserts N (N = L-1) zero values in symbol units between each bit of the multi-stream in which the XOR operation is performed. Converting a series of bit sequences received from a transmitter into multiple streams in parallel;
Performing an XOR operation on each bit value of the multiple streams;
Inserting zero values between each bit of the multi-stream in which the XOR operation is performed; And
Calculating a higher-order syndrome value by a coefficient of the remainder divided by a polynomial generated from the multiple streams in which the zero values are inserted into a primitive polynomial.
A high-order syndrome calculation method comprising a. Converting a series of bit sequences received from a transmitter into a parallel multiple stream consisting of symbol units, wherein the symbol units include a plurality of bits;
Performing an XOR operation in units of the symbols on the bit values of the multiple streams;
Inserting zero values between each bit of the multi-stream in which the XOR operation is performed; And
Calculating a higher-order syndrome value by a coefficient of the remainder divided by a polynomial generated from the multiple streams in which the zero values are inserted into a primitive polynomial.
A high-order syndrome calculation method comprising a. A computer-readable recording medium in which a program for executing the method of any one of claims 12 to 13 is recorded.

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