KR101832243B1 - Photo transistor and manufacturing method thereof - Google Patents

Photo transistor and manufacturing method thereof Download PDF

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KR101832243B1
KR101832243B1 KR1020160035506A KR20160035506A KR101832243B1 KR 101832243 B1 KR101832243 B1 KR 101832243B1 KR 1020160035506 A KR1020160035506 A KR 1020160035506A KR 20160035506 A KR20160035506 A KR 20160035506A KR 101832243 B1 KR101832243 B1 KR 101832243B1
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layer
base
epi
peripheral
emitter
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KR1020160035506A
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Korean (ko)
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KR20170110980A (en
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고성민
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주식회사 피앤엘세미
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Light Receiving Elements (AREA)

Abstract

A phototransistor according to an embodiment of the present invention includes a substrate of a first conductivity type, a first epi layer located on the substrate, a base layer of a second conductivity type located on the first epi layer, A first conductive type surrounding layer surrounding the edge, a first conductive type emitter layer located in a portion of the base layer, a base electrode in contact with the base layer, and an emitter electrode in contact with the emitter layer .

Description

[0001] PHOTO TRANSISTOR AND MANUFACTURING METHOD THEREOF [0002]

The present disclosure relates to a phototransistor and a method of manufacturing the same.

In general, a phototransistor can obtain an output current with the characteristic that light input from the outside is converted into current and amplified. The phototransistor has a lower response speed than the photodiode, but since the input light is amplified and output as a current, it can be used as a light sensor because of its high sensitivity. In addition, the characteristics of the phototransistor device are amplification factor, leakage current, response speed, breakdown voltage, etc., and there are various materials and processing methods to be suitably used in the application field in consideration of each characteristic.

The embodiments are intended to provide a phototransistor with a small scattering of the doping concentration and the base junction depth of the base layer.

A phototransistor according to an embodiment of the present invention includes a substrate of a first conductivity type, a first epi layer located on the substrate, a base layer of a second conductivity type located on the first epi layer, A first conductive type surrounding layer surrounding the edge, a first conductive type emitter layer located in a portion of the base layer, a base electrode in contact with the base layer, and an emitter electrode in contact with the emitter layer .

The doping concentration of the peripheral layer may be lower than the doping concentration of the substrate, and may be lower than the doping concentration of the emitter layer.

The doping concentration of the substrate may be greater than the doping concentration of the emitter layer.

The thickness of the peripheral layer may be equal to the thickness of the base layer.

The thickness of the peripheral layer may be 2 탆 or more and 6 탆 or less.

And a barrier layer of a first conductivity type surrounding the edge of the peripheral layer.

The doping concentration of the blocking layer may be greater than the doping concentration of the peripheral layer.

A method of manufacturing a phototransistor according to an embodiment of the present invention includes: forming a wafer by epitaxially growing a first epitaxial layer on a substrate of a first conductivity type; forming a second conductive type Forming a base layer by doping an impurity of a first conductivity type so as to surround the periphery of the second epi-layer; forming a first conductive type emitter layer on a part of the base layer Forming a base electrode to be in contact with the base layer, forming an emitter electrode to contact the emitter layer, and forming a collector electrode on one side of the wafer to face the base layer with the wafer therebetween, .

The forming of the base layer may include forming a peripheral layer by doping impurities of a first conductivity type so as to surround the periphery of the second epi-layer, and then performing heat treatment.

The perimeter layer may be doped to be less than the doping concentration of the substrate and the emitter layer.

The emitter layer may be doped to have a lower doping concentration than the substrate.

The perimeter layer may be formed to have the same thickness as the base layer.

The perimeter layer may be formed to a thickness of 2 탆 or more and 6 탆 or less.

And forming a barrier layer by doping impurities of the first conductivity type so as to surround the periphery of the peripheral layer.

The blocking layer may be doped to have a higher doping concentration than the peripheral layer.

According to the embodiments, a phototransistor having a small scattering of the doping concentration and the base junction depth of the base layer, a small amount of direct current amplification (hFE) scattering in the wafer, and improved yield can be manufactured.

1 is a plan view of a phototransistor according to an embodiment of the present invention.
2 is a cross-sectional view of the phototransistor of FIG. 1 taken along line II-II '.
FIGS. 3 to 8 sequentially illustrate a method of manufacturing a phototransistor according to an embodiment of the present invention. Referring to FIG.
9 is a cross-sectional view of a phototransistor according to an embodiment of the present invention.
10 is a cross-sectional view of a phototransistor according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

In addition, since the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to those shown in the drawings. In the drawings, the thickness is enlarged to clearly represent the layers and regions. In the drawings, for the convenience of explanation, the thicknesses of some layers and regions are exaggerated.

Also, when a portion such as a layer, a film, an area, a plate, etc. is referred to as being "on" or "on" another portion, this includes not only the case where the other portion is "directly on" . Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, to be "on" or "on" the reference portion is located above or below the reference portion and does not necessarily mean "above" or "above" toward the opposite direction of gravity .

Also, throughout the specification, when an element is referred to as "including" an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise.

Also, in the entire specification, when it is referred to as "planar ", it means that the object portion is viewed from above, and when it is called" sectional image, " this means that the object portion is viewed from the side.

Hereinafter, a phototransistor according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a phototransistor according to an embodiment of the present invention. 2 is a cross-sectional view of the phototransistor of FIG. 1 taken along line II-II '. 1 is shown with the exception of the oxide film 107, the base electrode 160, and the emitter electrode 170 shown in FIG.

A phototransistor according to an embodiment of the present invention includes a wafer 110, a base layer 120, a perimeter layer 130, an emitter layer 140, a base electrode 160, an emitter electrode 170, 180).

Wafer 110 includes a silicon (Si) and arsenic (As) as an n-type impurity such as highly doped (n ++; impurity concentration of 10 18 cm -3 may be greater, particularly 8 × 10 18 cm - 3 be greater than or equal to And a first epitaxial layer of an n-type semiconductor layer grown on the substrate by an epitaxial growth method and having a relatively lower doping concentration than the substrate. The substrate may have a resistance of about 0.001 Ωcm or more and 0.01 Ωcm or less, specifically about 0.002 Ωcm or more and 0.004 Ωcm or less. The first epi layer may have a resistivity of about 20? Cm to 40? Cm, and specifically about 30? Cm. The wafer 110 may be 100 μm or less in thickness. In the present embodiment, the doping concentration and thickness of each layer have been described by way of example, but it is not limited to the disclosed values.

The base layer 120 is located on the wafer 110. The base layer 120 may be a p-type semiconductor layer doped with boron (B) or the like and having a relatively lower doping concentration than the substrate. The resistance of the base layer 120 may be about 0.10? Cm to 0.3? Cm, and the thickness may be about 2 to 6 占 퐉. Specifically about 3 占 퐉 thickness at about 0.15? Cm resistivity, or about 4 占 퐉 thickness at about 0.2? Cm resistance and about 5 占 퐉 thickness at about 0.25? Cm resistance. The base layer 120 may be in the form of being surrounded by the perimeter layer 130.

The perimeter layer 130 may be positioned to surround the edge of the base layer 120. The peripheral layer 130 may be doped with n-type impurities such as arsenic (As), phosphorus (P), or the like (impurity concentration may be 10 13 cm -3 or more and 10 15 cm -3 or less). The peripheral layer 130 may have a lower doping concentration than the substrate and the emitter layer 140 described below. The thickness of the peripheral layer 130 may be about 2 袖 m or more and 6 袖 m or less and may be the same as the thickness of the base layer 120.

The emitter layer 140 may be located in a portion of the base layer 120. The emitter layer 140 may be doped with an n-type impurity. The emitter layer 140 has a lower doping concentration than the substrate and may have a higher doping concentration than the peripheral layer 130. The emitter layer 140 may be surrounded by the base layer 120.

The barrier layer 150 may be located on a part of the peripheral layer 130. The blocking layer 150 may be doped with an n-type impurity. The blocking layer 150 may have a lower doping concentration than the substrate and a higher doping concentration than the peripheral layer 130. The barrier layer 150 may be positioned to surround the periphery of the perimeter layer 130.

An oxide film 107 may be disposed on the base layer 120 and the peripheral layer 130. A base electrode 160 connected to the base layer 120 and an emitter layer 140 connected to the emitter layer 140 may be formed on the oxide layer 107. [ The electrode 170 is positioned. The base electrode 160 and the emitter electrode 170 may comprise aluminum (Al).

The collector electrode 180 is positioned on the lower surface of the wafer 110 so as to face the base layer 120 with the wafer 110 therebetween. The collector electrode 180 may comprise gold (Au).

Hereinafter, a method of manufacturing a phototransistor according to an embodiment of the present invention will be described with reference to FIGS. 2 to 8. FIG. FIGS. 3 to 8 sequentially illustrate a method of manufacturing a phototransistor according to an embodiment of the present invention. Referring to FIG.

A method of manufacturing a phototransistor of the present invention includes: growing a first epitaxial layer on a substrate to form a wafer; Growing a second epilayer on the wafer; Doping an impurity around the second epi-layer to form a base layer; Forming an emitter layer in the base layer; Forming a base electrode in contact with the base layer; Forming an emitter electrode in contact with the emitter layer; And forming a collector electrode on one side of the wafer so as to face the base layer with the wafer sandwiched therebetween.

Referring to FIG. 3, after a substrate 100 is prepared, a first epitaxial layer 101 is formed on a substrate 100 to form a wafer 110. The substrate 100 may comprise silicon (Si), arsenic (As) highly doped (n ++ to the n-type impurity such as; impurity concentration may -3 greater than 10 18 cm, specifically, 8 × 10 18 cm - 3 or more). The substrate 100 may have a resistance of not less than about 0.001? Cm and not more than 0.01? Cm, and specifically about 0.002? Cm and not more than 0.004? Cm. The thickness of the substrate 100 may be 600 μm or more and 700 μm or less, specifically, 625 μm. In preparing the substrate 100, the doping concentration and the thickness of the epitaxial layer to be grown on the substrate can be adjusted in consideration of the wavelength of the light to be applied to the phototransistor and the intended use thereof. . In the present embodiment, the doping concentration and thickness of each layer have been described by way of example, but it is not limited to the disclosed values.

The first epitaxial layer 101 is formed by an epitaxial growth method. Epitaxial growth methods include liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), and molecular beam epitaxy (MBE). Do not. The growth source may be varied depending on the material and the type of the substrate 100, and a solid-phase, liquid, or gaseous material including a compound having a lattice constant equal to or similar to that of the substrate 100 may be used as a growth source. The doping source may comprise a Group 5 compound semiconductor material such as nitrogen gas (N2) for n-type doping. The first epi layer 101 may be an n-type semiconductor layer having a relatively lower doping concentration than the substrate 100. The first epi layer 101 may have a resistivity of about 20? Cm to 40? Cm, and specifically about 30? Cm. The thickness of the first epi layer 101 may be 20 μm or more and 40 μm or less, specifically about 30 μm.

A second epi layer 102 is formed on the first epi layer 101. [ The second epi-layer 102 is also formed by an epitaxial growth method. The second epi layer 102 may be grown in a continuous process with the first epi layer 101. The doping source may comprise a Group 3 compound semiconductor material such as boron (B) for p-type doping. The second epi layer 102 may be a p-type semiconductor layer doped with boron (B) or the like and having a relatively lower doping concentration than the substrate 100. The resistance of the second epi layer 102 may be about 0.10? Cm to 0.3? Cm, and the thickness may be about 2 to 6 占 퐉. Specifically, it may be formed to a thickness of about 3 占 퐉 at a resistivity of about 0.15? Cm, or may be formed to a thickness of about 4 占 퐉 at a resistivity of about 0.2 占 ㎝ m and may be formed to a thickness of about 5 占 퐉 at a resistivity of about 0.25? have.

An oxide film 105 is formed on the second epi-layer 102. The oxide film 105 may include silicon oxide (SiO2).

4, a photoresist film (not shown) is formed on the oxide film 105 to define the periphery of the second epi-layer 102, thereby forming a second epi-layer (not shown) of the oxide film 105 102 are removed. The oxide film 105 is removed and the peripheral portion surface of the second epi-layer 102 is exposed.

Referring to FIG. 5, the oxide layer 105 is removed to form a peripheral layer 130 at the periphery of the second epi-layer 102 where the surface is exposed. The peripheral layer 130 may be formed by doping n-type impurities such as arsenic (As), phosphorus (P), etc. (n +; impurity concentration may be 10 13 cm -3 or more and 10 15 cm -3 or less). Diffusion or ion implantation processes may be used for doping the impurities. The perimeter layer 130 may be formed on a portion of the second epi-layer 102 and may surround the edge of the second epi-layer 102. The thickness of the peripheral layer 130 may be about 2 袖 m or more and 6 袖 m or less and may be the same as the thickness of the second epi-layer 102. After the peripheral layer 130 is formed by doping impurities, the photoresist layer is removed, and then the heat treatment is performed to complete the base layer 120. The base layer 120 may be in the form of being surrounded by the perimeter layer 130. An oxide film is formed during the heat treatment process. The doping concentration of the peripheral layer 130 may be lower than that of the substrate 100 and the emitter layer 140 described later. In the case of forming the base layer 120 by this method, unlike the case of forming the base layer by directly doping the p-type impurity, the doping concentration of the base layer and the base concentration of the impurity source are not influenced by the diffusion temperature or the concentration of the impurity source. So that the variation of the junction depth is small and uniform. Accordingly, the scattering of the direct current amplification factor (hFE) in the wafer 110 is small, and the yield is improved and the cost can be reduced.

Referring to FIG. 6, a base layer 120 is formed, and then a photoresist layer (not shown) is formed on the oxide layer 106 to define an emitter shape and a barrier layer shape. Next, the oxide film 106 corresponding to the emitter shape and the barrier layer shape is removed through the etching process. After the oxide film 106 is removed to implant the n-type impurity into the exposed portions of the surfaces of the second epi layer 102 and the peripheral layer 130, the photoresist film is removed and heat treatment is performed, (150). The emitter layer 140 may be formed on a portion of the base layer 120 and the blocking layer 150 may be formed on a portion of the peripheral layer 130. The barrier layer 150 may be formed to surround the periphery of the peripheral layer 130. The emitter layer 140 and the blocking layer 150 may have a lower doping concentration than the substrate 100 and a higher doping concentration than the peripheral layer 130. An oxide film is formed during the heat treatment process. Since the blocking layer 150 is formed on the edge of the base layer 120 along the circumferential direction of the device, the region where the depletion layer is generated in the wafer cut surface during device operation can be minimized. Although the emitter layer 140 and the blocking layer 150 are formed at the same time in this embodiment, the emitter layer 140 and the blocking layer 150 may be formed separately.

Referring to FIG. 7, a photoresist layer (not shown) is formed on the oxide layer 107 to remove a portion of the oxide layer 107 corresponding to a space in which the base electrode and the emitter electrode are formed. After the photoresist film (not shown) is removed, a metal film is deposited, and then a base electrode 160 connected to the base layer 120 and an emitter electrode 170 connected to the emitter layer 140 are formed through a photo transfer operation. The base electrode 160 and the emitter electrode 170 may comprise aluminum (Al).

Then, as shown in Fig. 8, the area under the wafer 110 is trimmed to a predetermined thickness. The shaved wafer 110 may have a thickness of 100 μm or less. Next, as shown in FIG. 2, a metal is deposited on the lower surface of the wafer 110 to form a collector electrode 180. The collector electrode 180 may comprise gold (Au).

According to the method of manufacturing a phototransistor according to an embodiment of the present invention, it is possible to form a wafer with a small scattering of the direct current amplification factor (hFE), so that a diameter of 8 inches or more, It has good concentration and thickness control and high process stability. Furthermore, since a substrate having a high doping concentration of impurities is used, it is possible to maintain an ohmic contact even if the wafer thickness is adjusted to be thin, and thus the wafer can be adjusted to a thickness of 100 μm or less. Since the thickness of the wafer can be freely adjusted, the degree of freedom of the packaging process is increased. Further, since the base layer is formed by doping the p-type semiconductor layer grown by the epitaxial method with the n-type impurity, the doping depth distribution of the p-type impurity in the base layer is stabilized at 3% to 5%, and the direct current The amplification factor (hFE) dispersion is uniform, thereby improving the yield and reducing the cost.

In this embodiment, a method of manufacturing a phototransistor is described as an example. However, the present invention is not limited thereto, and general transistors can be manufactured through the same process by varying the concentration and thickness of the first epi layer and the concentration and thickness of the second epi layer .

Hereinafter, a phototransistor according to an embodiment of the present invention will be described with reference to FIG. 9 is a cross-sectional view of a phototransistor according to an embodiment of the present invention. Description of the same components as those of the embodiment described above with reference to Figs. 1 and 2 is omitted.

The phototransistor according to an embodiment of the present invention includes a wafer 111, a base layer 121, a peripheral layer 131, an emitter layer 141, a base electrode 161, an emitter electrode 171, and a collector electrode 181).

Wafer 111 comprises silicon (Si) and boron (B) highly doped (p ++ to the p-type impurity such as; the impurity concentration may be 10 18 cm -3 or more, particularly 8 × 10 18 cm - 3 be greater than or equal to And a first epitaxial layer which is a p-type semiconductor layer having a relatively lower doping concentration than the substrate grown on the substrate by an epitaxial growth method. The wafer 111 may have a thickness of 100 m or less.

On the wafer 111, a base layer 121 is located. The base layer 121 may be an n-type semiconductor layer doped with arsenic (As) or the like and having a relatively lower doping concentration than the substrate. The thickness of the base layer 121 may be about 2 탆 or more and 6 탆 or less. The base layer 121 may be surrounded by the peripheral layer 131. The base layer 121 is formed by growing a second epitaxial layer which is an n-type semiconductor layer by epitaxial growth on the wafer 111, forming a peripheral layer 131 by doping a p-type impurity around the second epitaxial layer, . ≪ / RTI >

The perimeter layer 131 may be positioned to surround the edge of the base layer 121. The peripheral layer 131 may be doped with a p-type impurity such as boron (B) (p +; impurity concentration may be 10 13 cm -3 or more and 10 15 cm -3 or less). The peripheral layer 131 may have a lower doping concentration than the substrate and the emitter layer 141 described later. The thickness of the peripheral layer 131 may be about 2 탆 or more and 6 탆 or less, and may be the same as the thickness of the base layer 121.

The emitter layer 141 may be located in a part of the base layer 121. The emitter layer 141 may be doped with a p-type impurity. The emitter layer 141 has a lower doping concentration than the substrate and may have a higher doping concentration than the peripheral layer 131. The emitter layer 141 may be surrounded by the base layer 121.

The blocking layer 151 may be located in a part of the peripheral layer 131. The blocking layer 151 may be doped with a p-type impurity. The blocking layer 151 has a lower doping concentration than the substrate and may have a higher doping concentration than the peripheral layer 131. The barrier layer 151 may surround the periphery of the peripheral layer 131.

An oxide film 107 is disposed on the base layer 121 and the peripheral layer 131. A base electrode 160 connected to the base layer 121 and an emitter electrode 170). A collector electrode 180 is disposed on the lower surface of the wafer 111 so as to face the base layer 121 with the wafer 111 interposed therebetween.

Hereinafter, a phototransistor according to an embodiment of the present invention will be described with reference to FIG. 10 is a cross-sectional view of a phototransistor according to an embodiment of the present invention. Description of the same components as those of the embodiment described above with reference to Figs. 1 and 2 is omitted.

A phototransistor according to an embodiment of the present invention includes a wafer 110, a base layer 120, a perimeter layer 130, an emitter layer 140, a base electrode 160, an emitter electrode 170, 180).

A base layer 120 is positioned on the wafer 110 and a perimeter layer 130 is positioned around the base layer 120. The base layer is again located around the circumferential layer 130. That is, the base layer 120 is formed by epitaxially growing a second epitaxial layer, which is a p-type semiconductor layer, on the wafer 110, and then forming a peripheral layer 130 by doping n-type impurities around the second epitaxial layer When the n-type impurity is doped in the second epi layer, the entirety of the edge of the second epi layer is not doped, but only the peripheral portion of the second epi layer is doped to form the peripheral layer 130 It is also possible to do. When the peripheral layer 130 is formed not only to surround the entire edge of the second epilayer but only to the middle of the edge, the peripheral layer 130 is located around the base layer 120, 10 in which the base layer is located again.

A base electrode 120 is connected to the emitter layer 140 and a base electrode 160 is connected to the base layer 120. The emitter electrode 170 is connected to the base layer 120, Located. The collector electrode 180 is positioned on the lower surface of the wafer 110 so as to face the base layer 120 with the wafer 110 therebetween.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

100: substrate
101: first epilayer
110: wafer
102: second epilayer
120: base layer
130: perimeter layer
140:
150: blocking layer
160: Base electrode
170: emitter electrode

Claims (15)

delete delete delete delete delete delete delete Growing a first epitaxial layer as an n-type semiconductor layer by epitaxial growth on a substrate of a first conductivity type to form a wafer;
Growing a second epitaxial layer of a second conductivity type by epitaxial growth on the wafer;
Forming an oxide film on the second epilayer;
Removing the portion of the oxide film corresponding to the periphery of the second epi-layer to reveal the peripheral surface of the second epi-layer;
The oxide film is removed so as to surround the periphery of the second epi-layer, and the impurity of the first conductivity type is diffused or ion implanted into the peripheral portion of the second epi-layer where the surface is exposed to form a peripheral layer on the first epi- step;
Heat treating the second epi layer to form a base layer surrounded by the peripheral layer;
Forming an emitter layer of a first conductivity type on a portion of the base layer;
Forming a base electrode in contact with the base layer;
Forming an emitter electrode in contact with the emitter layer; And
And forming a collector electrode on one side of the wafer so as to face the base layer with the wafer therebetween,
Wherein the perimeter layer is formed on a portion of the second epi layer. delete 9. The method of claim 8,
Wherein the perimeter layer is doped to be lower than the doping concentration of the substrate and the emitter layer. 11. The method of claim 10,
Wherein the emitter layer is doped to have a lower doping concentration than the substrate. 12. The method of claim 11,
Wherein the peripheral layer is formed to have the same thickness as the base layer. The method of claim 12,
Wherein the peripheral layer is formed to a thickness of 2 占 퐉 or more and 6 占 퐉 or less. The method of claim 12,
And forming a blocking layer by doping an impurity of the first conductivity type so as to surround the periphery of the peripheral layer. The method of claim 14,
Wherein the barrier layer is doped to have a higher doping concentration than the peripheral layer.
KR1020160035506A 2016-03-24 2016-03-24 Photo transistor and manufacturing method thereof KR101832243B1 (en)

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