KR101815704B1 - Gate selection circuit of liquid crystal panel, accumulating capacity driving circuit, driving device, and driving method - Google Patents

Abstract

In the gate selection circuit of the active matrix type liquid crystal panel, the circuit scale is reduced.
A plurality of clock signals Ck1, Ck2, Ck3 and Ck4 are generated by the clock generating circuit 110, a shift register is constituted by a plurality of latch circuits LA1 (LA11 to LA1n), an enable clock signal 1, the enable 2) are shifted.
The switch circuits SW1 (SW11 to SW1m) sequentially output the plurality of clock signals Ck1, Ck2, Ck3, and Ck4 as gate selection signals in accordance with the output signals of the latch circuits LA1 (LA11 to LA1n).

Description

TECHNICAL FIELD [0001] The present invention relates to a gate selection circuit, a storage capacitor driving circuit, a driving device, and a driving method for a liquid crystal panel,

A storage capacitor driving circuit, a driving device, and a driving method of an active matrix type liquid crystal panel.

As shown in FIG. 16, the conventional gate selection circuit 201 is constituted by a shift register circuit composed of a plurality of latch circuits (LA1,...), And the clock signals (Clock1, Clock2) As shown in FIG.

The gate selection signals (Gate <1> to Gate <m>) are generated from the outputs (Q1 to Qm) of each of the plurality of latch circuits LA1 '.

On the other hand, the latch circuit LA1 is constituted by two clock inverter circuits (CINVa and CINVb) and one inverter (inverter) circuit INVa as shown in Fig. 20 (A) .

In this way, in the gate selection circuit 201, one latch circuit (LA1) is required for one gate selection circuit output (one output signal of the gate selection signals (Gate <1> to Gate <m> In addition, a control signal for operating the latch circuit LA1 is required.

On the other hand, the latch circuit shown in Fig. 20A is called a latch circuit in general, and the latch circuit composed of the two inverter circuits INVc and INVd shown in Fig. 20B is called a bus type latch circuit.

Then, the conventional storage capacitor driving circuit 202 includes a plurality of latch circuits LA1 (see FIG. 20 (A)) as in the gate selection circuit 201, as shown in FIG. And the clock signals (Clock 1, Clock 2) can be used as the clock signal of the normal latch circuit (LA1). The storage capacitor driving signals C <1> to C <m> are generated from the latch circuit output.

In this manner, in the storage capacitor driving circuit 202, as in the case of the gate selection circuit 201, one storage capacitor driving circuit output (one output signal among the storage capacitor driving signals C <1> to C <m>) , Each one latch circuit (LA1) is required, and a control signal for operating the latch circuit (LA1) is required.

18 shows an example of the overall configuration of the driving apparatus for driving the liquid crystal panel by the gate selection circuit 201 and the storage capacitance driving circuit 202 using such a conventional technique. An example of the drive waveform is shown in Fig.

18, the liquid crystal panel 1 includes a plurality of gate lines GL formed by arranging a plurality of electrodes in a horizontal direction and a plurality of gate electrodes GL formed by arranging a plurality of electrodes in the same horizontal direction A storage capacitor line CL and a source line SL formed by arranging a plurality of electrodes in the vertical direction.

Pixels made up of a TFT (thin film transistor) switch, a liquid crystal capacitor LC and a storage capacitor CS are formed at each intersection of the gate line GL and the source line SL.

The liquid crystal panel 1 is further provided with a gate selection circuit 201 for driving the plurality of gate lines GL, a storage capacitor drive circuit 202 for driving the plurality of storage capacitor lines, And a source driving circuit 203 for driving the electrodes are connected.

The gate selection circuit 201 sequentially selects pixel TFTs (thin film transistors) connected to the gate line GL in one scanning period and simultaneously supplies a desired data voltage from the source driving circuit 203 to the liquid crystal capacitance LC ).

Further, after the data voltage is written, the data written in the liquid crystal capacitor LC is converted into a voltage suitable for the optical characteristics of the actual liquid crystal by superimposing the predetermined voltage from the storage capacitor driving circuit 202, do.

On the other hand, Japanese Unexamined Patent Application Publication No. 2009-223051 discloses a display apparatus and a method of driving the display apparatus.

This display device is intended to realize a display device capable of relieving the high-density arrangement of the shift register circuits. To this end, the density of the circuit is reduced by disposing gate circuits on both sides of the panel.

The output of the SR at one end of the panel among the SRs (shift register circuits) constituting the gate circuit is transferred to the scan electrodes of the panel display area and used as the input at the one end SR, SR.

As described above, in the conventional gate circuit, one latch circuit is required for each output of one gate selection circuit.

Also in the conventional storage capacitor driving circuit, one latch circuit is required for each output of one storage capacitor driving circuit. In addition, since a control signal for driving the latch circuit is also required, an increase in the total number of circuits can not be avoided when applied to a panel. As a result, an increase in panel area is a concern.

In order to meet the demand for reduction of the panel area, there is a need for a means capable of reducing the overall number of circuits while maintaining the functions as in the past.

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and an object of the present invention is to reduce a circuit scale in a gate selection circuit of an active matrix type liquid crystal panel.

Another object of the present invention is to provide a driving apparatus for a liquid crystal panel capable of reducing the size of the storage capacitor driving circuit and reducing the overall circuit area.

According to an aspect of the present invention, there is provided a liquid crystal display device including a plurality of gate lines and a plurality of storage capacitor driving lines arranged in a horizontal direction and a plurality of source lines arranged in a vertical direction, A gate selection circuit for driving an active matrix type liquid crystal panel formed by arranging pixels having storage capacitances in a matrix form, the gate selection circuit comprising: a plurality of gate selection circuits for generating a predetermined horizontal synchronization signal synchronized with an image signal to be displayed on the liquid crystal panel A clock generating circuit which generates an enable clock signal, a predetermined vertical synchronizing clock signal, and a plurality of clock signals generated from the enable clock signal and possesses different phases, a shift register which is connected in series to form a shift register, A plurality of synchronizing clocks for synchronizing with the enable clock signal, And a second latch circuit which is provided in correspondence with the gate line and supplies the clock signal to each of the gate lines as a gate selection signal to the pixel, And a first switch circuit for sequentially outputting a selection signal.

With this configuration, a plurality of clock signals are generated by the clock generation circuit.

A shift register is constituted by a plurality of latch circuits, and information held in synchronization with the enable clock signal is shifted.

The switch circuit follows the output signal of the latch circuit and sequentially outputs each of the plurality of clock signals as a gate selection signal.

Thus, the circuit scale of the gate selection circuit as a whole can be reduced, and the circuit area can be reduced.

The gate selection circuit of the present invention is configured such that a plurality of clock signals generated by the clock generation circuit are sequentially output as a gate selection signal to the switch circuit in accordance with the output signal to the latch circuit, There is an effect that a gate selection circuit can be provided.

1 is a diagram showing a configuration of a gate selection circuit according to a first embodiment of the present invention.
2 is a diagram showing the configuration of the storage capacitor driving circuit according to the first embodiment.
3 is a diagram showing the relationship between the gate selection circuit and the storage capacitor driving circuit of the present invention.
4 is a diagram showing the operation of the gate selection circuit according to the first embodiment of the present invention.
5 is a diagram showing the operation of the storage capacitor driving circuit according to the first embodiment of the present invention.
6 is a diagram showing a configuration of a driving apparatus for a liquid crystal panel according to a second embodiment of the present invention.
7 is a diagram showing the operation of the gate selection circuit and the storage capacitor driving circuit according to the second embodiment of the present invention.
8 is a diagram showing a configuration of a driving apparatus for a liquid crystal panel according to a third embodiment of the present invention.
9 is a diagram showing an example of a clock signal conversion circuit.
10 is a diagram showing the operation of the gate selection circuit and the storage capacitor driving circuit according to the third embodiment of the present invention.
11 is a diagram showing a configuration of a driving apparatus for a liquid crystal panel according to a fourth embodiment of the present invention.
12 is a timing chart showing the operation of the fourth embodiment of the present invention.
13 is a diagram showing a configuration of a clock generation circuit for generating a control signal of the gate selection circuit.
14 is a diagram showing an operation waveform of the clock generation circuit shown in FIG.
15 is a diagram showing a configuration example of a liquid crystal display apparatus using the liquid crystal panel driving apparatus of the present invention.
16 is a diagram showing a configuration of a conventional gate selection circuit.
17 is a diagram showing a configuration of a conventional storage capacitor driving circuit.
18 is a diagram showing a configuration of a driving apparatus for a liquid crystal panel including a gate selection circuit and a storage capacitor driving circuit using a conventional technique.
Fig. 19 is a diagram showing an example of a driving waveform in the driving apparatus shown in Fig.
20 is a diagram showing a configuration of a latch circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention in the drawings, parts not related to the description are omitted. Like numbers refer to like parts throughout the specification.

 [First Embodiment]

(Gate selection circuit)

Fig. 1 shows a configuration of a gate selection circuit according to the first embodiment of the present invention.

The gate selection circuit 11 shown in Fig. 1 includes a latch circuit LA1 formed by serially connecting a plurality of latch circuits LA11 to LA1m, a switch circuit SW1 for selecting a desired gate signal from a four-phase clock signal, And a buffer circuit BA1 for outputting each gate selection signal (gate output).

The enable clock signals (enable 1 and enable 2), the clock signals Ck1, Ck2, Ck3 and Ck4 and the data signal Gdata supplied to the gate selection circuit 11 are supplied from the signal control circuit portion 101 .

On the other hand, the signal control circuit portion 101 will be described later with reference to Fig.

1, the latch circuit LA1 includes a plurality of latch circuits LA11 to LA1n connected in series, and the data signal Gdata input to the latch circuit LA11 at the first stage is connected to the enable clock Q2, Q3, ..., Qn, which are sequentially shifted by a signal (enable 1, enable 2).

On the other hand, among the plurality of output signals Q1, Q2, Q3, ..., Qn, odd-numbered output signals Q1, Q3, Q5, ... are output to the switch circuit SW1.

This is because each of the plurality of latch circuits LA11 to LA1n is a half latch circuit and two latch circuits are required for the four-phase clock signal since the four latch circuits Ck1, Ck2, Ck3, and Ck4 are timed with respect to the four- . Each of the plurality of latch circuits LA11 to LA1n is a normal latch circuit shown in Fig. 20 (A).

Each of the switch circuits SW11 to SW1m in the switch circuit SW1 is constituted by a MOS transistor and corresponds to each of the four-phase clock signals Ck1, Ck2, Ck3, and Ck4. The four switch circuits are divided into one unit to constitute the switch circuit SW1.

For example, the switch circuits SW11 to SW14 are one unit, the gates of the switch circuits SW11 to SW14 are connected in common, and the output signal Q1 of the latch circuit LA11 is input to the commonly connected gates do.

The clock signal Ck1 is input to the drain of the switch circuit SW11 and the signal output to the source becomes the input of the buffer circuit BA11 and is output as the gate selection signal Gate <1>.

The clock signal Ck2 is input to the drain of the switch circuit SW12 and the signal output to the source becomes the input of the buffer circuit BA12 and is output as the gate selection signal Gate <2>.

The clock signal Ck3 is input to the drain of the switch circuit SW13 and the signal output to the source becomes the input of the buffer circuit BA13 and is output as the gate selection signal Gate <3>.

The clock signal Ck4 is input to the drain of the switch circuit SW14 and the signal output to the source becomes the input of the buffer circuit BA14 and is output as the gate selection signal Gate <4>.

In the same manner, the switch circuits SW15 to SW18 are one unit, the gates of the switch circuits SW15 to SW18 are connected in common, and the output signal Q3 of the latch circuit LA13 is input to the commonly connected gates do.

The clock signal Ck1 is input to the drain of the switch circuit SW15 and the signal output to the source becomes the input of the buffer circuit BA15 and is output as the gate selection signal Gate <5>. Hereinafter, it is the same as the above description.

The outputs of the buffer circuits BA11 to BA1m are connected to the gate line output terminals Gate <1>, Gate <2>, Gate <3>, Gate <4>, ... Gate <m> When the gate line of the liquid crystal panel is m, the required gate output is also m.

Next, the configuration and operation of the clock generation circuit for generating the control signal of the gate selection circuit 11 shown in FIG. 1 are shown in FIG. 13 and FIG.

The clock generating circuit generates the enable clock signals (enable 1, enable 2) and the four-phase clock signals Ck1, Ck2, Ck3, Ck4 of the gate selecting circuit shown in Fig. 13A includes a frequency divider circuit 111 shown in FIG. 13A, an enable clock signal generator circuit 112 shown in FIG. 13B, and a four-phase clock generator circuit 113 shown in FIG. 13C.

The frequency divider circuit 111 shown in Fig. 13A is controlled by a horizontal synchronizing signal 1H and a horizontal synchronizing signal 1Hb which is logically inverted by the inverter circuit INV1.

In this frequency divider circuit 111, the clock inverter circuit CINV1, the inverter circuit INV2 and the clock inverter circuit CINV2 are cascade-connected and the output side of the clock inverter circuit CINV2 is connected to the clock inverter circuit CINV1 And is connected to the input side.

The output signal of the clock inverter circuit CINV2 becomes the input signal of one input terminal of the NAND circuit NAND1 and the other input terminal of the NAND circuit NAND1 is supplied with the start and stop of the frequency dividing circuit The signal RES to be controlled is inputted.

The clock inverter circuit CINV4 is connected between the output side of the NAND circuit NAND1 and one input side. A signal (frequency 1/2) that is divided by 2 (frequency is 1/2) of the frequency of the horizontal synchronizing signal 1H due to the input of the horizontal synchronizing signal 1H to the inverter circuit INV1 and the signal RES to the H level A) is obtained.

This signal A is input to the enable clock signal generation circuit 112 shown in Fig. 13 (B).

In the enable clock signal generation circuit 112 shown in Fig. 13B, four inverter circuits INV3, INV3a, INV3b and INV3c are connected in series, and two inverter circuits INV3a, INV3b and INV3c are connected to the output side of the inverter circuit INV3. (INV3d, INV3d) are connected in series.

The signal B outputted from the inverter circuit INV3 is outputted from the inverter circuit INV3c by inputting the signal A outputted from the frequency divider circuit 111 to the enable clock signal generation circuit 112, A signal (enable 1) is outputted, and an enable clock signal (enable 2) is outputted from the inverter circuit INV3e.

This enable clock signal (enable 1, enable 2) becomes the enable clock signal (enable 1, enable 2) of the gate selecting circuit 11 shown in Fig. On the other hand, the signal B is an inverted signal of the signal A. [

The signal A and the signal B are supplied to the NAND circuits NAND2 to NAND5 of the four-phase clock generation circuit 113 shown in Fig. 13C together with the vertical clock signals CKV1 and CKV2 Respectively.

The signal A and the vertical clock signal CKV1 are input to the NAND circuit NAND2 and the clock signal Ck1 is obtained through the inverter circuits INV4a, 4b and 4c.

The signal A and the vertical clock signal CKV2 are inputted to the NAND circuit NAND3 and the clock signal Ck2 is obtained through the inverter circuits INV5a, 5b and 5c.

The clock signal Ck3 is obtained through the inverter circuits INV6a, INb6b, and INc6, and the NAND circuit NAND4 receives the signal B and the vertical clock signal CKV1.

The clock signal Ck4 is obtained through the inverter circuits INV7a, 7b and 7c, and the NAND circuit (NAND5) receives the signal B and the vertical clock signal CKV2.

In this manner, the four-phase clock signals Ck1, Ck2, Ck3, and Ck4 can be obtained.

Fig. 14 shows a specific operation timing.

In the timing chart shown in Fig. 14, the horizontal synchronizing signal 1H, the clock signal Clock1, the vertical clock signal CKV1, the clock signal Clock2, the vertical clock signal CKV2, the enable clock signal , Enable 2), a four-phase clock Ck1 / Ck2 / Ck3 / Ck4, and a frequency divider circuit control signal RES.

As shown in Fig. 14, when the signal RES at the lowermost end becomes the H level of the high level, the dividing circuit starts to operate, and by the horizontal synchronizing signal 1H and the vertical clock signals CKV1 and CKV2 , Four-phase clocks Ck1, Ck2, Ck3, and Ck4 are generated.

Now, the storage capacitor driving circuit 12 according to the first embodiment of the present invention will be described.

2 is a diagram showing the storage capacitor driving circuit 12 according to the first embodiment of the present invention.

As shown in Fig. 2, the storage capacitor driving circuit of the present invention includes a latch circuit LA2 including a plurality of latch circuits LA2n + 2 to LA2n + 9, a storage capacitor drive data signal A switch circuit SW2 including a plurality of switch circuits SW2n + 2 to SWn + 9 for selecting one of the plurality of storage capacitors Cdata, and a plurality of buffer circuits (BAn to Ben + 7) Lt; RTI ID = 0.0 &gt; BA2. &Lt; / RTI &gt;

On the other hand, "n" represents an n-th gate line (vertical direction: Y). For example, "n + 2" indicates an n + 2-th gate line in the vertical direction.

As shown in Fig. 2, each of the switch circuits SW2n + 2 to SW2n + 9 is formed of a MOS transistor, and gate selection signals Gate <n + 2> Gate < n + 3 >, ..., Gate < n + 9 >

The respective drains of the respective switch circuits SW2n + 2 to SW2n + 9 are connected in common, and the data signal Cdata is input to the commonly connected drains.

The sources of the respective switch circuits SW2n + 2 to SW2n + 9 are connected to the data input sides of the latch circuits LA2 (LA2n + 2 to LA2n + 9), respectively.

Each of the data output sides of the latch circuits LA2 (LA2n + 2 to LA2n + 9) is connected to the input side of the buffer circuit BA2 (BA2n to BA2n + 7), and each of the buffer circuits BA2 The output side of the storage capacitor line output terminal C <n>, C <n + 1>, ... , And C < n + 7 >.

When the storage capacitor line of the liquid crystal panel is m, the required storage capacity output is m.

2, since the driving timing between the gate line GL and the storage capacitor line CL of the actual liquid crystal panel is matched, the vertical address of the gate line GL and the vertical address of the storage capacitor line CL And the vertical direction address of the first line.

Therefore, the storage capacitor driving signal C <n> and the driving signal of the n-th source line SL are driven by the gate selection signal Gate <n + 2> and the (n + Is generated.

The number of stages of the inverters constituting each of the buffer circuits BA2n to BA2n + 7 in the buffer circuit BA2 is three for the buffer circuit BA2n and two for the BA2n + 1. Thus, the output signals are alternately generated at different signal levels.

The inverter, which is the final output buffer circuit for each of the plurality of buffer circuits BA2n to BA2n + 7, is driven by power supplies V1 and V2 that can be voltage-adjusted (image contrast can be adjusted).

In addition, the number of inverter connection stages of each of the plurality of buffer circuits BA2n to BA2n + 7 is alternately configured in two or three stages.

The plurality of latch circuits LA2n + 2 to LA2n + 9 are formed by a bus-type latch circuit.

20 shows a configuration example of a normal latch circuit and a bus type latch circuit.

In the normal latch circuit shown in Fig. 20A, two clock inverter circuits (CINVa and CINVb) and one inverter circuit (INVa) are provided, and ten transistors are required as the number of elements.

In contrast, in the bus-type latch circuit, two inverter circuits INVc and INVd are connected in opposite parallel connection. Since the number of elements is realized by four transistors, it is possible to reduce the number of six transistors in the latch circuit portion.

Next, the overall configuration of the gate selection circuit and the storage capacitor driving circuit in the first embodiment of the present invention will be described.

3 is a diagram showing the relationship between the gate selection circuit and the storage capacitor driving circuit of the present invention and showing the relationship between the gate selection circuit disposed on the left side of the liquid crystal panel (screen) and the storage capacitor driving circuit disposed on the right side of the screen to be.

3, the gate selection signal generated by the gate selection circuit 11 passes on the gate line GL of the liquid crystal panel and is supplied to the switch circuit SW2 of the storage capacitor driving circuit 12 Respectively.

In the storage capacitor driving circuit 12, the storage capacitor driving data is set in the latch circuit LA2 at the timing when the gate output (gate selection signal) becomes H level, and the data set in the latch circuit LA2 is supplied to the buffer circuit BA2 And is output as a storage capacitance circuit output.

In this case, as shown in Fig. 2, the storage capacitor driving signal C <n + 2> is generated by the gate selection signal Gate <n>. This is set so as to delay the timing at which the data signal is written by the gate selection signal (Gate < n >) by the storage capacitor circuit output. In this example, . On the other hand, the number of lines to be offset can be appropriately selected.

15 shows a configuration example of a liquid crystal display apparatus using the liquid crystal panel driving apparatus (the gate selecting circuit 11 and the storage capacitor driving circuit 12) of the present invention.

The liquid crystal display device shown in Fig. 15 only shows a part directly related to the present invention, that is, a signal control circuit part for generating a signal such as a clock signal, so that the counter electrode driving circuit, the backlight, .

15, the liquid crystal panel 1 includes a gate line GL formed by arranging a plurality of electrodes in a horizontal direction, and a plurality of storage capacitor lines (not shown) formed by arranging a plurality of electrodes in the same horizontal direction, (CL), and a source line (SL) formed by arranging a plurality of electrodes in the vertical direction.

A pixel made up of a TFT (thin film transistor) switch, a liquid crystal capacitor LC, and a storage capacitor CS is formed at each intersection of the gate line GL and the source line SL.

The liquid crystal panel 1 is further provided with a gate selection circuit 11 for driving the plurality of gate lines GL, a storage capacitor driving circuit 12 for driving the plurality of storage capacitor lines, And a source driving circuit 13 for driving the source electrodes are connected.

The gate selection circuit 11 sequentially selects pixel TFTs (thin film transistors) connected to the gate line GL in one scanning period and simultaneously supplies a desired data voltage from the source driving circuit 13 to the liquid crystal capacitance LC ).

Further, after the data voltage is written, the data written in the liquid crystal capacitor LC is converted into a voltage suitable for the optical characteristics of the actual liquid crystal by superimposing the predetermined voltage from the storage capacitor driving circuit 12, do.

The signal control circuit portion 101 generates signals for controlling the gate selection circuit 11, the storage capacitor driving circuit 12, and the source driving circuit 13. [

The signal control circuit unit 101 is controlled by the control unit 2 including a CPU and the like, and based on an externally input image data signal, a synchronizing signal (horizontal and vertical synchronizing signal), and an external input clock signal, A signal for driving and controlling the selection circuit 11, the storage capacitor driving circuit 12, and the source driving circuit 13 is generated.

The clock generating circuit 110 in the signal control circuit portion 101 includes a frequency divider 111 for frequency dividing the horizontal synchronizing signal shown in Fig. 13, a divider 111 for generating an enable clock signal (enable 1, enable 2) Phase clock generating circuit 113 for generating the four-phase clock signals Ck1, Ck2, Ck3 and Ck4 and the clock signal converting circuit 114 shown in Fig. 9 .

The data signal generating circuit 121 generates and outputs the image signal of the source driving circuit 13 on the basis of the image data signal.

 (Operation of the first embodiment)

Next, the operation of the gate selection circuit in the first embodiment of the present invention will be described with reference to FIG.

4, the horizontal direction indicates the time, and the data signal Gdata input to the gate selection circuit 11 in the vertical direction, the enable clock signal (enable 1, enable 2), the four-phase clock signal Ck1, The output signals Q1, Q2, Q3 and Qm of the latch circuit LA1 and the gate selection signals Gate <1>, Gate <2>, Gate <3>, Gate <4> < m >).

4, when the data signal Gdata is input, the H level of the data signal Gdata is latched by the enable clock signals (enable 1 and enable 2), and the H level of the data signal Gdata is latched at the times t1, t2, and t3 The latch circuit output signals Q1, Q2, and Q3 are sequentially output.

Since the latch circuit outputs Q1 and Q2 are connected to the respective switch circuits SW1, they become enable signals for selecting the four-phase clock signals Ck1, Ck2, Ck3, and Ck4.

For example, when Q1 becomes H level, the switch circuit is turned ON, and the four-phase clock signals Ck1, Ck2, Ck3, and Ck4 are collectively selected, and the gate line output terminal Gate <1>, Gate <2>, Gate <3>, Gate <4> ...).

Since the latch circuit LA1 constitutes a shift register circuit, by sequentially transmitting the outputs Q1 and Q2, the switch circuit SW1 is also sequentially turned on, and each gate selection signal can be output at a desired timing .

Next, the operation of the storage capacitor driving circuit in the first embodiment of the present invention will be described with reference to Fig.

5, the horizontal direction is time, and in the vertical direction, the data signal Cdata input to the storage capacitor driving circuit 12 and the gate selection signal Gate <n + 2> output from the gate selection circuit 11) N + 9>, Gate <n + 3>, Gate n + 4, Gate n + 5, Gate n + 6, Gate n + N + 3>, C <n + 4>, C <n + 5>, C <n + 1>, C <n + + 6 >, C < n + 7 >).

When the gate selection signals (Gate <n + 2>, Gate <n + 3>,... Gate <n + 9>) from the gate selection circuit 11 are input to the respective switch circuits SW2 in FIG. 5, The switch circuits SW2 (SW2n + 2 to SW2n + 9) in the capacitor driving circuit 12 are turned ON in turn and the storage capacitor data Cdata is input to the latch circuits LA2 (LA2n to LA2n + 7).

The output of each held latch circuit LA2 (LA2n to LA2n + 7) is transferred to the buffer circuit BA2 (BA2n to BA2n + 7), and the storage capacitor line output terminals C <n>, C <n + 1> , C < n + 7 >).

On the other hand, the latch circuits LA2 (LA2n to LA2n + 7) are turned on in the next frame until the gate output (gate selection signal) from the gate selection circuit 11 is input to the switch circuit SW2 Continue to hold the value.

On the other hand, the latch circuit LA2 of the storage capacitor driving circuit in the first embodiment of the present invention is implemented by the bus type latch circuit (see Fig. 20 (B)) as described above.

The conventional storage capacitor driving circuit adopts the shift register configuration, and it is necessary to always supply the clock signal to the latch circuit which is the shifter register. For this reason, it is difficult for the storage capacitor driving circuit to be composed of the bus-type latch.

On the other hand, in the storage capacitor driving circuit of the present invention, since the timing of updating the data of the latch is determined only once in one frame, that is, only during a period in which the gate output of the gate selection circuit becomes H, no need. Therefore, it is possible to apply a bus-type latch having a small number of elements to the storage capacitance driving circuit.

 (Effects obtained by the first embodiment)

As described above, the output signal of the latch circuit LA1 used for generating the conventional gate selection signal is used as an enable signal for selecting a plurality of clock signals (for example, a clock signal of four phases). Therefore, when the conventional gate selection circuit requires one latch circuit per one gate output, if there are 0.5 (two latch circuits per four gate outputs) per one gate output in the gate selection circuit of the present invention, It is possible to configure the function. As a result, the number of latch circuits in the entire gate selection circuit can be reduced by half.

Although the four-phase clock signal is described as an example of the plurality of clock signals in the present embodiment, the gate selection circuit of the present invention is applicable to the case where the data signal Gdata input to the latch circuit LA1 and the enable clock signal Enable 1 and enable 2), it is possible to apply to clock signals other than four phases.

For example, by setting the pulse width of the data signal and the clock signal to 2 times (frequency 1/2) and inputting the 8-phase clock signal, the latch circuit necessary for the gate selection circuit is constituted by two latch circuits per 8 gate outputs .

Similarly, in the gate selection circuit of the present invention, by inputting the N phase clock signal, the required latch circuit can be reduced to 2 / N.

In the storage capacitor driving circuit of the present invention, the number of latch circuits required per output of the one-storage capacitor driving circuit is not changed to 1. However, by using the gate output of the gate selection circuit as the clock signal of the latch circuit, Can be reduced.

Further, unlike the conventional latch configuration, the bus-type latch circuit can reduce the number of circuit elements, and the overall circuit area of the storage capacitor driving circuit can be reduced as compared with the conventional case.

As described above, by using the gate selection circuit and the storage capacitor driving circuit of the present invention, the overall circuit area can be reduced, and as a result, the size of the frame of the liquid crystal panel can be reduced.

 [Second Embodiment]

In the first embodiment, the gate selection circuit 11 and the storage capacitor driving circuit 12 are provided separately, for example, as in the case shown in Fig. 18, on both sides of the liquid crystal panel 1, However, in the second embodiment, an example in which the gate selection circuit and the storage capacitor driving circuit are integrated into one, for example, an example in which two circuits are arranged on one side of the liquid crystal panel 1 .

An example of a driving apparatus for a liquid crystal panel according to the second embodiment of the present invention is shown in Fig.

The driving device 21 shown in Fig. 6 is composed of a gate selection circuit 11A and a storage capacitor driving circuit 12A.

In this driving device 21, the gate selection circuit 11A and the storage capacitor driving circuit 12A are alternately arranged in correspondence with the latch circuit LA1.

The gate selection circuit 11A includes a shift register circuit (latch circuit LA1) formed by serially connecting a plurality of latch circuits LA11 to LA1m and a desired gate signal from the four-phase clock signals Ck1, Ck2, Ck3, Ck4 A switch circuit SW1 formed of a plurality of MOS transistors for selecting the gate selection signals Gate <1>, Gate <2>, Gate <3>, Gate <4> BA1.

An enable clock signal (enable 1, enable 2) and a data signal Gdata are input to the shift register circuit (latch circuit LA1). A switch circuit SW1 is supplied with a plurality of clocks (Four-phase clock signals Ck1, Ck2, Ck3, and Ck4 in Fig. 6).

The outputs of the respective buffer circuits in the buffer circuit BA1 are connected to the gate line output terminals (Gate <1>, Gate <2>, Gate <3>, Gate <4>, ... Gate <m>).

The configuration of the gate selection circuit is the same as that of the gate selection circuit 11 of the first embodiment shown in FIG. 1, and a detailed description thereof will be omitted.

Then, the storage capacitor driving circuit 12A includes a switch circuit SW2, a switch circuit SW3, and a buffer circuit BA2.

The switch circuits SW2 (SW21 to SW2m) are switch circuits which are enabled by the clock signals (Ck1, Ck2, Ck3, Ck4) transmitted through the switch circuit SW3 and select the stored capacitance drive data signal (Cdata) , And sets this data in the latch circuits LA2 (LA21 to LA2m).

The switch circuits SW3 (SW31 to SW3m) have gates connected to the output sides of the even-numbered latch circuits LA12, LA14, ... in the shift register circuit (latch circuit LA1), and the four-phase clock signals Ck1, Ck2, Ck3, Ck4) and simultaneously enables the switch circuits SW2 (SW21 to SW2m).

The buffer circuits BA2 (BA21 to BA2m) are buffer circuits for receiving respective output signals of the latch circuits LA2 (LA21 to LA2m) and outputting the respective storage capacitance signals.

The output side of each of the plurality of buffer circuits BA21 to BA2m is connected to a corresponding one of the plurality of storage capacitor line output terminals C <1>, C <2>, C <3>, ..., C <m> Respectively.

In the configuration of the storage capacitor driving circuit, the contents including the switch circuits SW2 (SW21 to SW2m), the latch circuits LA2 (LA21 to LA2m), and the buffer circuits BA2 (BA21 to BA2m) And is the same as the capacitance driving circuit 12.

The storage capacitor driving circuit 12A shown in Fig. 6 differs from the storage capacitor driving circuit 12 shown in Fig. 2 in the point that a switch circuit SW3 (SW31 to SW3m) is used.

In other words, in the storage capacitor driving circuit 12 shown in Fig. 2, the gate selection signals Gate <n + 2> and Gate <n + 3> are used as gate signals of MOS transistors in the switch circuits SW2 (SW21 to SW2m) , ...) are used.

6, the switch circuits SW3 (SW31 to SW3m) output the output signals Q2 (LA1 to LA3m) of the even-numbered latch circuits LA12 to LA4m in the latch circuits LA1 Phase clock signals Ck1, Ck2, Ck3, and Ck4 and the MOS transistor gate signals of the switch circuits SW2 (SW21 to SW2m).

In this case, each switch in the switch circuit SW3 (SW31 to SW3m) is divided into four units to generate the gate signal of the switch circuit SW2.

For example, the four switch circuits SW31 to SW34 generate the gate signals of the switch circuits SW21 to 24 by the output signal Q2 of the latch circuit LA12 and the clock signals Ck1, Ck2, Ck3, and Ck4 . In the same manner, the four switch circuits SW35 to SW38 generate the gate signals of the switch circuits SW25 to 28 by the output signal Q4 of the latch circuit LA14 and the clock signals Ck1, Ck2, Ck3, and Ck4 .

 (Operation of Second Embodiment)

Next, the operation of the gate selection circuit and the storage capacitor driving circuit in the second embodiment of the present invention will be described with reference to FIG.

Here, the gate selection circuit is not different from the first embodiment, and a detailed description thereof will be omitted.

7, the horizontal direction is set as the time, and the data signal Gdata, the enable clock signal (enable 1, enable 2), the clock signals Ck1, Ck2, Ck3, Ck4, The output signal Q1 of the circuit LA11, the output signal Q2 of the latch circuit LA12, the data signal Cdata, the gate selection signal Gate <1>, the storage capacitor driving signal C <1> The gate selection signal Gate <2>, the storage capacitor driving signal C <2>, the gate selection signal Gate <3>, the storage capacitor driving signal C <3> ) And the storage capacitor driving signal (C < 4 >).

7, when the output Q2 of the latch circuit LA12 in the shift register circuit becomes H level, the operation of the storage capacitor driving circuit causes the switch circuit SW3 (SW31 to SW34) The switch circuit SW2 (SW21 to SW24) is enabled at a predetermined timing by the four-phase clock signals Ck1, Ck2, Ck3, and Ck4.

The switch circuits SW2 (SW21 to SW24) are turned on, and the storage capacitance data Cdata is input to the latch circuits LA2 (LA21 to LA24).

The output of each held latch circuit LA2 (LA21 to LA24) is transferred to the buffer circuit BA2 (BA21 to BA24), and the storage capacitor line output terminals C <1>, C <2>, C <3> 4 &gt;).

On the other hand, the latch circuits LA2 (LA21 to LA24) continue to hold the value of the storage capacitance data (Cdata) until the switch circuit SW2 (SW21 to SW24) is enabled again in the next frame.

On the other hand, the latch circuit LA2 of the storage capacitor driving circuit in the second embodiment of the present invention employs a bus-type latch circuit (see Fig. 20 (B)) composed of two inverter circuits.

In the first embodiment, the timing at which the data in the latch circuit LA2 is updated is a period during which the gate output of the gate selection circuit becomes H level. In contrast, in the second embodiment, the latch circuit LA12 of the gate selection circuit, The output Q2 of the clock signal CK2 becomes H level and the clock signals Ck1, Ck2, Ck3, and Ck4 of the four phases are changed to the H level. However, it is evident from the waveform diagram shown in Fig. 7 that the same effect as that of the first embodiment is obtained.

 (Effect in Second Embodiment)

Also in the second embodiment of the present invention, the output signal of the latch circuit LA1 is used as an enable signal for selecting a plurality of clock signals in order to generate a gate selection signal. In the gate selection circuit of the present invention, If there are 0.5 (two latch circuits per 4 gate outputs), it is possible to configure the same function. The same effect as that of the first embodiment can be obtained also in the second embodiment.

In the storage capacitor driving circuit, the number of latch circuits required per output of the one-storage capacitor driving circuit is not changed to one, but the control of the latch circuit LA2 is controlled by the output signals Q2 and Q4 , ...) and the four-phase clock signals (Ck1, Ck2, Ck3, Ck4), there is no need to separately prepare a control signal for controlling the storage capacitor driving circuit.

Further, unlike the conventional latch circuit configuration, by applying the bus-type latch circuit, it is possible to reduce the number of circuit elements, and the overall circuit area can be reduced also for the storage capacitor driving circuit.

As described above, by using the gate selection circuit and the storage capacitor driving circuit in the second embodiment of the present invention, the overall circuit area can be reduced while maintaining the same function as the conventional circuit, and as a result, The size of the frame of the liquid crystal panel can be reduced.

[Third Embodiment]

Fig. 8 shows a structure of a driving apparatus for a liquid crystal panel according to the third embodiment of the present invention.

The driving device 22 of the third embodiment shown in Fig. 8 is composed of a gate selecting circuit 11B and a storage capacitor driving circuit 12B.

The gate selection circuit 11B includes latch circuits LA1 (LA11 to LA1m), a switch circuit SW1, and a buffer circuit BA1.

On the other hand, the signal control circuit portion 101 incorporating the clock generating circuit 110 may be referred to as a gate selecting circuit.

The storage capacitor driving circuit 12B includes switch circuits SW2 and SW3, a latch circuit LA2, and a buffer circuit BA2.

The drive device 22 of the third embodiment shown in Fig. 8 differs from the drive device 21 of the second embodiment shown in Fig. 6 in that the transfer gates TG1 and TG2 Is a point newly added to the input side of the latch circuit LA1 (more precisely, LA11, LA13, ..., LA1m-1) which is a bidirectional switching circuit EXC Is the same as the circuit shown in Fig.

In other words, in the gate selection circuit and the storage capacitor driving circuit shown in Fig. 8, the data signal inputted to the latch circuits (LA11, LA13, ..., LA1m-1) (odd-numbered latch circuits) A bidirectional switching circuit EXC consisting of two transfer gates TG1 and TG2 for determining the transfer direction of the register and control signals UD and UDB for controlling the bidirectional switching circuit EXC are added.

8 is equivalent to the configuration in which the bidirectional switching circuit EXC is added to the gate selection circuit in the second embodiment shown in Fig. 6, and therefore, And the description thereof is omitted.

9 is a diagram showing a configuration of the clock signal conversion circuit 114. In Fig. In order to realize the bidirectional transfer of the shift register circuits LA11 to LA1m shown in Fig. 8, the clock signal conversion circuit 114 is synchronized with the states of the control signals UD and UDB and inverts the phase of the four-phase clock Circuit.

The clock signal conversion circuit 114 is provided in the clock generation circuit 110 of the signal control circuit portion 101 as shown in Fig.

9A, in the clock signal conversion circuit 114, the output sides of the transfer gate TG11 and the transfer gate TG12 are connected in common, and the input side of the transfer gate TG11 is connected with the clock signal CK1_a And the signal UDB is input to the control terminal phi and the signal UD is input to the control terminal phi.

The clock signal CK4_a is input to the input terminal of the transfer gate TG12 and the signal UD is input to the control terminal / φ and the signal UDB is input to the control terminal φ.

Any one of the clock signal Ck1_a and the clock signal Ck4_a is selected and output on the commonly connected output side of the transfer gates TG11 and TG12 according to the signal level of the signals UD and UDB.

The selected signal is output as the clock signal Ck1 through the buffer circuit BA3.

The transfer gates TG21 and TG22 to which the output sides are connected in common can be either one of the clock signal Ck2_a or the clock signal Ck3_a depending on the signal level of the signals UD and UDB in the same manner as the transfer gates TG11 and TG12 And the selected signal is output as the clock signal Ck2 through the buffer circuit BA3.

The transfer gates TG31 and TG32 to which the output sides are commonly connected also select either the clock signal Ck3_a or the clock signal Ck2_a according to the signal level of the signals UD and UDB and output the selected signal Is outputted as the clock signal Ck3 through the buffer circuit BA3.

The transfer gates TG41 and TG42 to which the output sides are commonly connected also select either the clock signal Ck4_a or the clock signal Ck1_a according to the signal level of the signals UD and UDB and output the selected signal Is outputted as the clock signal Ck4 through the buffer circuit BA3.

As shown in Fig. 9 (B), when the signal UD is at the H level and the signal UDB is at the L level, the input clock signals CK1_a, CK2_a, CK3_a, And the clock signals Ck1, Ck2, Ck3, and Ck4 according to the phase order of CK4_a.

On the other hand, when the signal UD is at the L level and the signal UDB is at the H level, the clock signals Ck1, Ck2, Ck3, Ck3, and Ck4 are inverted in phase order of the input clock signals CK1_a, CK2_a, CK3_a, Ck4 are output.

(Operation of Third Embodiment)

The operation of the gate selection circuit in the third embodiment of the present invention will be described with reference to FIG.

In the timing chart shown in Fig. 10, the horizontal direction is set as time and the data signal Gdata input to the latch circuit LA1, the enable clock signal (enable 1), the clock signals Ck1, Ck2, The output signal Q1 of the latch circuit LA11 or the output signal Qm-1 of the latch circuit LA1m-1), the output of the latch circuit LA21 The output signal Qm of the signal Q2 or the latch circuit LA1m, the signal UD and the signal UDB, the gate selection signal Gate <1>, the storage capacitor driving signal C <1> A gate selection signal Gate <3>, a storage capacitance driving signal C <3>, a gate selection signal Gate <4>, a gate selection signal Gate <2> M + 3>, the gate selection signal Gate <m-2>, the storage capacitor driving signal C <4>, the gate selection signal Gate < The driving signal C <m-2>, the gate selection signal Gate <m-1> The signal C <m-1>, the gate selection signal Gate <m>, and the storage capacitor driving signal C <m>.

As shown in Fig. 10, the bidirectional switching circuit EXC has a function of switching the transfer direction of the shift register circuit (the latch circuits LA1 (LA11 to LA1m)).

In other words, the transfer direction of the gate selection circuit is Gate <1>, Gate <2>, Gate <3>, Gate <4>, ... The signal UD is at the H level "UD = H", the signal UDB is at the L level "UDB = L", and the signal UDB of the bidirectional switching circuit EXC TG1 are turned on and TG2 is turned off, and the signal data Gdata is input to the latch circuit LA11 at the left end shown in Fig.

Data is sequentially transmitted in the form of output signals Q1, Q2, Q3, Q4, ... in synchronization with the enable clock signals (enable 1 and enable 2).

For example, gate selection signals Gate <1>, Gate <2>, Gate <3> and Gate <4> are output in the order of gate selection signals Gate 1, Gate 2 and Gate 4 in the period from t1 to t2.

Conversely, if the transfer direction of the gate selection circuit is ..., Gate <8>, ... The signal UD is at the L level "UD = L", the signal UDB is at the H level "UDB = H", and the signal UDB is at the H level when Gate < . Then, TG2 of the bidirectional switching circuit EXC is turned on, TG1 is turned off, signal data Gdata is input to the second latch circuit LA1m-1 from the right end, and the enable clock signal 1, Qm,... Sequentially in synchronization with the enable signal (enable 1, enable 2).

For example, gate selection signals are outputted in the order of the gate selection signals Gate <m>, Gate <m-1>, Gate <m-2>, and Gate <m-3> at time t3 to t4.

On the other hand, the operation from the latch output to the output of the gate selection signal is the same as in the first embodiment and the second embodiment.

The operation of the storage capacitor driving circuit in the third embodiment of the present invention is also the same as that of the second embodiment, and therefore, detailed description thereof will be omitted here.

(Effects in the Third Embodiment)

As described above, in the third embodiment, in addition to the functions of the second embodiment, it is possible to switch the transfer direction of the gate selection circuit and the storage capacitor driving circuit.

Further, by using the latch circuit LA1 used for generating the gate selection signal as an enable signal for selecting a plurality of clock signals, the gate selection circuit of the present invention is capable of generating 0.5 (4 Latch circuits), it is possible to configure the same functions, and therefore, the same effects as those of the first and second embodiments can be obtained.

In the storage capacitor driving circuit, the number of latch circuits required per output of the one-storage capacitor driving circuit is not changed to one, but control of the latch circuit LA2 is controlled by the output signals Q2, Q4, ..., And by using the four-phase clock signal, there is no need to separately prepare a control signal for controlling the storage capacitor driving circuit.

Further, by applying the bus-type latch circuit from the conventional latch structure, the number of circuit elements can be reduced, and the overall circuit area can be reduced also for the storage capacitor driving circuit.

As described above, by using the gate selection circuit and the storage capacitor driving circuit in the third embodiment of the present invention, it is possible to reduce the overall circuit area while maintaining the same function as the conventional circuit, and as a result, It is possible to contribute to the reduction of the size of the frame of the liquid crystal panel.

 The structure of the driving apparatus for the liquid crystal panel according to the fourth embodiment of the present invention is shown in Fig.

The driving apparatus 23 of the fourth embodiment shown in Fig. 11 includes a gate selecting circuit 11C and a storage capacitor driving circuit 12C.

The gate selection circuit 11C includes a latch circuit LA1 (LA11 to LA1m), a bidirectional switching circuit EXC, a partial display circuit DP1, a switch circuit SW1, and a buffer circuit BA1. On the other hand, the signal control circuit portion 101 incorporating the clock generation circuit 110 may be included and be referred to as a gate selection circuit.

The storage capacitor driving circuit 12C includes a partial display circuit DP2, a switch circuit SW2, a switch circuit SW3, a latch circuit LA2, and a buffer circuit BA2.

In the driving device 23 shown in Fig. 11, the gate selection circuit 11C and the storage capacitor driving circuit 12C are arranged alternately corresponding to the latch circuit LA1.

The gate selection circuit and the storage capacitor driving circuit of the fourth embodiment shown in Fig. 11 are different from the gate selection circuit and the storage capacitor driving circuit of the second embodiment shown in Fig. 8 in the configuration shown in Fig. Circuits DP1 to DPm are newly added, and the other configurations are the same as those of the third embodiment shown in Fig.

In other words, the circuit configuration in the fourth embodiment of the present invention is different from the configuration in which the partial display circuits DP1 to DPm are added to the gate selection circuit and the storage capacitor driving circuit in the third embodiment of the present invention same. Therefore, the description of the same components as those of the circuit shown in Fig. 8 will be omitted.

In Fig. 11, odd-numbered partial display circuits DP1, DP3, ... are constituted by connecting a NAND circuit and an inverter circuit in series.

For example, with respect to the partial display circuit DP1, the signal Part1 is inputted to one input terminal of the NAND circuit NAND21 and the output signal Q1 of the latch circuit LA11 is input to the other input terminal thereof .

The output signal of the NAND circuit NAND21 is input to the switch circuit SW1 through the inverter circuit INV21 and the output of the inverter circuit INV21 becomes the common gate signal of each MOS transistor in the switch circuit SW1.

The even-numbered partial display circuits DP2, DP4, ... are constituted by connecting a NAND circuit and an inverter circuit in series.

For example, for the partial display circuit DP2, the signal Part2 is inputted to one input terminal of the NAND circuit NAND22 and the output signal Q2 of the latch circuit LA12 is input to the other input terminal thereof .

The output signal of the NAND circuit NAND22 is input to the switch circuit SW3 via the inverter circuit INV22 and the output of the inverter circuit INV22 becomes the common gate signal of each MOS transistor in the switch circuit SW3.

(Operation of Fourth Embodiment)

The operation of the gate selection circuit in the fourth embodiment will be described with reference to Fig.

In the timing chart shown in Fig. 12, the horizontal direction is set as time, and the data signal Gdata input to the latch circuit LA1, the enable clock signal (enable 1), the clock signals Ck1, Ck2, The output signal Q1 of the latch circuit LA11 or the output signal Qm-1 of the latch circuit LA1m-1, the latch circuit LA12 The output signal Q2 of the latch circuit LA1m or the output signal Qm of the latch circuit LA1m, the signal UD, the signals Part1 and Part2, the gate selection signal Gate <1> >, The gate selection signal Gate <2>, the storage capacitor driving signal C <2>, the gate selection signal Gate <3>, the storage capacitor driving signal C <3> M <3>), the storage capacitor driving signal C <4>, the gate selecting signal Gate <m-3>, the storage capacitor driving signal C < >, The storage capacitor driving signal C <m-2>, the gate selection signal Gate <m-1> The signal C <m-1>, the gate selection signal Gate <m>, and the storage capacitor driving signal C <m>.

Since the operation of switching the transfer direction of the shift register is the same as that of the third embodiment, a detailed description thereof will be omitted. Here, operations related to the functions of the partial display circuit DP1 and the partial display circuit DP2 .

When the signal Part1 shown in Fig. 12 is at the H level, the switch circuit SW1 enabled by the output signal Q1 of the latch circuit LA11 is turned on, and the four-phase clock signals Ck1, Ck2, Ck3 , Ck4 are outputted as a predetermined gate selection signal.

In contrast, when the signal Part1 is at the L level, the gate selection circuit 11C is turned off and the gate selection signals Gate <1>, Gate <2>, Gate <3>, Gate <4> No output.

Reference is made to the timing indicated by the hatched portion denoted by a in Fig. 12.

During the period from t1 to t2, since the signal Part1 becomes the L level, the gate selection signals Gate < 2 > and Gate < 3 > (shaded portions indicated by the reference symbol a) are not output.

In this manner, the state of the switch circuit can be controlled for each gate line in accordance with the logic of the signal Part1, and only a desired gate line can be selected and output.

This function is a function necessary for partially displaying the liquid crystal panel and is realized by taking the same configuration as the fourth embodiment of the present invention.

Similarly, also in the storage capacitor driving circuit, the partial display circuit DP2 makes it possible to update only the data of the desired storage capacitor output.

Reference is made to the timing indicated by the hatched portion denoted by the reference numeral "Hold" in Fig.

 In the period from t2 to t3, the signal Part2 becomes the L level, and the storage capacitor driving signals C < 2 >, C < 3 & .

On the other hand, in the storage capacitor driving circuit, since the output state is maintained by the latch circuit LA2, the latch data of the latch circuit LA2 which is not updated by the partial display function is also held in the next frame.

(Effect in the fourth embodiment)

As described above, in the fourth embodiment, the function of the third embodiment is added to the function of the partial display.

The output signal of the latch circuit LA1 used for generating the gate selection signal is used as an enable signal for selecting a plurality of clock signals so that the gate selection circuit of the present invention has 0.5 Two latch circuits), it is possible to configure a function as in the prior art. Therefore, the same effects as those of the first embodiment, the second and third embodiments are obtained.

In addition, in the storage capacitor driving circuit, it is not necessary to separately prepare a control signal for controlling the storage capacitor driving circuit as in the above embodiment.

Further, by applying the bus-type latch circuit from the conventional latch structure, the number of circuit elements can be reduced, and the overall circuit area can be reduced also for the storage capacitor driving circuit.

As described above, by using the gate selection circuit and the storage capacitor driving circuit in the fourth embodiment of the present invention, it is possible to reduce the overall circuit area while maintaining the same function as the conventional circuit, and as a result, It is possible to contribute to the reduction of the size of the frame of the liquid crystal panel.

As described above, in the present invention, in the gate selection circuit of the electro-optical device (active matrix type liquid crystal panel) used in a portable information terminal or the like, the clock selection circuit includes a clock generation circuit A plurality of latch circuits controlled by enable clock signals (enable 1, enable 2) generated by the clock generating circuit to perform a shift register operation, and a plurality of latch circuits which are enabled by an output signal to the latch circuit And a switch circuit.

The plurality of clock signals generated by the clock generation circuit are sequentially output as the gate selection signal by the output signal to the latch circuit, thereby reducing the circuit scale of the entire gate selection circuit.

In the storage capacitor driving circuit for driving the storage capacitor of the pixel circuit of the liquid crystal panel, by using the gate selection signal output as the latch circuit enable signal in the storage capacitor driving circuit, it is necessary to drive the storage capacitor driving circuit Decreasing the control signal.

Further, by applying the bus-type latch circuit to the latch circuit of the storage capacitor driving circuit, the whole circuit area can be reduced.

Here, the correspondence relationship between the present invention and the above embodiment will be supplementarily described.

A driving apparatus for a liquid crystal panel according to the present invention comprises a gate selection circuit and a storage capacitor driving circuit.

The driving device of the liquid crystal panel of the present invention corresponds to the driving devices 21, 22, and 23.

The gate selection circuit (11, 11A, 11B, 11C) corresponds to the gate selection circuit of the present invention and the storage capacitor drive circuit of the present invention corresponds to the storage capacitor drive circuit (12, 12A, 12B, 12C) do.

On the other hand, the gate selection circuits 11, 11A, 11B, and 11C may include the clock generation circuit 110 shown in Fig.

The clock generation circuit in the present invention corresponds to the clock generation circuit 110 (refer to Fig. 15).

The first latch circuit in the present invention corresponds to each of the latch circuits LA1 (LA11 to LA1n) and the second latch circuit corresponds to each of the latch circuits LA2 (LA21 to LA2m).

In the present invention, the first switch circuit SW1 (SW11 to SW1m, etc.), the second switch circuit SW2 (SW21 to SW2m, etc.), the third switch circuit SW3 (SW31 to SW3m Respectively.

The bidirectional switching circuit in the present invention corresponds to the bidirectional switching circuit EXC (see Fig. 8), the first partial display circuit corresponds to the partial display circuit (DP1, see Fig. 11) The two-part display circuit corresponds to the partial display circuit DP2.

The enable clock signal of the present invention corresponds to the enable clock signals (enable 1 and enable 2), and the plurality of clock signals correspond to the four-phase clock signals Ck1, Ck2, Ck3, and Ck4.

The data held in the first latch circuit LA1 is the data signal Gdata, the data set in the second latch circuit LA2 is the data signal Cdata, the first partial display control signal is the signal Part1 (see Fig. 11) , And the second partial display control signal corresponds to each of the signals (Part 2, see FIG. 11).

In the embodiment, the clock generation circuit 110 in the gate selection circuit 11 generates an enable clock signal which is generated by frequency-dividing a predetermined horizontal synchronization signal synchronized with the image signal displayed on the liquid crystal panel 1, (Enable 1, enable 2) and a plurality of clock signals Ck1, Ck2, Ck3 (Ck1, Ck2, Ck3) generated from a predetermined vertical synchronizing clock signal and an enable clock signal , Ck4).

A plurality of first latch circuits LA1 are connected in series to form a shift register and shift information (Gdata) retained in synchronization with the enable clock signals (enable 1, enable 2).

The first switch circuit SW1 is provided corresponding to the gate line GL and supplies clock signals Ck1, Ck2, Ck3 and Ck4 to each gate line GL as a gate selection signal of the pixel. The first switch circuit SW1 sequentially outputs the gate selection signal in accordance with the output signal output from the first latch circuit LA1.

Thus, the plurality of clock signals Ck1, Ck2, Ck3, and Ck4 generated by the clock generation circuit 110 are sequentially output as the gate selection signal from the switch circuit SW1 in accordance with the output signal from the latch circuit LA1, It is possible to provide a gate selection circuit in which the circuit scale of the latch circuit LA1 is reduced.

In the above embodiment, the storage capacitor driving circuit 12 has a plurality of second latch circuits LA2 for driving the storage capacitors provided in the pixels, and the second switch circuit SW2 is output from the gate selection circuit 11 And transfers the information held in the storage capacitor CS to the second latch circuit LA2 according to the gate selection signal.

Thus, by using the gate selection signal output from the gate selection circuit 11, it becomes possible to reduce the control signal for controlling the second latch circuit LA2.

Further, since the second latch circuit can be constituted by a bus-type latch circuit constituted by two inverter circuits, the overall circuit area can be reduced also for the storage capacitor driving circuit.

In the above embodiment, the driving apparatus for the liquid crystal panel is provided with the gate selection circuit 11 and the storage capacitor driving circuit 12.

The gate selection circuit 11 includes a plurality of first latch circuits LA1 and a plurality of second latch circuits LA1 and LA2 for forming a shift register connected in series and shifting the information held in synchronization with the enable clock signals (enable 1, enable 2) When supplying the clock signals Ck1, Ck2, Ck3, and Ck4 corresponding to the respective gate lines GL as the gate selection signals of the pixels provided corresponding to the lines GL, the output signals from the first latch circuit LA1 And a first switch circuit SW1 for sequentially outputting a gate selection signal in accordance with the gate selection signal.

The storage capacitor driving circuit includes a plurality of second latch circuits LA2 for driving the storage capacitor CS provided in the pixel and a plurality of second latch circuits LA1 and LA2 for holding the storage capacitor CS in accordance with the gate selection signal output from the gate selection circuit 11. [ And a second switch circuit SW2 for transmitting information (data signal Cdata) to the second latch circuit LA2.

As described above, by using the gate selection circuit and the storage capacitor driving circuit of the invention in the driving apparatus for the liquid crystal panel, it is possible to reduce the number of circuits of the latch circuit and the overall circuit area. As a result, Can be reduced.

6), the third switch circuit SW3 inputs a plurality of clock signals Ck1, Ck2, Ck3, and Ck4, and the first latch circuit LA1 And is enabled by an output signal.

Then, in the enabled state, the clock signals Ck1, Ck2, Ck3, and Ck4 are output to the second switch circuit SW2, thereby bringing the second switch circuit SW2 into the enabled state.

The drive unit 21 sequentially supplies the plurality of clock signals Ck1, Ck2, Ck3, and Ck4 to the first switch circuit SW1 in a predetermined period that is enabled by the output signal of the first latch circuit LA1 And sequentially outputs the output signal of the second latch circuit LA1 as an output signal of the gate selection circuit. At the same time, in the predetermined period in which the output signal of the first latch circuit LA1 is enabled, And sets the information to be held in the storage capacitor CS in the circuit LA2.

Accordingly, by using the gate selection circuit and the storage capacitor driving circuit of the present invention in the driving apparatus for the liquid crystal panel, it is possible to reduce the overall circuit area while maintaining the same function as that of the conventional circuit. As a result, It is possible to reduce the size of the frame.

8) includes a bidirectional switching circuit EXC for selecting the input information input to the first latch circuit LA1 and selecting the direction in which the held information is shifted, And a clock signal conversion circuit 114 for converting the phase order of a plurality of clock signals supplied to the first switch circuit SW1 and the second switch circuit SW2.

This makes it possible to switch the transfer direction of the gate selection circuit and the storage capacitor driving circuit.

The gate selection circuit 11C of the driving device 23 of the liquid crystal panel (see Fig. 11) is connected to the first latch circuit LA1 and the first partial display control signal (Part1) A first switch circuit SW1 which is connected to each of the plurality of clock signals Ck1, Ck2, Ck3 and Ck4 and which is enabled by the output signal from the first partial display circuit DP1, &Lt; / RTI &gt;

The storage capacitor driving circuit 12C includes a second partial display circuit DP2 whose output is determined by the output signal from the first latch circuit LA1 and the second partial display control signal Part2 and a plurality of clock signals Ck1 Ck2, Ck3, and Ck4, respectively, and is enabled by the output signal from the second partial display circuit DP2, and in the enabled state, the clock signals Ck1, Ck2, Ck3, Ck4 And a third switch circuit SW3 for putting the second switch circuit SW2 in an enabled state.

 The plurality of clock signals Ck1, Ck2, Ck3 and Ck4 are selected by the gate selection circuit 11C (CK1, Ck2, Ck3, Ck4) only in the predetermined period in the enabled state by the output signal of the first partial display circuit DP1 As shown in Fig. The information held in the storage capacitor CS is supplied to the second switch circuit SW2 and the second switch circuit SW2 by the output signal of the second partial display circuit DP2 in a predetermined period enabled by the output signal of the first latch circuit LA1. 3 switch circuit SW3 is selectively enabled and selectively updated. The output order of the output signals in the gate selection circuit 11C and the storage capacitor driving circuit 12C is reversed in accordance with the bidirectional switching circuit EXC and the clock signal conversion circuit 114. [

As a result, it is possible to reduce the overall circuit area, and as a result, the size of the frame of the liquid crystal panel can be reduced, and the function of the partial display can be added.

Although the embodiment of the present invention has been described above, the gate selection circuit, the storage capacitor driving circuit, and the driving apparatus for the liquid crystal panel of the present invention are not limited to the above-described examples, It is needless to say that various modifications can be added within the scope of the present invention.

One… LCD panel, 2 ... A control unit 11, Gate selection circuit, 12 ... Accumulated capacitance drive circuit, 13 ... Source driving circuit, 21, 22, 23 ... Driving device of liquid crystal panel, 101 ... Signal control circuit section 110, A clock generating circuit, (111) ... Dividing circuit, 112 ... An enable clock signal generation circuit 113, 4-phase clock generation circuit, 114 ... Clock signal conversion circuit, 121 ... A data signal generation circuit 201, Gate selection circuit, 202 ... The storage capacitor driving circuit, BA 1, BA 2 ... Buffer circuit, CL ... Accumulation capacity line, (GL) ... Gate line, (SL) ... Source line, DP 1, DP2 ... Partial display circuits, LA 1, LA 2, LA 3 ... Latch circuit, SW 1, SW 2, SW 3 ... Switch circuit, TG 1, TG2 ... Transfer gate, EXC ... Bidirectional switching circuit

Claims (11)

delete delete delete delete In each of a plurality of regions in which a plurality of gate lines arranged in the horizontal direction, a plurality of storage capacitor driving lines arranged in the horizontal direction and a plurality of source lines arranged in the vertical direction cross each other, thin film transistor switches, liquid crystal capacitors, A liquid crystal panel having a plurality of pixels arranged in a matrix,
An enable clock signal generated by dividing a predetermined horizontal synchronous signal synchronized with an image signal displayed on the liquid crystal panel, a predetermined vertical synchronous clock signal, and at least four phases generated from the enable clock signal and having different phases, A clock generating circuit for generating a plurality of clock signals,
A plurality of first latch circuits connected in series to form a shift register and to shift the held information in synchronization with the enable clock signal,
The gate selection signal is sequentially output in accordance with the output signal of the first latch circuit when the clock signal corresponding to each gate line is supplied as the gate selection signal to the pixel A gate selection circuit including a first switch circuit, and
A plurality of second latch circuits for driving the storage capacitors provided in the pixels; a second switch circuit for transferring information held in the storage capacitor to the second latch circuit in accordance with the gate selection signal; And a third switch circuit connected to the first latch circuit and rendered to be in an enabled state by the output signal of the first latch circuit and outputting the clock signal in the enabled state to place the second switch circuit in the enabled state And a storage capacitor driving circuit including the storage capacitor driving circuit. 6. The method of claim 5,
And sequentially outputs the plurality of clock signals as output signals of the gate selection circuit in a predetermined period in which the first switch circuit is enabled by the output signal of the first latch circuit,
The second latch circuit is maintained in the storage capacity by the output signal of the first latch circuit through the second switch circuit and the third switch circuit in a predetermined period in which the third switch circuit is in an enabled state, Conveyed information,
Driving device. The method according to claim 5 or 6,
A bidirectional switching circuit for selecting the input information input to the first latch circuit and selecting a direction for shifting the held information,
Further comprising a clock signal conversion circuit for converting the phase order of the plurality of clock signals supplied to the first switch circuit and the third switch circuit,
And sequentially outputs the plurality of clock signals as output signals of the gate selection circuit in a predetermined period in which the first switch circuit is enabled by the output signal of the first latch circuit,
The second latch circuit is maintained in the storage capacity by the output signal of the first latch circuit through the second switch circuit and the third switch circuit in a predetermined period in which the third switch circuit is in an enabled state, Information,
And the output order of the output signals in the gate selection circuit and the storage capacitance driving circuit is reversed in accordance with the bidirectional switching circuit and the clock signal conversion circuit. In each of a plurality of regions in which a plurality of gate lines arranged in the horizontal direction, a plurality of storage capacitor driving lines arranged in the horizontal direction and a plurality of source lines arranged in the vertical direction cross each other, thin film transistor switches, liquid crystal capacitors, A liquid crystal panel having a plurality of pixels arranged in a matrix,
An enable clock signal generated by frequency-dividing a predetermined horizontal synchronous signal synchronized with an image signal displayed on the liquid crystal panel, a predetermined vertical synchronous clock signal, and at least four or more phases generated from the enable clock signal and having different phases A clock generating circuit for generating a plurality of clock signals,
A plurality of first latch circuits connected in series to form a shift register and to shift the held information in synchronization with the enable clock signal,
A first partial display circuit which outputs an output of the first latch circuit and a first partial display control signal, and a second partial display circuit which is provided corresponding to the gate line and which supplies the clock signal corresponding to each gate line to the pixel And a first switch circuit for sequentially outputting the plurality of clock signals as the gate selection signal in a predetermined period that is enabled by the output signal of the first partial display circuit when the gate signal is supplied as the gate selection signal of the gate Selection circuit,
A plurality of second latch circuits for driving the storage capacitors provided in the pixels, a second switch circuit for transferring information held in the storage capacitor to the second latch circuit in accordance with the gate selection signal, A second partial display circuit whose output is determined by an output of the first partial display control circuit and an output of which is determined by a second partial display control signal and a second partial display circuit which is connected to the plurality of clock signals, And a third switch circuit for outputting the clock signal in the enabled state to bring the second switch circuit into an enabled state,
A bidirectional switching circuit for selecting the input information input to the first latch circuit and selecting a direction for shifting the held information,
And a clock signal conversion circuit for converting the phase order of the plurality of clock signals supplied to the first switch circuit and the third switch circuit,
. The method according to claim 5 or 6,
Wherein the first latch circuit comprises:
Wherein the number of the first latch circuits is at least (2 / N) per one gate line, and the number of the latch circuits according to the number N of the plurality of clock signals (N is an even number in an even number). The method according to claim 5 or 6,
And the second latch circuit is a bus-type latch circuit formed of two inverter circuits. In each of a plurality of regions in which a plurality of gate lines arranged in the horizontal direction, a plurality of storage capacitor driving lines arranged in the horizontal direction and a plurality of source lines arranged in the vertical direction cross each other, thin film transistor switches, liquid crystal capacitors, And a plurality of pixels arranged in a matrix form, the method comprising the steps of:
An enable clock signal generated by frequency-dividing a predetermined horizontal synchronizing signal synchronized with an image signal displayed on the liquid crystal panel, a predetermined vertical synchronizing clock signal, and a plurality of Generating a clock signal,
Shifting information held in a plurality of first latch circuits connected in series and forming a shift register in synchronization with the enable clock signal,
Sequentially outputting the gate selection signal in accordance with an output signal of the first latch circuit when supplying the clock signal to each of the gate lines as a gate selection signal of the pixel,
The third switch circuit connected to the plurality of clock signals is enabled by the output signal of the first latch circuit and the clock signal is outputted in the enabled state to enable the second switch circuit to be in an enabled state , &Lt; / RTI &
The second switch circuit in the enabled state transfers to the second latch circuit the information held in the storage capacitor provided by the pixel in accordance with the gate selection signal,
The second latch circuit driving the storage capacitor
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