KR101784076B1

KR101784076B1 - Field Emission Display and Fabricating Method thereoof

Info

Publication number: KR101784076B1
Application number: KR1020150183527A
Authority: KR
Inventors: 이춘래; 최용훈
Original assignee: 이춘래; 최용훈
Priority date: 2014-12-22
Filing date: 2015-12-22
Publication date: 2017-10-10
Also published as: KR20160076481A

Abstract

The present invention relates to a field emission display and a method of manufacturing the same, and more particularly, to a field emission display (TFT) having a top gate structure, a pixel electrode connected to the TFT, a diffusion barrier layer formed on the pixel electrode, And a carbon nanotube formed on the seed metal pattern. The gate of the TFT is vertically overlapped with either the drain or the source. And an electrode which is not vertically overlapped with the gate of the TFT among the drain and the source is connected to the pixel electrode. The distance between the gate and the electrode of the TFT not overlapping with the gate of the TFT vertically and the gate is larger than the thickness of the gate insulating film.

Description

[0001] Field emission display and fabricating method thereof [0002]

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a field emission display including a carbon nanotube (hereinafter referred to as "CNT") and a thin film transistor (hereinafter referred to as "TFT") and a method of manufacturing the same.

Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). Such flat panel display devices include a liquid crystal display (LCD), a plasma display panel (PDP), an electroluminescence device, and a field emission display (FED).

The field emission display (FED) forms an electric field between a gate electrode and a field emitter arranged at regular intervals on a cathode electrode to induce the emission of electrons from the electron emission source, Images are displayed by impinging on the material. Such a field emission display device is advantageous for light and small size, and has attracted attention as a next generation display device together with a liquid crystal display device, a plasma display panel and the like because of advantages such as a wide viewing angle and low power consumption.

Micron, TI and Pixtec of USA have tried to commercialize low voltage field emission display but failed to develop field emission display by failing to develop low voltage phosphor and secure device reliability. Candescent of USA, Sony of Japan, Samsung SDI of Korea, and LGE tried to develop commercialization of high voltage FED, but failed to develop economical focusing mechanism and device structure to give up development of field emission display Respectively.

(CNT) as an emitter instead of a conventional molybdenum emission cone in ITRI of Taiwan, Samsung SDI of Korea, and cDream of the United States to solve the problems of the existing technology, It has failed to overcome the problems of the existing technology and abandoned the commercialization development of the field emission display device.

Although Canon / Toshiba of Japan is attempting to commercialize FED using SED technology as a joint venture, it still fails to commercialize because of the inconsistency of electron emission efficiency, the difficulty of emitter manufacturing, and the development of focusing mechanism and device structure. Respectively.

The inventors of the present invention have attempted to develop a field emission display device capable of directly using a TFT-LCD production line using carbon nanotubes (CNTs) as emitters, but the threshold voltage of carbon nanotubes (CNTs) Threshold Voltage, Vth) to the target level. Accordingly, the applicant of the present invention has proposed a structure capable of sufficiently lowering the threshold voltage of a carbon nanotube (CNT) while using the existing TFT-LCD production line, in Korean Patent No. 10-0871892 (registered on November 27, 2008) have. In the manufacturing process of the field emission display device proposed in Korean Patent No. 10-0871892, indium tin oxide (ITO) was corroded during the process of etching the nickel, and the total number of processes required for the conventional TFT-LCD It is estimated that the manufacturing process is complicated due to the increase in the number of mask steps (mask step) and the competitiveness of the manufacturing process compared to the conventional TFT-LCD. Korean Patent No. 10-0871892 proposes a field emission display device in which a seed metal such as nickel is diffused in a molybdenum / aluminum (Mo / Al) layer as a light shielding layer in a process of growing carbon nanotubes (CNTs) (CNT) growth is difficult because the seed metal layer is almost not left. Due to such a problem, the field emission display proposed in Korean Patent No. 10-0871892 has been put to practical use.

The applicant of the present application has proposed a field emission display device and a method of manufacturing the same which can solve the diffusion problem of seed metal and reduce the number of manufacturing processes through Korean Patent No. 10-1157215 (Jun. 11, 2012).

In such a field emission display device, the threshold voltage of the carbon nanotube (CNT) must be the same throughout the screen. In order to grow carbon nanotubes (CNTs), a high-temperature process of 400 ° C or higher is required, and measures must be taken to avoid problems in subsequent processes due to substrate expansion, contraction, and deformation at high temperatures. In the case of the technique proposed in Korean Patent No. 10-1157215, it has been difficult to align gate holes with carbon nanotubes (CNTs) due to high temperature deformation of the substrate after CNT growth. In order to solve this problem, a method of growing carbon nanotubes (CNTs) on the entire surface of a pixel has been proposed. However, in order to uniformize the height of carbon nanotubes (CNTs) It is difficult to cut the carbon nanotubes (CNTs). Thus, the gate electrode on the carbon nanotubes (CNTs) and the cathode under the carbon nanotubes (CNTs) are short-circuited through the carbon nanotubes (CNTs).

The inventors of the present invention have proposed a structure of a field emission display capable of solving the problems of the prior art in Korean Patent Application No. 10-2014-0087651 (Apr. According to the present invention, electrons are emitted from carbon nanotubes only by a voltage between an anode and a cathode without a gate electrode and a gate hole on a carbon nanotube (CNT). Accordingly, the proposed invention has no problem of aligning the CNTs with the gate holes, and the CNTs and the gate electrodes disposed thereon are not short-circuited, thereby increasing the yield. Since the proposed invention forms carbon nanotubes (CNTs) on a TFT array, the number of manufacturing steps of the TFT array substrate can be increased.

Korean Patent Laid-Open Publication No. 2002-0065968 (hereinafter referred to as " Prior Art 968 " hereinafter) refers to an upper part including a phosphor and an anode, a lower part including a cathode, The diode structure is drawn out. However, since the carbon nanotubes can not be vertically erected because the carbon nanotubes are adhered to the cathode as the adhesive layer and the lengths of the carbon nanotubes are uneven, the electron gun drawn from the carbon nanotubes is finely adjusted to the cathode voltage The display function can not be performed and can be used for simple illumination purposes only.

The present invention provides a field emission display device and a method of manufacturing the same, which can simplify the structure of a TFT array substrate and reduce the number of manufacturing processes by forming electron emitting devices including carbon nanotubes in the manufacturing process of a TFT array.

A cathode substrate of a field emission display according to an exemplary embodiment of the present invention includes a TFT (Thin Film Transistor) of a top-kate structure, a pixel electrode connected to the TFT, a diffusion barrier layer formed on the pixel electrode, And a carbon nanotube formed on the seed metal pattern.

The gate of the TFT is vertically overlapped with either the drain or the source. And an electrode which is not vertically overlapped with the gate of the TFT among the drain and the source is connected to the pixel electrode. The distance between the gate and the electrode of the TFT not overlapping with the gate of the TFT vertically and the gate is larger than the thickness of the gate insulating film.

The semiconductor channel layer and the diffusion barrier layer of the TFT include amorphous silicon or polysilicon. The seed metal pattern includes nickel silicide.

A method of manufacturing a field emission display device includes: forming a pixel electrode integrated with a source and a drain of a TFT and a drain of the TFT as a first metal pattern; Forming a gate insulating film covering the first metal pattern; Forming a semiconductor pattern on the gate insulating layer to form a diffusion barrier layer on the semiconductor channel of the TFT and the pixel electrode; Forming a gate of the TFT with a second metal pattern on the gate insulating film; Forming a protective film covering the TFT; Forming a seed metal pattern on the diffusion barrier layer; And forming carbon nanotubes on the seed metal pattern.

The present invention can simplify the structure of the TFT array substrate in the field emission display device and reduce the number of manufacturing processes by simultaneously forming the electron-emitting devices when forming the TFTs of the top gate structure.

The field emission display of the present invention emits electrons from the carbon nanotubes only by the voltage between the anode and the cathode without the gate electrode and the gate hole on the carbon nanotube. Accordingly, the field emission display of the present invention has no problem of alignment between the carbon nanotubes and the gate holes, and the yield of the carbon nanotubes and the gate electrode disposed thereon are not short-circuited.

Furthermore, the present invention can solve the problem of damaging the TFT in the field emission display by designing the TFT in an asymmetric structure.

1 is a cross-sectional view illustrating a field emission display according to an embodiment of the present invention.
2 is a plan view showing a pixel arrangement of a field emission display according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a cross-sectional structure of a pixel according to an embodiment of the present invention.
FIG. 4 is a graph showing current-voltage characteristics of a field emission display according to an embodiment of the present invention.
5 is a cross-sectional view illustrating an asymmetric TFT structure according to an embodiment of the present invention.
6 and 7 are diagrams showing voltages applied between the anode and the cathode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Referring to FIGS. 1 and 2, a field emission display according to an embodiment of the present invention is divided into an anode substrate and a cathode substrate facing each other with a vacuum space (VAC) therebetween. A spacer may be formed between the anode substrate and the cathode substrate.

The anode substrate and the cathode substrate are sealed with a sealant (SEAL) between the vacuum spaces (VAC). In order to maintain a cell gap of the vacuum space (VAC), a spacer is disposed between the anode substrate and the cathode substrate. The thickness of the vacuum space (VAC) between the anode substrate and the cathode substrate is approximately 1 mm. A high voltage of about 5 to 10 Kv is applied between the anode (AND) and the cathode (CAT). Spacers are made of glass or ceramic spacers because they must not penetrate the pixel area and must have sufficient strength.

The anode substrate includes an anode (ANO) and a phosphor (PHOS) formed on an upper substrate (SUBS2). The anode (ANO) is applied with a positive voltage. The anode ANO can be integrated with a metal black matrix (BM). An anode (ANO) integrated with the black matrix may be formed along the boundary between the sub-pixels. The phosphor (PHOS) is excited and transited by electrons from carbon nanotubes (CNT) to emit red, green and blue light.

The lower plate includes a TFT array formed on the lower substrate SUB1 and an electron-emitting device. The electron emitting device includes a pixel electrode (CAT) serving as a cathode and a carbon nanotube (CNT) formed thereon. This electron-emitting device is built in a TFT array.

The TFT array includes data lines DL, gate lines GL orthogonal to the data lines DL, TFTs formed at the intersections of the data lines DL and the gate lines GL, (CNT) formed on the pixel electrodes (CAT), and pixel electrodes (CAT) connected to the pixel electrodes (CAT) at a ratio of 1: 1. Each of the pixels may be provided with a storage capacitor (not shown) connected to the pixel electrode to maintain the pixel voltage for one frame.

A negative data signal having a negative polarity relative to the anode voltage is applied to the data lines DL. A scan signal synchronized with the data signal is sequentially applied to the gate lines GL. A scan signal selects pixels of one line to which data of an input image is to be written by simultaneously selecting TFTs connected to the gate lines GL one by one. The TFT array includes pads Pad for connecting data lines DL and gate lines GL to a drive IC (Integrated Circuit). The pads are divided into data pads (DP) and gate pads (GP). The data pads DP connect the data lines DL to the output channel of the data drive IC to which the data signals are output. The gate pads GP connect the gate lines DL to the output channel of the gate drive IC to which the scan signal is output.

The TFTs are turned on in response to a scan signal from the gate line GL to supply a negative data voltage to the pixel electrode CAT. The gate G of the TFT is connected to the gate line GL. The drain D of the TFT is connected to the data line DL and the source S of the TFT is connected to the pixel electrode CAT. The TFTs may be implemented by any one of an amorphous silicon (a-Si) transistor, a polycrystalline silicon transistor (LTPS), and an oxide transistor.

In order to simplify the structure of the TFT array and the electron-emitting device and to reduce the number of manufacturing processes, the TFT may be formed of a TFT of a top gate structure as shown in Fig. The gate insulating film GI insulates the electrodes so that the gate G of the TFT is not short-circuited with the source S and the drain D. [ The passivation layer (PASSI) covers the TFTs.

The pixel electrode CAT is connected to the source S of the TFT. The pixel electrode CAT is a cathode opposed to the anode ANO in the configuration of the electron-emitting device. A carbon nanotube bundle (CNTG) is formed on the pixel electrodes (CAT). The carbon nanotube bundles (CNTG) include carbon nanotubes (CNTs) formed on a seed metal pattern (SEED). Carbon nanotubes (CNTs) emit electrons when the voltage between the anode (AND) and the pixel electrode (CAT) is above the threshold voltage. The electrons are accelerated toward the anode ANO to excite the phosphor (PHOS) to emit the phosphor (PHOS).

According to the present invention, by vertically growing carbon nanotubes (CNTs) on a seed metal layer, the voltage applied to the cathode through the TFT can be precisely controlled, so that the gradation can be expressed by the data voltage applied to the cathode.

3 is a cross-sectional view illustrating a cross-sectional structure of a pixel according to an embodiment of the present invention.

Referring to FIG. 3, a first metal pattern is formed on a substrate SUBS. The first metal pattern is formed in the TFT region and the CNT region. The substrate SUBS may be made of a glass substrate, a ceramic substrate, a glass substrate, or the like. The present invention can form a first metal pattern by patterning metals such as Al / Mo, Al / Ta, Mo / W, Ta / Mo, and Cu by a photolithography process. The first metal pattern includes a source S and a drain D of the TFT, a data line DL, a data pad DP, and a pixel electrode CAT. The first metal pattern is about 2000 A (angstrom). The source S of the TFT is integrated with the pixel electrode CAT.

On the other hand, in a typical TFT-LCD, the pixel electrode uses indium tin oxide (ITO), but the present invention is formed of a metal such as a source and a drain of a TFT.

Next, the present invention deposits amorphous silicon, polysilicon, or silicon oxide on the TFT region and the CNT region to a thickness of a semiconductor material, for example, about 1000 A, and pattern the semiconductor layer by a photolithography process. As a result, a semiconductor channel layer (ACT) is formed on the TFT, and a diffusion barrier layer (BAR) is formed on the pixel electrode (CAT). The diffusion barrier layer (BAR) includes amorphous silicon or polysilicon. The diffusion barrier layer BAR is formed between the pixel electrode CAT and the seed metal layer SEED to prevent the seed metal from diffusing toward the pixel electrode CAT.

Next, an inorganic insulating material such as silicon nitride (SiNx) is deposited to a thickness of about 4000 A so as to cover the semiconductor pattern and the first metal pattern to form an insulating film GI, and the insulating film GI ) Is patterned to expose the diffusion barrier layer (BAR).

In the present invention, a metal such as Mo / Al, Al / Ta, Mo / Ta, Mo / W, or Cu is deposited on the TFT region and the metal is patterned by a photolithography process to form a second metal pattern. Nickel (Ni) is deposited to a thickness of about 200 to 400 A as a seed metal. The second metal pattern includes the gate G of the TFT, the gate line GL, the gate pad G, and the like. The seed metal is formed into a seed metal pattern (SEED) by a photolithography process or a laser scribing process with a small size of 5 μm 2 or less.

Then, the present invention forms an organic and / or inorganic protective film (PASSI) on the TFT region to cover the TFT and pattern the protective film (PASSI). The present invention then grows carbon nanotubes (CNTs) on a seed metal pattern (SEED). Carbon nanotubes (CNTs) can be grown on a seed metal pattern (SEED) in a PECVD (Plasma Enhanced Chemical Vapor Deposition Apparatus) process. The present invention exposes the pads GP, DP by etching a portion of the passivation film (PASSI) with a photolithographic process and an etching process.

Nickel silicide may be formed on the seed metal pattern SEED when nickel (Ni) is formed on the diffusion barrier layer (BAR) in a post-process. The grain (GR) of the nickel suicide layer acts as a seed of a single-crystal carbon nanotube (CNT). When monocrystalline carbon nanotubes grow on the nickel silicide, the monocrystalline carbon nanotubes (CNTs) can be vertically grown on the seed metal layer (SEED) with a conical structure that becomes sharp toward the top. When the single crystal carbon nanotube (CNT) grows with such a structure, electrons can be emitted even at a relatively low voltage, so that the electron emission efficiency is higher than that of the cylindrical carbon nanotube, and the threshold voltage for releasing electrons is lowered.

If the seed metal pattern (SEED) is large, the carbon nanotube (CNT) becomes thick and the height becomes low. In contrast, when the seed metal pattern (SEED) is small, the carbon nanotubes (CNTs) become thin and high and are effective in lowering the threshold voltage.

In the TFT array substrate, there is no separate electrode on the carbon nanotubes (CNT), for example, a gate electrode and a gate hole disposed on the electron emission source in the conventional field emission display. Therefore, the field emission display device of the present invention does not have a problem of alignment between the CNTs and the gate holes, and there is no fear that the CNTs and the gate electrodes disposed thereon are short-circuited.

A conventional field emission display of the CNT type operates in a triode structure, that is, a triode structure in which a gate is provided between a cathode (an emitter including CNTs) and an anode. On the other hand, the field emission display device of the present invention operates as a diode including a cathode (an emitter including a CNT) and an anode and no gate electrode therebetween. Therefore, in the field emission display of the present invention, the pixel is substantially the same as the diode in terms of an equivalent circuit.

It is possible to precisely control the electron emissive state according to the gray level value of the input image using the TFT formed for each pixel to express the gray level of the input image.

Electrons are emitted from the carbon nanotubes CNT when the voltage difference V between the anode ANO and the pixel electrode (or the cathode, CAT) is equal to or higher than the threshold voltage of the CNT, as shown in FIG. As the voltage difference (V) increases, the beam current (I) increases and the light emitting area increases, thereby representing a high gray scale. The gradation can be expressed according to a negative data signal applied to the pixel electrode CAT through the TFT. For example, when the anode voltage is constant, the lower the negative data voltage, the higher the beam current I and the higher gradation can be expressed. When the negative data voltage is lowered, the beam current I decreases, Lower.

The TFT array having such a structure is similar to the TFT array structure of the lower TFT of the TFT-LCD. Therefore, the field emission display device of the present invention can be manufactured in a production line of a TFT array of a liquid crystal display device.

Since a liquid crystal display device is not a self-light emitting device, a backlight unit (BLU) is required, and a polarizing plate and a color filter, which are respectively formed on an anode substrate and a cathode substrate, are required. On the other hand, the field emission display device of the present invention does not need a separate light source such as a backlight unit, and does not need a polarizing plate and a color filter.

On the other hand, the pixels of the LCD include the TFTs but are not connected to the cathodes of the diodes, and the data voltage is not supplied to the cathodes in the case of the OLED display. Therefore, the connection structure between the TFT and the pixel electrode of the present invention is completely different from that of the conventional LCD and OLED display.

A pixel of the field emission display device is applied with a high voltage. On the other hand, TFTs are semiconductor devices which are liable to be damaged at a high voltage. Particularly, when a high voltage is applied between the anode and the cathode, dielectric breakdown may occur in the TFT or be greatly damaged. In order to prevent this, the TFT of the present invention is manufactured with an asymmetric structure as shown in FIG.

5 is a cross-sectional view illustrating an asymmetric TFT structure according to an embodiment of the present invention. 6 and 7 are diagrams showing voltages applied between the anode and the cathode.

Referring to FIG. 5, the gate G of the TFT is vertically overlapped with either the drain D or the source S. When the TFT is implemented as an n-type MOSFET, the source S is connected to the pixel electrode CAT. In this case, the gate G is not vertically overlapped with the source S and is spaced apart by a preset offset distance d2. This is to prevent dielectric breakdown between the gate (G) and the source (S) when a high voltage is applied between the anode (ANO) and the pixel electrode (CAT or cathode). The offset distance d2 should be set larger than the thickness d1 of the insulating film GI. When the thickness of the insulating film GI is about 4000 A, the offset distance d is about 1 to 4 μm (or about 15,000 to 40,000 A). If the offset distance (d) is larger than 4 占 퐉, the on-resistance of the TFT becomes high, which may lead to power consumption and an increase in heat generation.

The voltage V applied between the anode ANO and the pixel electrode CAT can be expressed as V = V1 + V2 + V3 as shown in FIGS. V1 is a voltage applied to the vacuum space resistance R1, and V2 is a voltage applied to the carbon nanotube resistor R2. V3 is a voltage applied to the resistor R3 of the TFT. R1 is much larger than R2 and R3. Thus, if V2 and V3 are ignored, V can be viewed as V1. When the TFT is turned off, the resistance of the TFT becomes large and V3 instantaneously increases, so that the current between the gate G and the source I increases rapidly. As a result, insulation breakdown may occur between the gate G and the source S if the gap between the gate G and the source S in the TFT is small. The present invention can solve the problem that the TFT is damaged in the field emission display device by designing the TFT with an asymmetric structure in which the distance between the gate G and the source S is made longer as shown in Fig.

On the other hand, the TFT of the present invention is not limited to an n-type MOSFET. When the TFT is implemented as a p-type MOSFET, the pixel electrode CAT is connected to the drain D and the gate G is superposed only on the source S without overlapping with the drain D vertically.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUBS1, SUBS2: substrate ANO: anode
PHOS: phosphor CAT: pixel electrode (cathode)
BAR: diffusion barrier layer SEED: seed metal layer
CNT: Carbon nanotubes GI: Insulating film
PASSI: Shield

Claims

A field emission display device comprising an anode substrate including an anode and a phosphor, and a cathode substrate bonded to the anode substrate via a vacuum space,
The cathode substrate
A TFT (Thin Film Transistor) of a top gate structure;
An insulating film covering the drain and the source of the TFT and insulating the drain and the source from the gate of the TFT;
A pixel electrode connected to the TFT so as not to be vertically overlapped with the TFT;
A diffusion barrier layer formed on the pixel electrode;
A seed metal pattern formed on the diffusion barrier layer; And
And a carbon nanotube formed on the seed metal pattern,
The gate of the TFT is superimposed on either the drain or the source,
An electrode which is not vertically overlapped with the gate of the TFT among the drain and the source of the TFT is connected to the pixel electrode,
Wherein a distance between the gate and the gate of the TFT is not larger than the thickness of the insulating film.

The method according to claim 1,
Wherein the semiconductor channel layer of the TFT and the diffusion barrier layer comprise amorphous silicon or polysilicon,
Wherein the seed metal pattern comprises nickel silicide.

A method of manufacturing a field emission display device comprising an anode substrate including an anode and a phosphor, and a cathode substrate bonded to the anode substrate through a vacuum space,
The step of fabricating the cathode substrate may include:
Forming a source and a drain of the TFT and a pixel electrode integrated with the drain of the TFT in the first metal pattern;
Forming a gate insulating film covering the first metal pattern;
Forming a semiconductor pattern on the gate insulating layer to form a diffusion barrier layer on the semiconductor channel of the TFT and the pixel electrode;
Forming a gate of the TFT with a second metal pattern on the gate insulating film;
Forming a protective film covering the TFT;
Forming a seed metal pattern on the diffusion barrier layer; And
And forming carbon nanotubes on the seed metal pattern,
The gate of the TFT is vertically overlapped with either the drain or the source,
An electrode which is not vertically overlapped with the gate of the TFT among the drain and the source is connected to the pixel electrode,
Wherein the distance between the gate and the gate of the TFT is not larger than the thickness of the gate insulating film.

The method of claim 3,
Wherein the semiconductor channel layer of the TFT and the diffusion barrier layer comprise amorphous silicon or polysilicon,
Wherein the seed metal pattern comprises nickel silicide. &Lt; RTI ID = 0.0 > 15. < / RTI >

5. The method of claim 4,
Wherein forming the seed metal pattern on the diffusion barrier layer comprises:
Wherein the seed metal pattern is formed to a size of 5um2 or less by using a photolithography process or a laser scribing process.

The method according to claim 1,
Further comprising a protective film covering the TFT,
The insulating film and the protective film are located on the TFT,
Wherein the insulating film and the protective film are not formed on the pixel electrode, the diffusion barrier layer, the seed metal pattern, and the carbon nanotube.