KR101772593B1 - Analog-digital converter with self-reflecting the change in temperature environment - Google Patents

Abstract

Disclosed is an analog-digital converter for autonomously reflecting changes of an environment temperature. The analog-digital converter of the present invention comprises: an analog-digital converting unit which converts a converted analog voltage converts into digital output data; a band gap reference unit which generates a converting reference voltage, and adjusts a temperature dependency of a level of the converting reference voltage by means of controlling data; and a control unit which checks a first check data value, which is a data value of the digital output data generated in a first timing in a compensating mode, and a second check data value, which is a data value of the digital output data generated in a second timing in the compensating mode having a different environment temperature from the first timing in the compensating mode, and generates the controlling data. The analog-digital converter of the present invention minimizes time taken and costs and greatly improves a converting accuracy by reflecting autonomously changes of environment temperatures and adjusting levels of the converting reference voltages.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter (ADC)

The present invention relates to an analog-to-digital converter for converting an input of an analog component into an output of a digital component, and more particularly to an analog-to-digital converter having a high conversion accuracy by reflecting a change in ambient temperature.

Generally, an analog-to-digital converter is an apparatus that converts an input analog voltage of an analog component into digital output data of a digital component based on a conversion reference voltage, and is widely employed in a semiconductor chip. In such an analog-to-digital converter, a high conversion accuracy is required to allow the input analog voltage of the same level to always be converted into digital output data of the same data value.

On the other hand, the internal temperature of the semiconductor chip can be increased according to the operation. In this case, a change in the ambient temperature of the analog-digital converter employed in the semiconductor chip may occur, and conversion accuracy may be lowered. In order to prevent degradation of the conversion precision due to the change of the ambient temperature, a trimming technique is used in the conventional analog-to-digital converter.

However, conventional analog-to-digital converters using the trimming technique have a disadvantage in that they require a lot of time and cost because of a separate trimming operation.

It is an object of the present invention to provide an analog-to-digital converter that reflects changes in ambient temperature in order to minimize the time and cost.

According to an aspect of the present invention, there is provided an analog-to-digital converter. The analog-to-digital converter of the present invention provides an analog voltage supply that provides an input analog voltage that is received in the conversion mode as a converted analog voltage and a test voltage that is dependent on the temperature in the correction mode as the converted analog voltage. An analog-to-digital converter for converting the converted analog voltage into digital output data, wherein the data value of the digital output data is adjusted depending on a level of a conversion reference voltage; A bandgap reference unit for generating the conversion reference voltage, wherein the temperature dependence of the level of the conversion reference voltage is controlled by control data; And a second correction data value which is a data value of the digital output data generated at a first timing of the correction mode and a second correction data value which is generated at a second timing of the correction mode in which an environmental temperature is different from a first timing of the correction mode, And a control unit for generating the control data by checking a second confirmation data value which is a data value of the data, wherein the data value of the control data is adjusted depending on a magnitude relation between the first confirmation data value and the second confirmation data value And the control unit.

In the analog-to-digital converter of the present invention configured as described above, the first and second confirmation data values, which are the data values of the digital output data at the first timing and the second timing of the correction mode in which the environmental temperatures are different from each other, Is confirmed. At least one of the intensity of the positive temperature dependency and the intensity of the negative temperature dependency of the bandgap reference portion is adjusted based on the first confirmation data value and the second confirmation data value reflecting the environmental temperature. As a result, the level of the conversion reference voltage is adjusted within the allowable range in the operating temperature range by itself.

Thus, according to the analog converter of the present invention, since the change in the ambient temperature is reflected in itself, and the level of the converted reference voltage is adjusted, the conversion time and cost are minimized, and the conversion accuracy is greatly improved.

A brief description of each drawing used in the present invention is provided.
1 is a view for explaining a voltage for driving an analog-to-digital converter of the present invention embedded in a semiconductor chip.
2 is a block diagram schematically illustrating an analog-to-digital converter of the present invention.
3 is a detailed view of the analog voltage supply unit of FIG.
4 is a diagram for explaining that the data value of the digital output data in the analog-to-digital converter of the present invention depends on the level of the converted reference voltage.
5 is a detailed view of the analog-to-digital converter of FIG.
6 is a view showing an example of the bandgap reference portion 300 of FIG.
FIG. 7 is a diagram for explaining the temperature dependency of the conversion reference voltage generated in the bandgap reference portion of FIG. 6; FIG.
FIG. 8 is a detailed view of the control unit of FIG. 2. FIG.
9 is a diagram showing a preferred example of the converted voltage width generating unit of Fig.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

It should be noted that, in understanding each of the drawings, the same members are denoted by the same reference numerals whenever possible. Further, detailed descriptions of known functions and configurations that may be unnecessarily obscured by the gist of the present invention are omitted.

In describing the contents of the present invention throughout the specification, the meaning of the terms 'connected' and 'connected' among individual components is not limited to direct connection, It also includes all connections. Also, a plurality of expressions for each component may be omitted.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The analog-to-digital converter (ADC) of the present invention can be embedded in the semiconductor chip (SECH) as shown in Fig. At this time, the analog-to-digital converter (ADC) of the present invention can be driven by the power supply voltage VDD which is different from the chip power voltage VCPW driving the semiconductor chip SECH.

Therefore, the analog-to-digital converter (ADC) of the present invention can be used not only in an on state in which the chip power voltage VCPW is supplied but also in an off state in which supply of the chip power voltage VCPW is interrupted It is driveable.

2 is a block diagram schematically illustrating an analog-to-digital converter (ADC) of the present invention.

In this specification, the operation of the analog-to-digital converter (ADC) of the present invention is roughly divided into two modes. First, the conversion mode is a mode for converting an input analog voltage VANGN received from the outside into digital output data DOUT. The correction mode is a mode for confirming the conversion precision of the analog-to-digital converter (ADC) of the present invention, and has a first timing and a second timing.

Generally, the internal temperature of the semiconductor chip SECH increases as the chip power voltage VCPW is supplied and driven.

In this case, the internal temperature of the semiconductor chip (SECH), that is, the ambient temperature of the ADC of the present invention is set such that the chip power voltage (VCPW) on state to an off state.

In this specification, a substantial time generated by switching the chip power voltage VCPW from an on state to an off state may be referred to as the 'first timing' of the correction mode.

That is, the 'first timing' is an environment temperature in a sufficiently heated state, and is considered to have the highest environmental temperature in the range of interest.

In Fig. 2, the OFF response signal POFF is active during the first timing of the correction mode.

The internal temperature of the semiconductor chip SECH may be set such that the chip power voltage VCPW is turned off after a predetermined time elapses from when the chip power voltage VCPW is off, And when it is switched from the off state to the on state, it is relatively low.

In this specification, the chip power voltage VCPW is switched from off to on for a considerable period of time after a certain period of time has elapsed or when the chip power voltage VCPW is switched from on to off May be referred to as the " second timing " of the correction mode.

That is, the 'second timing' is regarded as the environmental temperature in a sufficiently cooled state and has the lowest environmental temperature in the range of interest.

In Fig. 2, the ON response signal PON is active during the second timing of the correction mode.

2, the analog-to-digital converter of the present invention includes an analog voltage supplier 100, an analog-to-digital converter 200, a bandgap reference unit 300, and a controller 400.

The analog voltage providing unit 100 provides the input analog voltage VANGN received in the conversion mode as the converted analog voltage VANGC and the test voltage VMS in the correction mode as the converted analog voltage VANGC .

At this time, the test voltage VMS maintains a relatively constant level with respect to a change in temperature.

In the present embodiment, the mode signal XMOD is inactivated from "conversion mode" to "L" and activated from "correction mode" to "H". That is, the mode signal XMOD is activated to "H" when the OFF response signal POFF or the ON response signal PON is activated to "H"

FIG. 3 is a view showing the analog voltage supplier 100 of FIG. 2 in detail. Referring to FIG. 3, the analog voltage providing unit 100 includes a test voltage generating unit 110 and an analog voltage selecting unit 130.

The test voltage generating unit 110 generates the test voltage VMS and is preferably composed of resistors 111 and 113 having a resistance value proportional to each other. The test voltage VMS generated in the test voltage generating unit 110 may have a constant level irrespective of changes in ambient temperature.

The analog voltage selection unit 130 selects the input analog voltage VANGN as the converted analog voltage VANGC in the conversion mode and the converted analog voltage VANGC as the test voltage VMS in the correction mode, .

That is, at the first timing and the second timing of the correction mode, the level of the converted analog voltage VANGC is controlled by the test voltage VMS.

Referring again to FIG. 2, the analog-to-digital converter 200 converts the converted analog voltage VANGC into digital output data DOUT and outputs the digital output data DOUT. At this time, the data value of the digital output data DOUT depends on the level of the conversion reference voltage VRFC, as shown in Fig.

For example, with respect to the converted analog voltage VANGC of the test voltage (VMS) level, when the level of the conversion reference voltage VRFC is the target voltage Vtar, (DA0). However, when the level of the conversion reference voltage VRFC is greater than the target voltage Vtar, the digital output data DOUT is converted to the reference data value VANGC with respect to the converted analog voltage VANGC of the test voltage VMS level. (DA-) smaller than the data value DA-. When the level of the conversion reference voltage VRFC is smaller than the target voltage Vtar, the digital output data DOUT is set to the reference data value VANGC for the converted analog voltage VANGC of the test voltage VMS level. (DA +) larger than the data value DA0.

Thus, the magnitude relation of the level of the conversion reference voltage VRFC with respect to the target voltage Vtar can be confirmed through the data value of the digital output data DOUT.

5 is a view showing the analog-digital converter 200 of FIG. 2 in detail. Referring to FIG. 5, the analog-to-digital converter 200 includes a converted voltage width generating unit 210 and an analog-to-digital converting unit 230.

The converted voltage width generating unit 210 generates a converted minimum voltage VMIN and a converted maximum voltage VMAX. At this time, the level of the conversion minimum voltage VMIN and the conversion maximum voltage VMAX are determined to be dependent on the level of the conversion reference voltage VRFC. The level difference between the converted minimum voltage VMIN and the converted maximum voltage VMAX increases with an increase in the level of the converted reference voltage VRFC.

The analog-to-digital conversion unit 230 converts the level of the converted analog voltage VANGC into a data value of the digital output data DOUT. At this time, the level of the converted minimum voltage VMIN serves as the level of the converted analog voltage VANGC for generating the digital output data DOUT having the minimum data value, and the converted maximum voltage VMAX is And the level of the converted analog voltage VANGC for generating the digital output data DOUT having the maximum data value.

Referring back to FIG. 2, the bandgap reference unit 300 generates a conversion reference voltage VRFC. At this time, the temperature dependency of the level of the conversion reference voltage VRFC is controlled by the control data DCON.

The temperature dependence of the level of the conversion reference voltage VRFC is determined by a combination of a positive temperature dependence (MPST) positively correlated with a change in ambient temperature and a negative temperature dependency (MNGT) negatively correlated with a change in environmental temperature .

At least one of the intensity of the positive temperature dependency (MPST) and the intensity of the negative temperature dependency (MNGT) is controlled by the control data (DCON).

Subsequently, the temperature dependency of the level of the conversion reference voltage VRFC provided by the bandgap reference portion 100 and the adjustment by the temperature dependency control data DCON will be described in more detail.

6 is a view showing an example of the bandgap reference portion 300 of FIG. The bandgap reference unit 300 includes first, second and third resistors 310, 320 and 330 and first and second PNP bipolar transistors 340 and 350 and an operational amplifier 360 . At this time, the first resistor 310 has a resistance value R1 which is varied by the control data DCON and is formed between the conversion reference voltage VRFC and the first preliminary terminal NPRE1. The second resistor 320 has a fixed resistance value R2 and is formed between the conversion reference voltage VRFC and the second preliminary terminal NPRE2. The third resistor 330 has a fixed resistance value R3 and is formed between the second spare terminal NPRE2 and the collector terminal of the second PNP bipolar transistor 350. [

The base terminal and the collector terminal of the first PNP bipolar transistor 340 are commonly connected to the ground voltage VSS and the emitter terminal of the first PNP bipolar transistor 340 is connected to the first preliminary terminal NPRE1 . The base terminal and the collector terminal of the second PNP bipolar transistor 350 are commonly connected to the ground voltage VSS and the emitter terminal of the second PNP bipolar transistor 350 is connected to the second preliminary terminal NPRE2 Respectively. The emitter terminal of the second PNP bipolar transistor 350 is connected to the second preliminary terminal NPRE2.

At this time, it is assumed that the current density flowing through the second PNP bipolar transistor 350 is k times the current density flowing through the first PNP bipolar transistor 340.

The operational amplifier 360 includes a positive input terminal connected to the first preliminary terminal NPRE1, a negative input terminal connected to the second preliminary terminal NPRE2 and a negative input terminal connected to the converted reference voltage VRFC, As shown in Fig.

The level of the conversion reference voltage VRFC having the above configuration is expressed by Equation (1).

(1)

VRFC = Veb2 + (1 + R2 / R3) * Vt * ln (k * m)

    = MNGT + MPGT

Here, Veb2 is the voltage difference of the emitter terminal to the base terminal of the second PNP bipolar transistor 150, and Vt is the thermal voltage.

And m is R2 / R1.

At this time, since 'Veb2' has a negative correlation with a change in ambient temperature, 'Veb2' can be expressed as negative temperature dependency (MNGT). (1 + R2 / R3) * Vt * ln (k * m) can be expressed as a positive temperature dependency (MPST) since the above-mentioned 'Vt' has a positive correlation with the change of the environmental temperature. And, the intensity of the positive temperature dependency (MPST) depends on the change of the value of m. That is, the intensity of the positive temperature dependency (MPST) increases as the value of m increases.

In order to confirm the effect of the present invention, it is assumed that the value of m in the bandgap reference unit 300 is fixed.

In an ideal case, the bandgap reference part 300 has an intensity of a proper positive temperature dependency and a negative temperature dependency, and the conversion reference voltage (VRFC) of a stable level of the allowable margin range with respect to a change in the temperature range of interest (See Fig. 7 (a)).

However, due to changes in process conditions and the like, the intensity of the positive temperature dependency and / or the intensity of the negative temperature dependency of the bandgap reference portion 300 may be changed to a non-ideal state as intended.

If the intensity of the negative temperature dependency is higher than the reference temperature dependency, the level of the conversion reference voltage VRFC goes down from the higher environmental temperature to the allowable margin range (see (b ) Reference)

If the intensity of the negative temperature dependency is lower than the reference temperature dependency, the level of the conversion reference voltage VRFC is lowered from the lower ambient temperature to the allowable margin range (see FIG. 7 (c)

When the level of the conversion reference voltage VRFC provided by the band gap reference unit 300 deviates from the allowable margin range with respect to a change in the temperature change of interest (see (b) and (c) of FIG. 7) The conversion accuracy of the analog-to-digital converter employing the band gap reference portion 300 is lowered.

In the band gap reference unit 300 of FIG. 6, the value m is controlled by the control data DCON. In this embodiment, the value of m is adjusted in the direction of increasing as the control data DCON increases. As a result, the intensity of the positive temperature dependency (MPST) of the level of the conversion reference voltage VRFC is adjusted to increase in accordance with the increase of the control data DCON.

Accordingly, the converted reference voltage VRFC in the analog-to-digital converter of the present invention is adjusted by the control data DCON so as to allow the change in the temperature range of interest again as shown in FIG. 7 (a) And is controlled to a stable level of the margin range.

Referring back to FIG. 2, the controller 400 checks the first confirmation data value FDA1 and the second confirmation data FDA2 to generate the control data DCON. Here, the first confirmation data value FDA1 is a data value of the digital output data DOUT generated at the first timing of the correction mode, and the second confirmation data value FDA1 is a data value of the second output data DOUT Is the data value of the digital output data DOUT generated at the timing.

At this time, the data value of the control data DCON is adjusted depending on the magnitude relationship between the first confirmation data value FDA1 and the second confirmation data value FDA2.

For example, assume that the first confirmation data value FDA1 is larger than the second confirmation data value FDA2. In this case, the level of the conversion reference voltage VRFC at the first timing is lower than the level of the conversion reference voltage VRFC at the second timing.

That is, the intensity of the positive temperature dependency of the level of the conversion reference voltage VRFC generated in the bandgap reference unit 300 is lower than the intensity of the negative temperature dependency.

In this case, the controller 400 checks the first confirmation data value FDA1 and the second confirmation data FDA2 to increase the data value of the control data DCON.

As a result, the m value increases so that the intensity of the positive temperature dependence of the level of the conversion reference voltage VRFC is in a proper relationship with the intensity of the negative temperature dependency.

On the contrary, it is assumed that the first confirmation data value FDA1 is smaller than the second confirmation data value FDA2. In this case, the level of the conversion reference voltage VRFC at the first timing is higher than the level of the conversion reference voltage VRFC at the second timing.

That is, the intensity of the positive temperature dependency of the level of the conversion reference voltage VRFC generated in the bandgap reference unit 300 is higher than the intensity of the negative temperature dependency.

In this case, the controller 400 checks the first confirmation data value FDA1 and the second confirmation data FDA2 to reduce the data value of the control data DCON.

As a result, the value of m is decreased such that the intensity of the positive temperature dependency of the level of the conversion reference voltage VRFC is in a proper relationship with the intensity of the negative temperature dependency.

Subsequently, the control unit 400 is described in detail.

FIG. 8 is a view showing the control unit 400 of FIG. 2 in detail. Referring to FIG. 8, the controller 400 includes an up-down signal generating unit 410 and a control data storage unit 430.

The up-down signal generating unit 410 generates an up signal UP and a down signal DN. At this time, any one of the up signal UP and the down signal DN is activated when the first confirmation data value FDA1 is greater than the second confirmation data value FDA2. Any one of the up signal UP and the down signal DN is activated when the first confirmation data value FDA1 is smaller than the second confirmation data value FDA2.

The up signal UP is activated when the first confirmation data value FDA1 is larger than the second confirmation data value FDA2 and the down signal DN is activated when the first confirmation data value FDA1 FDA1) is smaller than the second confirmation data value (FDA2).

The up-down signal generating unit 410 specifically includes flip-flop means 411 and up-down signal generating means 413. The flip flop means 411 stores the first confirmation data value FDA1 generated at the first timing of the correction mode and the second confirmation data value FDA2 generated at the second timing of the correction mode.

In this embodiment, the flip-flop means 411 includes a first flip-flop 411a and a second flip-flop 411b. The first flip flop 411a stores the first confirmation data value FDA1 in response to the occurrence of the clock CLK during the first timing of the correction mode in which the OFF response signal POFF is active. The second flip flop 411b stores the second confirmation data value FDA2 in response to the occurrence of the clock CLK during the second timing of the correction mode in which the ON response signal PON is active .

The up-down signal generating means 413 confirms the first confirmation data value FDA1 and the second confirmation data value FDA2 stored in the flip-flop means 411 and outputs the up signal UP and the down- And generates a signal DN.

The control data storage unit 430 stores the control data DCON and may be implemented as a semiconductor memory. At this time, the control data DCON is increased in response to the activation of the up signal UP, and is decreased in response to the activation of the down signal DN. If both of the up signal UP and the down signal DN are in the inactive state, the previous data value of the control data DCON is maintained.

In summary, in the above-described analog-to-digital converter of the present invention, the first confirmation data value FDA1, which is the data value of the digital output data DOUT at the first timing and the second timing of the correction mode, And the second confirmation data value FDA2 are confirmed. At least one of the intensity of the positive temperature dependence and the intensity of the negative temperature dependency of the bandgap reference portion 300 is determined based on the first confirmation data value FDA1 and the second confirmation data value FDA2, . As a result, the level of the conversion reference voltage VRFC is adjusted within the allowable range in the use temperature range by itself.

Thus, according to the analog converter of the present invention, since the change in the ambient temperature is reflected in itself, and the level of the converted reference voltage is adjusted, the conversion time and cost are minimized, and the conversion accuracy is greatly improved.

On the other hand, according to a more preferred embodiment, the converted voltage width generating unit 210 of the analog-digital converter 200 is controlled by the control data DCON as shown in Fig. It is considered that the level of the conversion reference voltage VRFC can be changed by the control data DCON.

At this time, the level of the conversion reference voltage VRFC according to the control data DCON can be obtained by calculating from the above-mentioned (Equation 1).

Subsequently, the converted voltage width generating unit 210 of FIG. 9 will be described in detail.

9, the converted voltage width generating unit 210 includes first to third amplifiers 211 to 213, a driving transistor 214, a source resistor 215, a resistor string 216, and a node selector 217).

The first amplifier 211 receives the conversion reference voltage VRFC as a negative input terminal. The second amplifier 212 has a positive input terminal connected to a maximum node NMAX and a negative input terminal connected to an output terminal providing the converted maximum voltage VMAX. The third amplifier 213 has a positive input terminal connected to the minimum node NMIN and a negative input terminal connected to the output terminal providing the converted minimum voltage VMIN .

The driving transistor 214 is formed between the power supply voltage VDD and the maximum node NMAX and is controlled by the output terminal of the first amplifier 211. The source resistance 215 is formed between the ground voltage VSS and the minimum node NMIN.

The resistor string 216 includes a plurality of resistors RS1 to RSn formed in series between the maximum node NMAX and the minimum node NMIN.

The node selector 217 selects a node between the plurality of resistors RS1 through RSn included in the resistor string 216 as a positive input terminal of the first amplifier 211, And a plurality of selection switches MSW1 to MSW (n-1) for connecting the selection switches MSW1 to MSW (n-1). At this time, a node between the plurality of resistors (RS1 to RSn) of the resistor string 216 connected to the positive input terminal of the first amplifier 211 is determined by the control data DCON do.

9, the level of the converted minimum voltage VMIN and the converted maximum voltage VMAX are adjusted by the control data DCON.

Thus, the converted minimum voltage VMIN and the converted maximum voltage VMAX may be determined to compensate for the influence of the level of the conversion reference voltage VRFC by the control data DCON.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

For example, in the present specification, an embodiment has been shown and described in which a converted analog voltage is provided directly to the analog-to-digital conversion section. However, the technical idea of the present invention is not limited to the embodiment in which the converted analog voltage is directly provided to the analog-to-digital conversion section, but also to the analog-to-digital conversion section indirectly provided through other analog circuits such as a buffer, a level shifter, It will be apparent to those skilled in the art.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (8)

In an analog-to-digital converter,
An analog voltage supplier for providing a received input analog voltage as a converted analog voltage in the conversion mode and providing the converted test voltage as the converted analog voltage in the correction mode;
An analog-to-digital converter for converting the converted analog voltage into digital output data, wherein the data value of the digital output data is adjusted depending on a level of a conversion reference voltage;
A bandgap reference unit for generating the conversion reference voltage, wherein the temperature dependence of the level of the conversion reference voltage is controlled by control data; And
Wherein the digital output data generated at the second timing of the correction mode in which the first check data value is the data value of the digital output data generated at the first timing of the correction mode and the first timing of the correction mode is different from the environmental temperature, And a control data generating unit generating the control data by checking a second confirmation data value which is a data value of the control data, wherein the data value of the control data is adjusted depending on a magnitude relation between the first confirmation data value and the second confirmation data value And a control unit,
The analog-to-digital converter
A converted voltage width generating unit for generating a converted minimum voltage and a converted maximum voltage, wherein the converted minimum voltage and the converted maximum voltage have a level that is dependent on the level of the converted reference voltage;
And an analog-to-digital conversion unit for converting the converted analog voltage into the digital output data, wherein the data value of the digital output data is dependent on the converted minimum voltage and the level of the converted maximum voltage And an analog-to-digital converter.
The apparatus as claimed in claim 1, wherein the analog voltage supplier
A test voltage generating unit for generating the test voltage; And
And an analog voltage selection unit for selecting the input analog voltage as the converted analog voltage in the conversion mode and selecting the converted analog voltage as the test voltage in the correction mode.
delete The method as claimed in claim 1, wherein the converted minimum voltage and the converted maximum voltage generated in the converted voltage width generating unit
Wherein the control data is adjusted by the control data to compensate for the influence of the change in the level of the conversion reference voltage by the control data.
The method according to claim 1,
The temperature dependency of the level of the conversion reference voltage provided in the bandgap reference portion
A positive temperature dependency positively correlated to a change in the environmental temperature and a negative temperature dependency negatively correlated to a change in the environmental temperature,
At least one of the intensity of the positive temperature dependency and the intensity of the negative temperature dependency
Wherein the control data is controlled by the control data.
The apparatus of claim 1, wherein the control unit
Up signal and a down signal, wherein one of the up signal and the down signal is activated when the first confirmation data value is larger than the second confirmation data value, and the up signal and the down signal are activated when the first confirmation data value is greater than the second confirmation data value, Wherein the other one of the signals is activated when the first confirmation data value is smaller than the second confirmation data value; And
And a control data storage unit for storing the control data, wherein the data value of the control data is increased in response to activation of the up signal and is decreased in response to activation of the down signal To-analog converters.
7. The apparatus of claim 6, wherein the up-down signal generating unit
Flip flop means for storing the first confirmation data value and the second confirmation data value; And
And an up-down signal generating means for generating the up signal and the down signal by checking the first confirmation data value and the second confirmation data value stored in the flip-flop means.
2. The apparatus of claim 1, wherein the analog-to-digital converter
The semiconductor integrated circuit device is embedded in a semiconductor chip driven by ON of a chip power voltage and is also drivable when the chip power voltage is OFF,
The first timing of the correction mode
And in response to a transition of the chip power voltage from an on state to an off state,
The second timing of the correction mode
And in response to a transition from an off state to an on state of the chip power voltage.

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