JPH09321376A - Semiconductor laser controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the optical output by forming an error amplifier for controlling the forward current of a semiconductor laser and a current drive section for feeding a drive current corresponding to an emission command signal, as a forward current, to the semiconductor laser on one chip of an integrated circuit. SOLUTION: An optoelectric feedback loop 6 is formed by connecting a semiconductor laser 3 and a light receiving element 4 in loop while including an error amplifier 8. Output from the semiconductor laser 3 is monitored by the light receiving element 4 and the forward current of the semiconductor laser 3 is controlled such that the optical output is equal to an emission command signal IDA1 generated from a pulse width generating/data modulating section 2. A constant current source 7 functions to feed the semiconductor laser 3 with a forward driving current corresponding to an emission command signal IDA2 generated from the pulse width generating/data modulating section 2. Consequently, the optical output from the semiconductor laser 3 can be controlled basically by the sum (or the difference) of a control current from the optoelectric feedback loop 6 and the driving current from the constant current source 7. The modulating section 2 and the driving section 5 are integrated on one chip.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a laser printer,
The present invention relates to a semiconductor laser control device for driving and controlling a semiconductor laser used as a light source in a digital copying machine, an optical disc device, an optical communication device and the like.

[0002]

2. Description of the Related Art A semiconductor laser is extremely small in size and can be directly modulated at a high speed by a driving current, so that it has been widely used in recent years as a light source for a laser printer or the like.

However, the relationship between the driving current of the semiconductor laser and the light output changes remarkably with temperature, which is a problem when the light intensity of the semiconductor laser is set to a desired value. In order to solve this problem and utilize the advantages of the semiconductor laser, as one of the APC (Automatic Power Control) methods, the light output of the semiconductor laser is monitored by a light receiving element, and the light output of the semiconductor laser generated in the light receiving element is monitored. The optical output of the semiconductor laser is always set to a desired value by an optical / electrical negative feedback loop that controls the forward current of the semiconductor laser so that the signal proportional to the received light current and the light emission level command signal are equal. Control methods are known. In this case, the control speed is limited due to the limitation of the operation speed of the light receiving element and the operation speed of the amplification element forming the optical / electrical negative feedback loop.

[0004] An improved system in consideration of this point has been proposed in, for example, Japanese Patent Application Laid-Open No. 2-205086. According to the publication, an optical / electrical negative feedback loop that constantly controls the forward current of the semiconductor laser so that the optical output of the semiconductor laser is monitored by the light receiving element and the output is equal to the emission level command signal. Conversion means for converting the light emission level command signal into a forward current of the semiconductor laser.
A method is disclosed in which the optical output of a semiconductor laser is controlled by the sum or difference of the control current of the electric negative feedback loop and the current generated by the conversion means. Here, the optical / electrical negative feedback loop includes, for example, a semiconductor laser, a light receiving element, a constant current source, and an error amplifier. The conversion means is constituted by, for example, a constant current source.

According to this, when the optical output corresponding to the current for directly driving the semiconductor laser by the conversion means is P _S , the step response characteristic of the optical output of the semiconductor laser is P _out = P ₀ + (P _S −P ₀ ) ｛1-exp (−2πf ₀ t
)｝ P _out ; light output of the semiconductor laser P ₀ ; set light intensity of the semiconductor laser t; time f ₀ ; crossover frequency in the open loop of the optical / electrical negative feedback loop. If P _S ≒ P _0, the optical output of the semiconductor laser instantly becomes equal to P _0, the value of f ₀ may be is seen smaller than in the case of only optical and electrical negative feedback loop. In reality, it suffices that f ₀ = 40 MHz or so, and a cross frequency of this degree can be easily realized.

In Japanese Patent Application Laid-Open No. 5-67833, the components described in the above-mentioned Japanese Patent Application Laid-Open No. 2-2005086 are disclosed by using an IC using a bipolar transistor to form a light / electric negative feedback loop. The points that facilitate the design are described.

Next, a description will be given of the history of the one-dot multi-value conversion technique using a laser printer as an example. The laser printer was originally developed as a non-impact printer that replaces the line printer, but due to the high speed and high resolution of the laser printer, its application as an image printer was considered from an early stage, and various recording methods based on the dither method were put into practical use. Has been converted. Also, due to the rapid progress of semiconductor technology in recent years, the amount of information that can be processed has increased rapidly, and in the laser printer, the one-dot multi-valued technology has been put into practical use, and while firmly solidifying its position as an image printer. is there. However, the current multi-valued level has an output level equivalent to 8 bits in a high-end machine, but is suppressed to a numerical value at most in a low-end machine. This is due to the large amount of information, which is mainly due to the fact that the circuit size of the semiconductor laser control modulator for realizing the one-dot multi-value output is large and expensive.

[0008] Currently, as a semiconductor laser control modulation system for performing multi-valued output of one dot, there are A.I. Light intensity modulation method B. Pulse width modulation method C. A pulse width intensity mixing method has been proposed.

A. Light intensity modulation method (PM = Power Modu
This is a method of recording by changing the light output itself, and since halftone recording is realized by using the intermediate exposure area, stabilization of the printing process is an important requirement, and the demand for the printing process becomes strict. However, control modulation of the semiconductor laser becomes easy.

B. Pulse width modulation method (PWM = Pulse
Width Modulation) Although the light output level is binary, it is a method of recording by changing the light emission time (that is, pulse width), so the intermediate exposure area is less utilized than the PM method, and By combining adjacent dots, it is possible to further reduce the intermediate exposure area (requirement for stability of the printing process is reduced). However, when the pulse width is set to 8 bits and the adjacent dot combination is realized, the structure of the semiconductor laser control modulator becomes complicated.

C. Pulse width intensity mixed modulation method (PWM +
PM method) The PM method has a strict requirement for stabilization of the printing process, and the PWM method has a problem that the semiconductor laser control modulator is complicated. Therefore, the PM method and the PWM method are combined. , For example, JP-A-6-3
It is disclosed in Japanese Patent No. 47852.

This modulation method is basically a binary recording method, which is based on a PWM method which is stable to a printing process, and compensates for a transition between pulses by a PM method. This modulation method reduces the number of required pulse widths and power values when combined to achieve the same number of gradations, compared to individual modulation methods. In addition to being stable to the printing process and suitable for integration, it is possible to achieve downsizing and cost reduction. In order to realize such a modulation method, the semiconductor laser control device is provided with a pulse width generation unit and a data modulation unit that receive image data and a pixel clock, and the pulse width generation unit and the data modulation unit It is configured to output a light emission level command signal to the laser controller and the semiconductor laser driver. That is, the PWM method is used as a basis by the pulse width generation unit and the data modulation unit according to the input image data, and the transition part is supplemented by the PM method.

In this case, in order to more specifically realize the pulse width intensity mixed modulation method within one dot, the C-MO
There is a proposal to easily form a pulse width generation unit by using an IC using an S device and to easily design an optical / electrical negative feedback loop unit by using an IC using a bipolar transistor.
This is described in Japanese Patent Application Laid-Open No. Hei 6-347852.

[0014]

However, according to the method disclosed in Japanese Unexamined Patent Publication No. 6-347852, a current adding method for reducing the control amount by the optical / electrical negative feedback loop and a pulse width within one dot are also used. There is still room for improvement in realizing the intensity mixing modulation system with a configuration that has a higher degree of integration so as to achieve a smaller size and power saving, and to operate at higher speed and higher accuracy.

[0015]

According to the first aspect of the present invention,
A pulse width modulation / intensity modulation signal generation unit that generates a light emission command signal that simultaneously performs pulse width modulation and intensity modulation on the input data based on the input data, a semiconductor laser, and an optical output of the semiconductor laser is monitored. A light receiving element proportional to the optical output of the semiconductor laser obtained from the light receiving element and the light emission command obtained from the pulse width modulation / intensity modulation signal generating section In order to control the driving of the semiconductor laser by the sum or difference current of the error amplification unit that controls the forward current of the semiconductor laser so that the signals become equal to each other, and the control current of the optical / electrical negative feedback loop. A drive current corresponding to the light emission command signal generated and supplied from the pulse width modulation / intensity modulation signal generation unit is passed as a forward current to the semiconductor laser. A flow drive unit is constituted by a one-chip integrated circuit.

Therefore, everything from the digital control system, which is the pulse width modulation / intensity modulation signal generation section, to the analog drive system, such as the error amplification section and the current drive section, is configured as a one-chip integrated circuit. In addition to power saving, the pulse width intensity mixed modulation method within one dot can be realized at higher speed and higher accuracy.

Here, regarding the pulse width modulation / intensity modulation signal generation section, in the invention described in claim 2, the data conversion means for converting the input data into the pulse width modulation data and the intensity modulation data, and the pulse width modulation data. Pulse width modulation means for generating a plurality of pulses pulse width modulated based on;
It has a light emission command signal generating section for simultaneously performing pulse width modulation and intensity modulation for the semiconductor laser based on the outputs of these data conversion means and pulse width modulation means. Therefore, it becomes clear that the pulse width modulation / intensity modulation signal generating section forming the digital control system is integrated into one chip.

According to the third aspect of the invention, since the one-chip integrated circuit is formed by the bipolar transistor, it becomes easy to construct an analog drive system amplifier such as an error amplifying section or a current driving section. , The input level can be set freely and the input level can be lowered.

According to the invention of claim 4, since the one-chip integrated circuit is formed by the C-MOS transistor, it becomes easy to construct the pulse width modulation / intensity modulation signal generation section side in particular. Also, the degree of integration can be increased.

According to the invention of claim 5, since the one-chip integrated circuit is formed by a hybrid circuit of a bipolar transistor and a C-MOS transistor, an analog drive system such as an error amplifying section or a current driving section is particularly used. Can be easily configured with bipolar transistors, and a digital control system such as a pulse width modulation / intensity modulation signal generator can be used.
It can be easily configured with MOS transistors, and circuit design becomes easy.

[0021]

FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIG. The semiconductor laser control device of the present invention is applied as a control device including an optical / electrical negative feedback loop for controlling the optical output of a semiconductor laser used for optical writing in a laser printer or the like. Further, as a method for obtaining multi-gradation output within one dot, the pulse width intensity mixed modulation method (PWM + PM method) described in the above-mentioned publications is used.

In order to realize such a modulation system, the semiconductor laser control device 1 according to the present embodiment basically generates a light emission command signal by inputting image data and an input clock as shown in FIG. A pulse width generation unit and a data modulation unit (hereinafter, abbreviated as pulse width generation / data modulation unit) 2 are provided. Further, the semiconductor laser 3 is provided with a light receiving element 4 for monitoring its optical output. The semiconductor laser 3 and the light receiving element 4 are a semiconductor laser controller and a semiconductor laser driver (hereinafter, semiconductor laser controller Drive unit) 5. The light emission command signal generated by the pulse width generation / data modulation unit 2 is given to the semiconductor laser control / drive unit 5. That is, according to the input image data, the pulse width generation / data modulation unit 2 uses the PWM system as a basic tone, and the transition portion is compensated by the PM system.

A basic conceptual diagram of the light output waveform of the semiconductor laser 3 is shown in FIG. FIG. 3 shows the semiconductor laser 3 in the case of outputting a total of 18 gradations of 3 values of pulse width and 6 values of power.
2 schematically shows the optical output waveform of the above. Since this modulation method is basically a PWM method as shown in the figure, the intensity modulation unit using the intermediate exposure area needs to output with a minimum pulse width. In order to obtain such an optical output, for example, assuming that the pulse width is T as shown in FIG. 4, two pulses of T shown in pulse 1 and (T + ΔT) shown in pulse 2 or pulse 3 are shown. T and ΔT (Δ
T is the minimum pulse width) and two pulses may be generated. T
When all the bits are set to the H level in the pulse of and the bits are turned on / off according to the data in the pulse of ΔT, the waveform of the optical output as shown in FIGS. 3 and 4 can be obtained. FIG. 4A shows a left-aligned optical waveform, and FIG. 4B shows a right-aligned optical waveform.

Next, a more specific block diagram configuration of the semiconductor laser control device 1 of the present embodiment will be described with reference to FIG. First, the semiconductor laser control / drive unit 5 includes an optical / electrical negative feedback loop 6 and a constant current source 7 forming a current drive unit.
It is composed of The optical / electrical negative feedback loop 6
Is formed including the semiconductor laser 3 and the light receiving element 4, and an error amplifier 8 which is connected to the semiconductor laser 3 and the light receiving element 4 in a loop and constitutes an error amplifying section. The optical / electrical negative feedback loop 6 monitors the light output of the semiconductor laser 3 by the light receiving element 4, and the light output and the light emission command signal (I _DA1 ) generated by the pulse width generation / data modulator 2 are equal. So that the forward current of the semiconductor laser 3 is controlled at all times. Further, the constant current source 7 functions so as to flow a drive current according to the light emission command signal (V _DA2 ) generated by the pulse width generation / data modulation unit 2 in the forward direction of the semiconductor laser 3. As a result, in the semiconductor laser control / driving unit 5, the optical output of the semiconductor laser 3 is basically generated by the sum (or difference) of the control current of the optical / electrical negative feedback loop 6 and the driving current of the constant current source 7. Controlled by.

According to this, when the optical output corresponding to the current for directly driving the semiconductor laser 3 by the constant current source 7 is P _S , the step response characteristic of the optical output of the semiconductor laser 3 is as described above. _{out = P 0 + (P S} -P 0) {1-exp (-2πf 0 t
)} P _out ; optical output of the semiconductor laser 3 P ₀ ; set light intensity of the semiconductor laser 3 t; time f ₀ ; crossover frequency in open loop of the optical / electrical negative feedback loop 6 is approximated. If P _s ≒ P ₀ , the optical output of the semiconductor laser 3 instantaneously becomes equal to P _0, and the value of f ₀ is
It can be seen that it may be smaller than in the case of only the electric negative feedback loop 6. In reality, it suffices that f ₀ = 40 MHz or so, and a cross frequency of this degree can be easily realized. While FIG. 5A shows how the optical output changes when only the optical / electrical negative feedback loop 6 is used, FIG. 5B shows the case where the constant current component I _DA2 is added by the constant current source 7. The change in the optical output of is shown, and it can be seen that it is converted into a more rectangular wave.

With regard to the semiconductor laser control device 1 having such a function, in this embodiment, the pulse width generation / data modulation section 2 and the semiconductor laser control / drive section 5 are integrated into a one-chip integrated circuit 9 by bipolar transistors. It is integrated. Here, although the optical / electrical negative feedback loop 6 portion including the error amplifier 8 is not particularly shown, for example, by using a well-known bipolar transistor circuit as shown in FIG. Can be integrated. Also, regarding the constant current source 7 part,
Although not shown in particular, it can be integrated by using a well-known bipolar transistor circuit as shown in FIGS. 13 and 17 of JP-A-5-67833.

Therefore, here, a more specific structure and operation of the pulse width generation / data modulation section 2 side in the integrated circuit 9 will be described below. Now, in the present embodiment,
3 bits for pulse width modulation (ie 8 levels), 5 for intensity modulation
The configuration example is such that bits (that is, 32 values) are combined and a total of 8-bit gradation (256 values) can be output per dot. The pulse width generation / data modulation unit 2 includes a pulse width modulation / intensity modulation signal generation unit 11 and a light emission command signal generation unit 1
2 is constituted.

First, as shown in FIG. 6, the light emission command signal generator 12 produces the current I according to the intensity modulation data PMD.
_DA , / I _DA ("/" indicates inversion with respect to the signal;
D / A converter (DAC) 13 for converting the same)
And a differential switch 14a that switches whether to pass the current / I _DA according to the pulse 1, and a differential switch 1 that switches whether to pass the current I _DA according to the pulse 2.
And 4b, differential switch 14a, 14b current / I _DA flowing accordance switching, current converting each voltage / V _DA, the V _DA and I _DA - consists voltage converter (I-V) 15a, a, 15b There is. Here, / I _DA + I _DA = I _full
In a relationship. The current value I _full is the intensity modulation data PMD
_Is the value of the current I _DA when all are turned on, and is the maximum current value of the light emission command signal. Differential switch 14a, 14b
I _DA1 = I when both pulses 1 and 2 are at H level
_Works to be _full . When the pulse 1 is at the L level and the pulse 2 is at the H level, I _DA1 = I _DA . When both pulses 1 and 2 are at the L level, I _DA1 = 0.
That is, when both pulses 1 and 2 are at the H level, I _DA
I _DA1 regardless of the value of (that is, intensity modulation data PMD)
= I _full . Therefore, the intensity modulation data PMD may be constant for one pixel clock. As a result, this is advantageous in increasing the speed of the semiconductor laser control device.

Such differential switches 14a and 14b are constructed by differentially connecting a pair of bipolar transistors, for example. Current-voltage converter 15
a, 15b is supplied as emission command signal two voltage values (V _DA2, / V _DA2) the voltage V _DA2 as shown in FIG. 1 with respect to the constant current source 7. The constant current source 7 generates the current I _DA2 according to the difference voltage between the two voltage values of the light emission command signal V _DA2 . Such current-voltage converters 15a and 15b
Is also composed of, for example, bipolar transistors whose bases are grounded. Therefore, the light emission command signal generator 12 itself is easily integrated and formed as a bipolar transistor configuration.

On the other hand, the pulse width modulation / intensity modulation signal generation unit 11 in the pulse width generation / data modulation unit 2 includes, for example, a data conversion unit 16 serving as data conversion means and a pulse width modulation unit serving as pulse width modulation means. 17 and a pulse generation oscillator 18 having a PLL configuration. And said pulse generating oscillator 18 internal clock X ₀ is synchronized with the input clock, as shown in FIG. 8, the X ₀ and the same frequency (i.e.,
A plurality of pulses having the same frequency with the input clock) and having a constant phase difference of pulses X ₁ , X ₂ , ..., Xk having different phase differences are generated. When the pulse width modulation is 8-valued, k = 7, and the phase difference of each pulse is 1/8 · T.
_CK (T _CK is the cycle of the input clock). Also, X ₄ ,
X ₅ , X ₆ and X ₇ are inversion signals of X ₀ , X ₁ , X ₂ and X ₃ , respectively. Here, the pulse to be synchronized with the input clock may be either, and synchronizes the pulse X ₆ in FIG. 8, the internal clock X ₀ which is delayed by 1/4 period from the input clock. The data converter 16 has a function of converting the input image data into pulse width modulation data PWMDATA and intensity modulation data PMDATA. The pulse width modulation unit 17 has a function of generating two pulses PW _on and PW _da from the output X _k of the pulse generation oscillator 18 according to the pulse width modulation data PWMDATA obtained from the data conversion unit 16.

For example, the logic for obtaining the left-aligned optical output waveform will be described with reference to FIG.

[0032]

[Equation 1]

Further, D _n1 , D _n2 , D _m1 , D _m2 , D _n1 ′,
D _n2 ′, D _m1 ′ and D _m2 ′ are pulse width modulated data PWMDA
TA, image data D ₇ (MSB) to D ₀ (LSB)
Of these, if the upper 3 bits, that is, D ₇ , D ₆ , and D ₅ are data for pulse width modulation, they are expressed by equation (3).

[0034]

[Equation 2]

In order to realize such a logic, the data converter 16 and the pulse width modulator 17 are constructed as shown in FIG. 7, for example. First, in the data conversion unit 16, the image data D _{0 to} D ₇ are respectively converted into pulse width modulation data D _ni and D.
A logic unit 21 for converting _ni ′, D _mj , and D _mj ′ according to the equation (3).
~ 24 are provided. 25 is image data D _{0 to} D ₇
This is a logic unit that outputs the lower 5 bits of data as it is as intensity modulation data D _pk . These logic units 21
25 to 25 have means (for example, a latch) for holding the modulated data. On the other hand, in the pulse width modulator 17, multiplexers 26 to select one of the pulses X _k according to the pulse width modulation data D _ni , D _ni ′, D _mj and D _mj ′.
29 are provided. Further, the output X _n of multiplexers 26 to 29, X _n the AND gate 30a~30d to perform ', X _m, X _m' logic (1) with respect to
And OR gates 30e and 30f are provided. OR
The output of the gate 30e is a pulse PW _da , and the OR gate 30f
Output becomes a pulse PW _on . The data conversion unit 16 and the pulse width modulation unit 17 which mainly perform such logic can also be configured by being integrated with bipolar transistors.

In this way, according to the present embodiment,
Since the pulse width generation / data modulation unit 2 and the semiconductor laser control / driving unit 5 are all integrated as a one-chip integrated circuit 9 by bipolar transistors, the pulse width modulation / intensity modulation mixed method within one dot can be used. In controlling the driving of the semiconductor laser 3 by taking into consideration the optical / electrical negative feedback loop 6 + addition current value control method, it is possible to achieve small size and power saving, and all is processed in the integrated circuit 9 of one chip. It can operate at higher speed and with higher accuracy. In particular, by forming the integrated circuit 9 of one chip and the bipolar transistor, it becomes easy to configure an analog drive system amplifier such as the error amplifier 8 and the constant current source 7, and the input level thereof can be freely set. In addition, the input level can be reduced. Therefore, it is convenient for improving the functions of the laser printer and the like.

A second embodiment of the present invention will be described with reference to FIGS. 9 to 25. Even in the present embodiment, basically, the pulse width / intensity mixed modulation method as in the above-described embodiment, or the optical / electrical negative feedback loop + summing current value control method for reducing the burden on the optical / electrical negative feedback loop ,
The same parts as those shown in FIGS. 1 to 8 are designated by the same reference numerals. That is, the semiconductor laser control device 1 according to the present embodiment also has a pulse width generation / data modulation unit 2 and a semiconductor laser control / drive unit 5 as shown in FIG.
It is composed of

FIG. 9 shows a more detailed configuration example of the semiconductor laser control device 1 according to the present embodiment. In the present embodiment, the pulse width modulation / intensity modulation signal generation unit 31 and the semiconductor laser control / driving unit 5 that generate a plurality of pulses by converting the input data into pulse width modulation data and intensity modulation data are one of them. Most of the elements except the constituent elements are integrated and configured as a one-chip integrated circuit 32. More specifically, as illustrated with respect to a part of the circuit configuration, it is integrated into one chip with bipolar transistors. In particular, this embodiment clarifies an example of this bipolar transistor configuration.

First, the semiconductor laser control / drive section 5 side will be described. The optical / electrical negative feedback loop 6 includes a light emission command signal setting unit 41, a light emission command signal generation unit 42, and an error amplifier 4.
3, the current driver 44, the semiconductor laser 3, and the light receiving element 4. The light emission command signal generation unit 42 includes a light emission command signal generation unit first configuration unit 42a and a light emission command signal generation unit second configuration unit 42b. As the operation, the semiconductor laser 3 and the current generated by the first configuration unit 42a of the light emission command signal generation unit according to the modulated data are operated.
Is compared with the monitor current output from the light receiving element 4 in proportion to the optical output of the semiconductor laser 3, and the error is converted into the forward current of the semiconductor laser 3 via the error amplifier 43 and the current driver 44. The monitor current is the light emission command signal generation unit first constituent unit 42a.
When the monitor current is smaller than the current generated by the light emission command signal generating section first component 42a, the forward current of the semiconductor laser 3 is decreased. To control. An optical / electrical negative feedback loop 6 is formed here.

In general, there are variations in the differential quantum efficiency of the semiconductor laser 3 and the light-electric conversion light receiving sensitivity of the light receiving element 4. Therefore, it is necessary to set the current value according to each characteristic. Regarding such element variations, in the light emission command signal setting section 41, a current value I _DA1 , that is, a light receiving element in terms of direct current operation, is set by an external current setting signal so that the semiconductor laser 3 has a desired optical output. By setting the monitor current value _IPD of 4, it is possible to absorb individual differences and set the semiconductor laser 3 to always have a desired optical output.

The current driver 44 is configured as a high-speed voltage shifter 45 which instantaneously shifts the output of the error amplifier 43 by a desired potential by a differential switch configuration, for example. The voltage shift by the high-speed voltage shift unit 45 instantly becomes the forward current of the semiconductor laser 3, and the optical output of the semiconductor laser 3 can be modulated at high speed. In particular, by having the high-speed voltage shift section 45 functioning as the current drive section 44 in the control system of the optical / electrical negative feedback loop 6 and having the same output section as the optical / electrical negative feedback loop 6 side, This is advantageous in reducing the number of elements of the integrated circuit 32 and reducing the power consumption.

FIG. 10 shows an example of the circuit configuration using the bipolar transistors of the error amplifier 43 and the high speed voltage shift section 45. First, the light emission command signal generation unit 42 from the PD terminal
A monitor current I _PD flowing through the light receiving element 4 is supplied to the base of the transistor Q _{1 in} the (emission command signal generator first constituent part 42a) in proportion to the optical output of the semiconductor laser 3. A D / A conversion unit, which will be described later, in the light emission command signal generation unit 42 converts the input data into a current I _DA1 and causes this current I _DA1 to flow from the base of the transistor Q ₁ . The result of the comparison between the currents I _PD and I _DA1 is detected at the base of the transistor Q ₁ . The result is input to the differential amplifier 51 composed of the transistors Q ₂ , Q _3, etc., and the output of the differential amplifier 51 is input to the base of the drive transistor 52. The drive transistor 52 causes a forward current to flow through the semiconductor laser 3 via the resistor Re. An optical / electrical negative feedback loop 6 is formed here. Between the differential amplifier 51 and the LD terminal of the semiconductor laser 3, a differential switch 53 including transistors Q ₄ , Q ₅ , a resistor R _{2 and the} like and forming a differential circuit is connected. The differential switch 53 or the driving transistor 52 constitutes a high-speed voltage shift unit 45 that instantaneously shifts a desired potential. This voltage shift instantaneously becomes a forward current of the semiconductor laser 3 via the emitter follower 54 composed of the transistors Q ₆ , Q ₇ and the transistor 52.

Here, in the present embodiment, as described above, the drive transistor 52 that finally drives the semiconductor laser 3 and the resistor R _e are externally attached to the integrated circuit 32. This drive transistor 52 and resistor R _e
Is several tens to several hundreds mA for driving the semiconductor laser 3.
It is necessary to pass a certain amount of current. However, in the case of the configuration of this embodiment, the current in the semiconductor laser control / driving unit 5 is sufficient to be several mA at the most in the output unit connected to the driving unit (driving transistor 52). Therefore, power consumption is reduced and integration (development of LSI) is facilitated. In the circuit shown in FIG. 10, the current driver 44
It is the resistors R ₂ , R ₃ and
The transistor Q _{9 and the} like. However, as described above, there are element variations in the differential quantum efficiency of the semiconductor laser 3,
In addition, there is a deterioration in efficiency due to changes over time. Therefore, the differential quantum efficiency of the semiconductor laser 3 is detected by the differential quantum efficiency detection unit 46, and this voltage shift amount is set. As a result, the optical output P _S as shown in FIG.
It is possible to obtain an ideal optical output in which

Further, in the circuit shown in FIG. 10, the differential amplifier 51 composed of the transistors Q ₂ , Q _3, etc. constitutes its output as a voltage drop from the power supply voltage V _{cc at the} resistor R ₄ . Since the optical / electrical negative feedback loop 6 controls the optical output of the semiconductor laser 3 in real time, it also controls the power supply voltage fluctuation. In addition, in the process of inputting to the differential amplifier 51 the result detected at the PD terminal (base potential of the transistor Q _{1 in} the light emission command signal generation unit first constituent portion 42a), the transistors Q ₁₁ , Q ₁₂ and the resistor R are connected. Feedback is being made via ₆ , and this differential amplifier 51
The voltage gain of is determined by the resistance values of resistors R ₅ and R ₆ ,
Reduce the gain. As a result, this differential amplifier 51
And the control speed is improved.
Here, the resistors R ₅ and R ₆ are external elements. The control speed of the control system (optical / electrical negative feedback loop 6) can be varied by changing the resistance values of these resistors R ₅ and R ₆ .

The differential quantum efficiency of the semiconductor laser 3 is detected,
In FIG. 9, the block for realizing the function of setting the voltage shift amount is configured by the timing generation unit 47, the differential quantum efficiency detection unit 46, the memory unit 48, and the addition current setting unit 49. As a result, the timing generator 47 generates a timing signal that is sufficiently slower than the control speed of the error amplifier 43. At that timing, the differential quantum efficiency of the semiconductor laser 3 is detected by the differential quantum efficiency detector 46. The detection result is recorded in the memory unit 48. The current value of the addition current setting unit 49 is set according to the data in the memory unit 48. These operations are performed as an initialization operation only at a predetermined initialization such as when the power is turned on or when the power is reset (when the optical output of the semiconductor laser 3 is turned off). During normal operation, the current value of the added current setting unit 49 is held. Further, in the integrated circuit 32, a power supply unit 101 is provided together with a startup unit 50 connected to the timing generation unit 47.

Next, FIGS. 11 and 12 show examples of circuit configurations using bipolar transistors in the light emission command signal setting section 41 and the light emission command signal generation section 42.

First, as the configuration of the light emission command signal setting unit 41, the current setting of the light emission command signal generation unit 42, the current setting of the addition current setting unit 49, the base current compensation unit of the current of the light emission command signal generation unit 42, and , And the current of the light emission command signal generation unit 42 and the current of the addition current setting unit 49 are interlocked with each other to adjust from an external signal, and each part will be described with reference to a circuit example shown in FIG.

The current of the light emission command signal generator 42 is set by the emitter potential of the transistor Q ₇₁ and the resistor R ₄₁ . Here, the current I of the light emission command signal generation unit 42
_DA1 is the direct current because it is monitoring current I _PD of the light receiving element 4, it is necessary to make the integrated circuit 32 (LSI) current that is not affected by the internal temperature variation. That is, the emitter potential of the transistor Q ₇₁ needs to be a stable potential, and the resistor R ₄₁ needs to be a resistor requiring absolute accuracy. For this reason, the emitter potential of the transistor Q ₇₁ is the stable potential generated in the power supply section, and the VREF 11 terminal potential is the same as that of the transistors Q _{72 to} Q _75.
It is generated via a voltage follower 55 composed of Then, the VR terminal is used as an external terminal, and the resistor R ₄₁ is an external resistor or a variable resistor having good absolute accuracy and temperature characteristics. By changing the resistance value of the resistor R ₄₁ , it is possible to adjust the characteristics of the semiconductor laser 3 and the light receiving element 4 to obtain a desired light output.

The current setting of the addition current setting section 49 is determined by the emitter potential of the transistor Q ₇₈ and the resistor R ₄₂ ,
Output from the IDA2SET terminal to the addition current setting section 49. Here, the emitter potential of the transistor Q ₇₈ is the transistor Q
_Since the emitter potential of ₇₁ is almost the same as the emitter potential of transistor ₇₁ , the emitter potential of transistor Q ₇₁ is equal to that of transistors Q ₇₁ , Q ₇₆ ,
It is converted to the emitter potential of the transistor Q ₇₈ through Q ₇₇ and Q ₇₈ .

The base current of the light emission command signal generator 42 is compensated by the base current of the transistor Q ₇₇ . The current I _DA1 of the light emission command signal generation unit 42 needs to be the current I _PD , that is, the absolute current determined by the external light receiving element 4 as described above. Here, for example, in the case of the circuit configuration example shown in FIG. 11, the reference current determined by the emitter potential of the transistor Q ₇₁ and the resistor R ₄₁ is an absolute current. Therefore, this reference current is inverted by the current mirror circuit 56 and then flows as a current I _{DA 1} from the PD terminal through some transistors. A base current error of each transistor occurs while passing through several transistors. Such a base current error occurs at each bit (b0, b1, b2, b3, b4) in the 5-bit D / A converter. The base current amount of the transistor Q ₇₇ is adjusted to compensate for such a base current error. That is, in the case of the circuit configuration of the present embodiment, the generation of an error current due to the base current and the characteristic change are suppressed by adding the number of transistors passing through the base current of the reference current to the reference current. This makes it possible to easily perform base current compensation.

The circuit configuration shown in FIG. 12 is related to the block diagram shown in FIG. Referring to FIG. 6, the current I _DA includes a D / A converter 13 including a plurality of transistors, a differential switch 14b including a switching transistor, and a current-voltage converter (I / V) including a transistor.
Converter) 15b. As described above, the base current error that occurs while the current I _DA passes through the plurality of transistors in each of these parts is compensated.

Next, a portion for adjusting the current of the light emission command signal generating section 42 and the current of the addition current setting section 49 in accordance with an external signal will be described. As described above, the current setting of the light emission command signal generating unit 42 and the current setting of the addition current setting unit 49 are determined by the emitter potential of the transistor Q ₇₁ and the resistor R ₄₁ . Further, as described above, the emitter potential of the transistor Q ₇₁ receives the VREF 11 terminal potential as an input and is the output of the voltage follower 55 composed of the transistors Q _{72 to} Q ₇₅ and the like. Therefore, the control voltage (external voltage) is input from the VCONT terminal through the resistors R ₄₃ and R ₄₄ and the transistor Q ₇₉ in parallel with the VREF 11 terminal, and the emitter potential of the transistor Q ₇₁ is changed by this control voltage. Let That is, the light emission command signal generation unit 4
It is possible to increase or decrease the current of No. 2 and the current of the addition current setting unit 49 in conjunction with each other. Therefore, the variable optical output by the optical / electrical negative feedback loop and the variable optical output by the added current value control system can be interlocked. As a result, the changed waveform of the optical output can be corrected to a waveform approximate to a rectangular waveform as in the case shown in FIG.

Next, the light emission command signal generator 42 will be described with reference to FIG. This light emission command signal generator 4
2 is D / of 5 bits (b0, b1, b2, b3, b4)
It is configured to include an A converter and a current addition drive unit.
The 5-bit digital data converted from a digital signal to an analog signal by the D / A converter in the light emission command signal generation unit 42 is the PWM & PM signal generation unit 3 shown in FIG.
1 to PMDATA (light intensity modulation signal).

However, if it is necessary to set the optical output with higher accuracy, the number of bits of the D / A converter may be increased. Alternatively, if the main purpose is pulse width modulation,
The number of bits of the D / A converter may be reduced. In the present embodiment, the D / A converter is composed of a combination of a current mirror circuit and a resistance ladder, but an equivalent modification is allowed as appropriate.

The current addition drive unit detects the current I _DA1 and its inversion current by the emitter potentials of the transistors Q ₈₁ and Q ₈₂ , passes through the emitter followers Q ₈₃ and Q _84, and then the transistors Q ₄ and Q _5. To the base of. Since the emitter potentials of the transistors Q ₈₁ and Q ₈₂ are potentials that directly reflect the current value of I _DA1 , the differential switch 53 including the transistors Q ₄ and Q ₅ is turned on / off as shown in FIG. D / A converter 5 instead of the binary output of
When it is composed of bits, a 5-bit current drive output can be obtained at high speed.

Next, FIG. 13 illustrates a more specific configuration example of the pulse width modulation / intensity modulation signal generation unit 31 side in the integrated circuit 32. In the present embodiment, the pulse width modulation is 3 bits (that is, 8 values), and the intensity modulation is 5 bits (that is, 32 values).
8 bits per dot (2
56 value) is output. The pulse width modulation / intensity modulation signal generation unit 31 includes, for example, the data conversion unit 6
1, a pulse width modulation unit 62, and a pulse generation oscillator 63 having a PLL configuration. Since these configurations are similar to the configurations shown in FIG. 1 in the first embodiment, details thereof will be omitted.

Here, the structure of the input portion of the integrated circuit 32 to which the image data D _{0 to} D ₇ are input is shown in FIG.
This will be described with reference to (a) and FIG. 14 (b). In the integrated circuit 32 having a bipolar transistor configuration, an ECL (Emitter Coupled Logic) is provided at an input section of a data conversion section 61 to which image data is input, as shown in FIG.
A circuit 71 is provided. In this ECL circuit 71, the emitters of two pairs of transistors Q _a and Q _b are differentially connected to each other, and a constant current source 72 is connected to these emitters.
Is connected. Here, the ECL circuit 71 is V with respect to the base potentials V _a and V _b of the transistors Q _a and Q _b.
If the value of _a− V _b is about ± 200 mV, it has a characteristic that the logic holds. Therefore, for example, when the value of the potential V _b is fixed, the potential V _a is V _a ≧ V _b +200 mV
Alternatively, V _a ≦ V _b −200 mV, and ± 250 mV may be taken into consideration in consideration of variations. As a result, 500 mV is sufficient as the voltage swing amount of V _a .

The image data input to the integrated circuit 32 corresponding to the ECL circuit 71 exhibiting such peculiarity has a normal voltage swing amount of 0-5V, for example, the above-mentioned 0-5V.
It is configured to be extremely reduced to 00 mV and input. Specifically, as shown in FIG. 14A, a resistor R _a is provided on a transmission line such as a harness 73 to which image data having a voltage swing amount of 0 to 5 V is input, and the transmission line and a power source having a voltage of 5 V. A resistor R _b is provided between the terminal and the resistor R _b.
The resistance ratio of _a and R _b is set to about 9: 1 (for example, R _a = 1.5 kΩ, R _b = 165 Ω). Such a circuit constitutes the impedance matching circuit 74.

According to such a configuration, when the image data input to the resistor R _a shows a voltage swing amount of 0-5 V, the potential at the connection point (input point) between the transmission line and the resistor R _b is the resistance. It shows 4.5-5V depending on the resistance ratio of R _a and R _b . Therefore, the voltage swing at this connection point is 0-500mV
Is reduced to 1/10 and input to the ECL circuit 71 side in the integrated circuit 32. Here, with respect to the time constant τ, τ =
Considering CR = C · (V / I), if the input voltage swing amount is reduced and the current is the same, the time constant τ
Apparently, it can be made smaller. That is, the speed of data transfer can be increased. In fact, 70
Higher speed is possible up to about 80 MHz. Also, by reducing the voltage swing amount and inputting it in this way, the driving amount also decreases, and the energy is reduced to about 1/100.
Since it is extremely reduced, it is not only advantageous for power saving, but also advantageous for EMI countermeasures. Furthermore, such an input section is configured as an impedance matching circuit 74, and reflection of input data hardly occurs.

In constructing the input section by the impedance matching circuit 74, the resistor R _b may be connected to the ground side as shown in FIG. 14 (b).

When the original image data has a pulse waveform of the potential V as shown in FIG. 15A, this pulse waveform is a positive logic waveform of the potential V / 2 as shown in FIG. 15B. It is also possible to divide the signal into a combination with a negative logic (inverted logic) waveform of the potential V / 2 as shown in FIG. More specifically, a signal based on a positive logic waveform as shown in FIG. 15B is input to the transistor Q _a side of the ECL circuit 71,
A signal based on a negative logic waveform as shown in FIG.
It suffices to input it to the transistor Q _b side of the CL circuit 71 and obtain a differential output of both. In this case,
The transmission line is the same as the input transistor in the constant current source connected to the bases of the transistors Q _a and Q _b . In other words, considering the amount of voltage swing at the input point described above, the combination of positive logic and negative logic results in 250
A swing amount of mV is sufficient.

According to such an input method, the energy is ∝ (voltage) ^2. Therefore, if a single image data as shown in FIG. It is reduced to 1/4 of that of the method (a). Also, even when noise is involved, the noise has a similar effect on both positive logic and negative logic signals, and its differential output is taken. As a result, the noise component is canceled out. It becomes a data transfer input method that is resistant to noise.

In this way, according to the present embodiment,
Since the pulse width modulation / intensity modulation signal generation unit 31 and the semiconductor laser control / drive unit 5 are all integrated as a one-chip integrated circuit 32 by bipolar transistors,
Light for pulse width modulation / intensity modulation mixed method within 1 dot
Electric negative feedback loop 6 + additional current value control method (Fig. 5 (a)
And FIG. 5B), the drive of the semiconductor laser 3 is controlled and the power consumption can be reduced, and all the processing is performed in the one-chip integrated circuit 32. It can function with precision.

The timing generator 47 can be constructed by using, for example, a delay circuit, but in this embodiment, as shown in more detail in FIG. 16, an oscillator circuit 81 and a bias circuit (not shown). No.) and a latch circuit 82. In general, by latching the oscillation signal generated in the oscillation circuit 81 by the latch circuit 82 and sequentially transmitting the latched data to the next stage, for example,
Six timing signals T0 to T5 are generated, and the oscillation circuit 81 is forcibly prevented from oscillating at the same time as the final timing.

The differential quantum efficiency detecting section 46 is, for example, a sample hold circuit 83 for detecting the peak value in the error output of the error amplifier 43, and the sample hold circuit 8.
3 and the comparator 84 for comparing the output value of 3 with a predetermined value.

The memory section 48 compares the comparison result of the comparator 84 with the timing T1 generated by the timing generation section 47.
It has a function of holding in synchronization with T5. The addition current setting unit 49 is composed of, for example, a 5-bit D / A converter 85.

Next, the structure and operation of each of these parts will be described.
Will be explained. First, the bipolar transistor of the oscillation circuit 81.
FIG. 17 shows an example of the circuit configuration of the transistor. Also, Ini
FIG. 20 shows a schematic operation at the time of sharing. Transistor
Q_{twenty two}Collector potential V_Q22C(TDSTART pin voltage) is a figure
It is represented as an oscillation operation in 20. This transistor Q
_{twenty two}The collector current of the transistor Q_{twenty four}, Q_{twenty five}Composed of
The differential switch 86 is turned on and off. example
If transistor Q_{twenty two}When the collector current of the
Register Q_{twenty one}If it is larger than the collector current of
Langista Q_{twenty two}Collector potential V_Q22CAs a result,
Capacitor C₁ Is the transistor Q_{twenty one}, Q_{twenty two}Collector power
It is discharged as a current difference between the flows. Meanwhile, the tiger
Register Q _{twenty two}When the collector current of is off
Q_{twenty two}Collector potential V_Q22CAs a result,
Sa C₁ Is transistor Q_{twenty one}Depending on the collector current of
Is displayed. Thus the capacitor C₁ Charge, de
Oscillates by repeating the charge.

First, at the timing 0 shown in FIG. 20, that is, from the time the power is turned on until the oscillation start timing signal TS is sent from the start-up unit 50.
The potential of the TDSTART terminal is forcibly H level (almost the same potential as _Vcc ), and the VPTDSTART terminal is 0V. Therefore, the transistor Q ₂₃ generated from the VPTDSTART pin
Has a collector current of 0, and the transistor Q _{25 of} the differential switch 86 is also at the L level. However, since the collector current of the transistor Q ₂₃ is 0, the collector current of the transistor Q ₂₂ is also 0.

Referring to FIG. 19 showing the configuration of the final stage of the latch circuit 82, the potential of the VPTDSTART terminal is 0.
V, the collector current of the transistor Q ₃₁ is 0A. As a result, the base potential of the transistor Q ₂₃ is V _cc ,
The collector current of the transistor Q ₂₃ becomes 0A. Also,
In the differential switch 86, the collector current of the transistor Q ₂₃ is 0 A and the base potential of the transistor Q ₂₅ is at L level, so the collector current of the transistor Q ₂₂ is 0 A.

After that, when the oscillation start timing signal TS passes, the potential of the VPTDSTART terminal becomes H level.
The collector current of the transistor Q ₂₂ begins to flow. In the differential switch 86, since the transistor Q ₂₅ is at L level, the collector current of the transistor Q ₂₃ flows through the transistor Q ₂₆ . At this time, the transistor Q _{22 is} passed through the current mirror circuit 87 including the transistors Q ₂₆ and Q _22.
The same current flows through This timing TS, the collector current of the transistor Q ₂₂ is the collector potential V _Q22C transistor Q ₂₂ when the collector current is larger than the transistor Q _21, i.e., TDSTART terminal potential is gradually lowered. Then, at the moment when the base potential of the transistor Q ₂₄ becomes equal to or lower than the base potential of the transistor Q ₂₅ , the differential switch 86 operates and the transistor Q ₂₄
Is turned on, the collector current of the transistor Q ₂₆ , and therefore the collector current of the transistor Q ₂₂ is turned off, and the base potential of the transistor Q ₂₅ rises by the potential determined by the collector current of the transistor Q ₂₄ and the resistor R ₁₁ . This moment is timing T0.

After timing T0, the collector current of the transistor Q ₂₂ is turned off, so that the transistor Q ₂₂ is turned off.
₂₂ collector potential V _Q22C , that is, the TDSTART terminal potential is
Gradually rise. Then, at the moment when the base potential of the transistor Q ₂₄ is equal to or higher than the base potential of the transistor Q ₂₅ , the differential switch 86 is inverted and the collector current of the transistor Q ₂₂ is turned on. In this way, the oscillation operation is repeated. The amplitude of this oscillation is determined by the potential determined by the collector current of the transistor Q ₂₄ and the resistance R ₁₁ . The period is determined by the collector current of the transistor Q _21, the collector current of the transistor Q ₂₂ , and the capacitance of the capacitor C ₁ . A desired timing signal can be obtained by appropriately determining these values.

In such operation, the transistor Q
_When the collector current of ₂₂ is just twice the collector current of transistor Q ₂₁ , the collector current of transistor Q ₂₁
(Collector current of transistor Q ₂₂ ) − (Collector current of transistor Q ₂₁ ) becomes equal, and the amount of charge per unit time charged and discharged in the capacitor C ₁ becomes equal. Therefore, as shown in FIG. 20, a triangular wave having the same rise time and fall time is obtained.

A square wave is obtained at the base of the transistor Q ₂₅ as the oscillating output of the oscillating circuit 81, and the voltage shift, swing amount adjustment, and inversion processing are performed, and then the emitter of the transistor Q _X (not shown). An output waveform of the potential V _QXE is obtained. The waveform of the emitter potential V _QXE is obtained by conversion using the two-level signal a triangular waveform of the collector potential V _Q22C is well known.

Next, FIG. 18 shows a circuit configuration example of the latch circuit 88 which is one structural unit of the latch circuit 82. In the present embodiment, the latch circuit 82 generates the timing signals T0 to T5.
It is configured by being connected to a stage. Latch circuit 8 shown in FIG.
Reference numeral 8 is an example of one constitutional unit for generating the timing signal T0. In the illustrated example, a plurality of transistors and resistors are configured as constituent elements. Among them, the transistors Q _{31 to} Q ₃₃ form one switch 89a, and the transistors Q _{34 to} Q ₃₆ form one switch 89a. The switch 89b is formed. In the switch 89a, the collector current of the transistor Q ₃₃ when asserted, the base potential of the transistor Q _31, i.e., the input data is inverted to the base potential and the emitter potential of the transistor Q ₃₇ outputs. In the switch 89b, the transistor Q
_When the collector current of the transistor ₃₆ is on, the base of the transistor Q ₃₄ is connected to the emitter of the transistor Q ₃₇ , so that the output is maintained as it is.

When the base of the transistor Q ₃₃ is CLK, the base of the transistor Q ₃₆ is / CLK, the base of the transistor Q ₃₁ is DATA 0, and the emitter of the transistor Q ₃₇ is the output Q, the relation between them can be expressed by a logical expression: Q = CLK / DATA0 + / CLK / Q.

Here, as described above, the transistor Q _X
The emitter potential V _{QX E} (see FIG. 20), that is, the base / CLK of the transistor Q ₃₆ is in the output holding state at the H level from the timing TS to the timing T0. Also,
The current source 90 composed of transistors Q ₃₈ , Q _39, etc.
The current flows up to the timing TS from the moment when the current is 0 and the timing TS is reached. Base of transistor Q ₃₆ / CL
Since K is at H level and the output Q is in the output holding state, the output Q is at H level until the timing T0. At timing T0, since / CLK (= V _QXE ) is at L level and the base input of the transistor Q ₃₁ is DATA0, the output Q becomes L level for the first time, and after timing T0, the base (input data) of the transistor Q ₃₁ becomes Since it is at L level, the output Q holds the L level state. This state is referred to as the emitter potential V _Q37E of the transistor Q ₃₇ in FIG.
It is shown as a waveform of (timing signal T0).

In the next stage (not shown), CLK is inverted and input,
_Assuming that the emitter potential V _Q37E of the transistor Q ₃₇ is DATA1, Q '= / _{CLK.multidot.DATA1} + _{CLK.multidot.Q} ', so that the timing signal T1 shown by _{V.sub.Q37 (1) E} in FIG. 20 can be obtained. Actually, the switch 89a of the latch circuit of the next stage outputs the input data DATA1 (L level) at the timing of the rising edge of / CLK, and since the input data DATA1 is held at the L level, the L level output is held. It

Thereafter, the timing signals T2 to T5 can be similarly obtained. “N” in V _{Q3 7 (n) E} in FIG. 20 indicates the number of stages 1 to 5.

Further, as shown in FIG. 19, in the final stage latch circuit 88 _L for generating the timing signal T5, the collector current of the transistor Q ₃₁ is given to the base of the transistor Q ₂₃ in the oscillator circuit 81. The voltage is set to drive the oscillation circuit 81. Therefore, the base potential of the transistor Q ₂₃ is supplied from the timing TS to the timing T5. However, transistor Q
The base potential of ₂₃ is not supplied with turning off the collector current of the transistor Q ₂₃ at the moment when the timing T5.

That is, by oscillating only while the required timing signal is generated and stopping the oscillation at the same time when the desired timing signal is generated, the oscillation operation of the oscillation circuit 81 causes the other circuits to perform noise and current fluctuations. It has a circuit configuration that does not adversely affect. Further, in order to generate the timing signals T0 to T5 as described above, it is possible to use a delay circuit or the like, but as in the present embodiment,
By using the oscillator circuit 81, the timing of the oscillator circuit 81 can be generated even when a large number of timing signals are generated only by using the capacitor C ₁ as an external element outside the LSI (integrated circuit 32). Can be set freely. However, when the timing generation unit 47 is configured by using a delay circuit, an external element that determines each timing is required to set the timing freely, but when the number of required timings is small, The use of the delay circuit has the advantage of not requiring the latch circuit. In any case, the control speed of the optical / electrical negative feedback loop 6 can be freely set, and the semiconductor laser 3 / light receiving element 4 can be set.
It is also possible to obtain an optical output waveform that is not affected by the frequency characteristic of 1), which is convenient for optimizing the initialization time of the integrated circuit 32.

Further, generally, there is a frequency characteristic between the semiconductor laser 3 and the light receiving element 4, and this frequency characteristic affects the operation of the above-mentioned control system (optical / electrical negative feedback loop 6) and the above-mentioned timing setting. If the frequency characteristics are not good, there is no problem. However, if the frequency characteristics are not good, if the above-mentioned timing is constant, the semiconductor laser 3 and the light receiving element 4 are connected to each other. It is necessary to add a circuit for compensating the frequency characteristic or set the above-mentioned timing to be sufficiently delayed. However, if such timing is set sufficiently late, the initialization time will be prolonged accordingly. However, if a frequency characteristic compensation circuit is added, the number of elements will increase, which is not preferable in any case. In this respect, unlike the present embodiment, by configuring the timing generation unit 47 using the oscillation circuit 81, it is not necessary to provide a circuit for compensating the frequency characteristic only by changing the capacitance of the capacitor C ₁ . In addition, since the entire initialization time does not become long, it is possible to perform efficient initialization while reducing the number of elements. Further, when a timing signal is generated using such an oscillation circuit 81, a flip-flop is normally used, but by using a latch circuit 82 in which a required number of stages of latch circuits 88 are combined as in the present embodiment. The number of elements can be reduced.

Next, the schematic operation at the time of initialization controlled by these timing signals will be described with reference to the time chart of FIG. 20 and the circuit configuration example of the differential quantum efficiency detection unit 46 shown in FIG. First, the optical output of the semiconductor laser 3 is set to a desired maximum light emission state from the forced off state at the timing TS. It is assumed that this maximum light emission value has already been set in the light emission command current generation unit 42. Then, at timing T0, all the input data are set to 0, and the offset light emission state is maintained. After this state is maintained until timing T5, the normal operation state for receiving the original input data is set after timing T5. In order to operate the optical / electrical negative feedback loop 6, it is necessary to perform offset light emission in which the optical output of the semiconductor laser 3 is not turned off completely but slightly emitted. Therefore, in practice, the optical output of the semiconductor laser 3 is controlled by the optical / electrical negative feedback loop 6 between the set maximum emission and the offset emission.

The optical output of the semiconductor laser 3 always detects the differential quantum efficiency by executing the sequence operation as shown in FIG. Set an appropriate added current value.

The difference between the maximum light emission and the offset light emission as shown in FIG. 20, that is, operating current Iop-oscillation threshold current I
Since th is the differential quantum efficiency, the differential quantum efficiency detection unit 46
The sample hold circuit 83 in the inside detects this difference. Schematically, this difference corresponds to the difference in terminal potential of the resistor Re (see FIG. 16) between the maximum light emission and the offset light emission. This difference depends on the difference in the emitter potentials of the transistor Q ₁₂ (see FIG. 10) of the error amplifier 43 in the two cases when the high-speed voltage shift unit 45, which is the current driver 44, is not operating. Therefore, the emitter potential of the transistor Q ₁₂ at the time of maximum light emission is sampled and held, and the potential shift amount of the high-speed voltage shift unit 45, which was 0 at the timing T0, is gradually changed by the addition current setting unit 49 to obtain the difference. Is the potential change of the resistor R ₂ (see FIG. 10) in the high-speed voltage shift unit 45, and the differential quantum efficiency is detected.

Specifically, as shown in FIG. 21, the emitter potential of the transistor Q ₁₂ , that is, the VCOMP terminal is connected to the transistor Q ₄₂ via the emitter follower 91 of the transistor Q _42.
It becomes the base potential of ₄₃ . The base potential of the transistor Q ₄₃ is maintained by the transistors Q ₄₁ , Q ₄₆ , Q ₄₇ , while the current of the current source 92 including the transistor Q ₄₅ is flowing.
By the voltage follower 53 composed of Q _{48 and the} like, the potential becomes the same as the base potential of the transistor Q ₄₄ . When the current of the current source 92 is turned off at the timing T0, the change of the base potential of the transistor Q ₄₃ shows the change of the potential of the VCOMP terminal as it is. However, the base potential of the transistor Q ₄₄ does not change as the capacitance of the capacitor C ₂ increases, and the base potential of the transistor Q _{43 at} the timing T0, that is,
It is possible to sample and hold the emitter potential of the transistor Q ₁₂ at the time of maximum light emission. The lower part of FIG. 20 shows a schematic waveform sampled and held by these transistors Q ₄₃ and Q ₄₄ .

The base potentials of these sample-held transistors Q ₄₃ and Q ₄₄ are transferred to the transistors Q ₄₉ and Q _50.
It is input to the comparator 84, etc., and the magnitude is compared. The comparison result is held in the memory unit 48 in synchronization with the timing signals T1 to T5. Therefore, this memory unit 48 is
Although a configuration example is not shown in particular, it suffices to have a function of holding the comparison output of the comparator 84 in synchronization with the timing signals T1 to T5. For example, the memory unit 48 is configured by a 5-stage latch circuit as used in the timing generation unit 47, and when the base potential on the transistor Q ₄₃ side is higher than the base potential on the transistor Q ₄₄ side in the comparison by the comparator 84. It may be configured to output the L level.

The addition current setting section 49 adds five switches composed of two stages of differential switches, a current mirror circuit for supplying current to the current sources of these switch sections, and outputs of each switch section. And a current mirror circuit which outputs the current from the current driver (high-speed voltage shifter 45). Here, a 5-bit D / A converter 85 is basically composed of five switch sections, and the current sources of these switch sections have a minimum bit current of I1, and a switch section of the next bit has a 2-bit value. * I1, and 4 * I1, 8 * I1, and 16 * I1 are set for each switch part of the higher bits. As a result, the maximum output current of the entire switch unit is 31 * I1. At this time,
The maximum current (maximum voltage) set in the current driver (high-speed voltage shifter 45) is the above-mentioned (operating current Iop).
It is set to be larger than the maximum value of- (oscillation threshold current Ith).

At timing T0, the light output of the semiconductor laser 3 is changed from the maximum light emission state to the offset light emission state as shown in FIG. 20, and at the same time, the current of the most significant bit of the switch section is forcibly output. In this state, the maximum light emission state is offset and the current of the switch section of the most significant bit is forcibly output, causing a potential change in the terminal potential of the voltage shift section. Since the control system 6 controls the optical output of the semiconductor laser 3 to be in the offset emission state, it changes so as to compensate for the difference between these potential changes. As a result, the potential of the VCOMP pin changes. The differential quantum efficiency detection unit 46 detects such a change. Then, the potential of the VCOMP terminal at this time is compared with the potential of the VCOMP terminal in the maximum light emitting state. The comparison result is stored in the memory unit 48. The memory section 48 latches this result and resets the switch section of the most significant bit of the addition current setting section 49. When the potential of the VCOMP pin is higher than that in the maximum light emission state, the setting is turned off. Conversely, when the potential of the VCOMP pin is lower than that in the maximum light emission state, the setting is turned on. Here, timings T0 to T1 (T
1 to T2, ..., T4 to T5 are also the same), it is necessary to set the time during which the control system of the optical / electrical negative feedback loop 6 sufficiently converges.

Timing T0 also at timing T1
As in the case of, the upper 2nd bit is forcibly output,
The result is reset at timing T2. At timing T2, the potential of the VCOMP terminal at the time of detection is compared with the potential of the VCOMP terminal at the time of maximum light emission, and ON / OFF of the resetting of the bit switch portion is determined according to the comparison result. In the present embodiment, since the differential quantum efficiency is detected with the accuracy of D / A for 5 bits, the same is repeated for 5 bits. To illustrate how the change of the base potential at this time, the transistor Q ₄₄ shown in the lower part of FIG. 20
It becomes similar to the case of the base potential of. The illustrated example in this case shows a waveform in the case of 1, 1, 1, 0, 1 in order from the lower bit.

In the present embodiment, the differential quantum efficiency detection unit 4
6 and although the detection accuracy of the added current setting unit 49 and 5 bits, by raising the detection accuracy further increasing the number of bits, in the optical output waveform shown in FIG. 10 (b), P _S content of the light output amount of the desired The optical output is controlled by the control system of the optical / electrical negative feedback loop 6, and the optical output waveform approaches a more ideal square wave.

Next, FIG. 22 shows a circuit configuration example of the power supply unit 101 using bipolar transistors. In
A bandgap reference is formed in a circuit composed of transistors Q ₅₁ and Q ₅₂ and resistors R ₂₁ , R ₂₂ and R ₂₃ , and V = (emitter potential of Q ₅₃ ) −V _be V _be ; The emitter area and resistance of the transistor are determined so that the inter-voltage does not change as much as possible with temperature. As a result, the emitter potential of each of the transistors Q ₅₄ , Q ₅₅ , Q ₅₆ becomes a stable potential having no temperature characteristic. In the case of the circuit configuration shown in FIG. 22, the current flowing by connecting the resistor R ₂₄ to the emitter of the transistor Q ₅₄ is returned by the current mirror circuit 102. Thereby, the integrated circuit 20
An internal current source is generated. That is, the integrated circuit 32
The current flowing through the PNP transistor having the VBBP terminal as the base potential in the start-up unit 50 and the like all becomes a constant current source, and similarly, N having the VBBN terminal as the base potential is used.
All the current flowing through the PN transistor becomes a constant current source.
The current value is determined by the resistance connected to the emitter of each transistor.

The startup section 50 will be described. The start-up unit 50 plays a role of protecting the semiconductor laser 3 from deterioration or damage caused by an excessive current flowing through the semiconductor laser 3 during a period until the power supply voltage _Vcc reaches a predetermined value when the power is turned on. .. Also,
The startup unit 50 plays a role of generating a necessary initialization start signal in the timing generation unit 47. The startup unit 50 is composed of a first startup unit 50a and a second startup unit 50b as shown in FIG.

First, in the first startup section 50a, in the differential switch 111 composed of the transistors Q ₆₁ and Q ₆₂ , the transistor Q ₆₂ is turned on from the power source voltage V _cc to a certain set potential. , Power supply voltage V _cc
The resistors R _{31 to} R ₃₇ are set so that the transistor Q ₆₁ is turned on in a range in which a certain potential exceeds a certain set potential. In this case, a certain set potential is the power supply voltage V as much as possible.
It is set to a potential close to the predetermined potential of _cc . For example, when the predetermined potential of the power supply voltage is 5.0 V and the certain set potential is set to about 2 to 3 V, it cannot be said that the entire circuit is operating as desired, but 4. It can be considered that if the voltage is set to about 5 V, almost the entire circuit operates as desired. Therefore, in the above case, it is set to 4.5V. Since the desired operation is started after the power supply voltage reaches a certain set voltage in this manner, the semiconductor laser 3 can be protected and the initialization start signal can be generated more safely.

Specifically, as shown in FIG. 23, the base potential of the transistor Q ₆₂ is simply the voltage of the collector potential of the transistor Q ₆₃ shifted through the emitter follower 112. Therefore, the base potential of the transistor Q ₆₂ is determined by the collector potential of the transistor Q ₆₃ .
Similarly, the base potential of the transistor Q ₆₁ is
_As long as ₆₄ is off, it is determined by the collector potential of transistor Q ₆₅ . The collector potential of the transistor Q ₆₃ is determined by the transistor Q ₆₆ , the resistor R ₃₃ and the power supply voltage. _Assuming that the current of the current source composed of the transistor Q ₆₆ and the resistor R ₃₃ is I ₁ and the power supply voltage is V _cc , the collector potential V _q63c of the transistor Q ₆₃ is V _q63c = V _cc −I ₁ * R ₃₁ Become. Here, since the current I ₁ is a constant current source whose base potential is the voltage supplied from the VBBN terminal, I ₁ * R ₃₁
Is a constant potential. Originally, the power supply unit 101 is also driven by the power supply voltage, so if the power supply voltage is 0 V, the current I ₁ is also 0.
A. However, since a certain set potential is set to a potential as close as possible to the predetermined potential of the power supply voltage, in a state (time) in which the differential switch 111 constituted by the transistors Q ₆₁ and Q ₆₂ is switching, Power supply 1
01 is functioning, and the current I ₁ is also a constant current. Then, _Vq63c changes according to the power supply voltage _Vcc .

Collector potential V of transistor Q _65
Q65c, like the above equation, the current source of the current composed of the transistors Q ₆₇ and the resistor R ₃₄ When I _2, the _{V q65c = V cc -I 2 *} R 32. Here, considering the current flowing through the resistor R ₃₆ assuming that the resistors R ₃₄ and R ₃₅ have the same resistance value, V _cc = (I ₂ + I ₃ ) * R ₃₆ + V _be + I ₂ * R ₃₅ . Here, the current I ₃ is due to the transistor Q ₆₈ and the resistor R.
The current value of the constant current source composed of ₃₇ and V _be is the base-emitter voltage of the transistor.

From the above equation, V _q65c = I ₃ * R ₃₆ + V _be + I ₂ * (R ₃₆ + R ₃₅ −R ₃₂ ). Here, since I ₃ * R ₃₆ has a constant potential similarly to the current I ₁ and V _be also has a substantially constant potential, if R ₃₆ + R ₃₅ = R ₃₂ , the collector potential V _q65c of the transistor Q ₆₅ is equal to the power supply. A constant potential independent of voltage can be obtained. That is, the collector potential V _q65c of the transistor Q ₆₅ is constant, and the collector potential V _q63c of the transistor Q ₆₃ changes according to the power supply voltage V _cc . Therefore, by appropriately setting both potentials, it is possible to switch the differential switch 111 constituted by the transistors Q ₆₁ and Q ₆₂ at appropriate timing according to the change in the power supply voltage when the power is turned on. As a result, the transistor Q ₆₂ is on until the power supply voltage V _cc reaches a certain set potential from 0V. In this state, the collector current flowing through the transistor Q ₆₂ is inverted by the current mirror circuit 113, and the transistors Q ₆₉ and Q ₇₀ are turned on. This allows TDSTAR
The potentials of the T and TD terminals are forced to be approximately the same as _Vcc . Specifically, the error amplifier 23 is controlled by forcibly setting the potential of the PD terminal of the light receiving element 4 to the H level.
Is forced to the L level. In this way, the semiconductor laser 3 is protected by suppressing the forward current of the semiconductor laser 3 from flowing. At the same time, as described later, the potential of the TDSTART terminal is forcibly set to the H level to suppress the oscillation circuit in the timing generation unit 47 from being forcibly oscillated. Then, when the power supply voltage V _cc exceeds a certain set potential, that is, when the transistor Q ₆₁ changes to the ON state, the protection of the semiconductor laser 3 is released and the semiconductor laser 3 is brought into the normal operation state, and the oscillation in the timing generation section 47 is performed. The oscillation start signal is generated by canceling the oscillation suppression of the circuit. At the same time, the VPTDSTART terminal potential for generating the current source of the timing generator 47 is output.

In the present embodiment, the light emission command signal generation unit 42 is configured by connecting two D / A converters in parallel as the light emission command signal generation unit first and second constituent units 42a and 42b. As illustrated in FIG. 24, two D /
The A converter may be made common and configured as the light emission command signal generation unit 42 as one circuit. According to this, the parts that perform the same function are shared,
The number of elements constituting a circuit can be reduced.

Next, FIG. 25 shows a semiconductor laser deterioration detecting section 1
21 shows a configuration example of the bipolar transistor 21. If the semiconductor laser 3 deteriorates to some extent, it can be set by detecting the values in the current setting of the optical / electrical negative feedback loop 6 and the current driver 44. In the case where a large current flows through the device, a deterioration detection unit is necessary to protect the integrated circuit 32. The semiconductor laser deterioration detector 121 is provided for this purpose. The operation of this circuit is as follows: LD connected to the semiconductor laser 3
The potential VLD of the terminal is constantly monitored, and when a certain comparison potential is exceeded, an error signal is output from the error terminal LDERR terminal to the outside. In the circuit of the illustrated example, the differential amplifier 122 is composed of transistors Q ₅₇ and Q ₅₈ . Transistor Q ₅₉
The comparison potential applied to the power supply unit 1 is described with reference to FIG.
It is generated from 01. L given to transistor Q ₅₈
When the potential VLD of the D terminal exceeds this potential, the transistor Q
₅₈ turns on and current flows from the LDERR pin to the collector of transistor Q ₅₉ . An open collector is configured here.

As a result, when the semiconductor laser 3 deteriorates or fails, the semiconductor laser 3 emits an excessive light output, and the potential VLD of the LD terminal rises excessively. Since it is possible to detect the error and output the error signal in advance, it is possible to prevent the danger from being continued without being used as it is.

Next, FIG. 2 shows a third embodiment of the present invention.
6 to 34, a description will be given. In this embodiment,
In particular, the specific configuration examples of the data conversion unit 61 and the pulse width modulation unit 62 will be clarified. Regarding the logical operation by the data conversion unit 16 and the pulse width modulation unit 17 in the above-described first embodiment, there is a correlation that the pulse PW _on is always shorter than the pulse PW _da by the minimum pulse. Therefore, a part of the modulation data can be shared. That is, D _ni = D _ni ′ and D _mj = D _mj ′. Therefore, for example, the logic units 22 and 24 can be omitted in FIG.
The number of elements of the data conversion unit 16 is reduced and the pulse width modulation unit 1
The number of data lines for 7 can be reduced.

That is, the following logical expression may be used.

[0102]

(Equation 3)

Further, normally, when the input data string is an image data N-bit data string, the maximum number of gradations that can be output is 2 ^ N, which is 0/2 ^ N to 2 ^ N / 2 ^ N. Of the 2 ^ N + 1 output states, one or several are missing. Further, when one bit of the position control signal is further added as an input data sequence, 2 モ ー ド N-value gradation output is performed in each mode of the left-justified waveform and the right-justified waveform, but in each mode, one of the output states is missing. I have. Therefore, in order to completely obtain 2 ＾ N + 1 gradations, N + 1 bits and 1 bit of the position control signal are required as image data. However, since the full-off (0/2 @ N) and full-on (2 @ N / 2 @ N) waveforms are the same in both the left-justified waveform and the right-justified waveform, the full-off, full-on and intermediate values of the left-justified waveform and the right-justified waveform, respectively, are 1 / 2 @ N- (2 @ N-
1) / 2 ＾ N (2 × (2 ＾ N−1)) pieces in total 2 ＾ (N +
If 1) states are output, 2 ＾ N + 1-valued gradation output including the position control even from the N + 1-bit data string is obtained.

For example, assuming that the data string is 4 bits, 9-value gradation per dot (9 values from 0/8 to 8/8, 0/0
8 (always off), 8/8 (always on), each having a total of 16 states of 1/8 to 7/8 of the left-aligned or right-aligned waveform). If the input image data is such a data string, the same gradation number can be obtained with a data string having one bit less. Therefore, the input data transfer rate can be reduced, and the number of input terminals can be reduced. Further, the buffer memory usually used in the preceding stage of the data conversion unit 21 can be reduced. Conversely, when the number of input data lines is determined, the number of gradations can be increased by forming such a data string. This is particularly effective when the number of data bits per dot is small.

Specifically, when the write clock frequency is to be doubled, if the data string is a 9-value gradation including the dot position control per dot in each of the upper 4 bits and the lower 4 bits, the write clock frequency In the case of doubling, the number of gradations can be increased without increasing the number of input data lines and a high-quality image can be obtained.

That is, equations (7), (8) and (9) may be used. In the equation (7), X _n , X _n ′, X _m and X _m ′ are (5)
Follow the formula. Further, when the intensity modulation data D _pk is M = 0,
Only D _p4 is set to H level, and all others are set to L level.

[0107]

(Equation 4)

Further, regarding the pulse width modulation section 17, when the forced light-off command signal S _W1 and the forced light emission command signal S _W2 are taken into consideration, a logical formula such as formula (10) is used instead of formula (7). As a result, the semiconductor laser 3 can be forcibly turned off or emitted regardless of the input image data.
However, the forced off command signal S _W1 and the forced light emission command signal S _W2
Will never be at H level at the same time.

[0109]

(Equation 5)

FIG. 20 shows a block configuration example of the data conversion section 61, the pulse width modulation section 62 and the switch section 131 which are configured to perform pulse width modulation according to the logical description of equations (10), (5) and (8). Show. First, in the data conversion unit 61, two logic units 142 that perform the logic of equation (8) based on the input image data D _{0 to} D ₇ , the position control data P, and the frequency selection signal M to convert into pulse width modulation data 142. , 143 are provided. Means for temporarily holding the converted pulse width modulation data, for example, latch circuits 144 and 145 are provided on the output side of the logic units 142 and 143. A gate signal generation circuit 146 that generates a gate signal based on the output from the pulse generation oscillator 63 is connected to these latch circuits 144 and 145.

Further, the pulse width modulator 62 is provided with multiplexers 147 to 150. The first multiplexer 147 receives four (X _i ) of the pulses X _{0 to} X _{7 having} different phase differences and outputs one of the input signals X _i according to the pulse width modulation signals D _{n1 to} D _n4 which are select signals.
It has the function of selecting one of the normal or inverted signals or the signal of H level or L level at all times. Multiplexer 148-
The same applies to 150. Further, the multiplexer 15 is also provided at the subsequent stage of these multiplexers 147 to 150.
1, 152 are provided. The multiplexer 151 outputs X _n output from the multiplexers 147 and 148,
Any one of X _n ′ is selected according to the pulse width modulation signals D _n5 and D _n6 which are select signals. The same applies to the multiplexer 152. AND gates 154a to 154d and an OR gate 154 which generate the pulses PW _da and PW _on according to the logic of the equation (10) by the outputs of the multiplexers 151 and 152 and the internal clock of the pulse generation oscillator 63.
e, 154f are provided. OR gate 154e,
Multiplexers 155 and 156 forming the switch unit 131 are interposed at the output of 154f. These multiplexers 155 and 156 follow the OR gate 154e, the OR gate 154e and the forced light emission command signal S _W1 or the forced light emission command signal S _W2 .
It has a function of outputting the output from 154f as it is or by switching it to L level or H level at all times.

The data conversion section 61, the pulse width modulation section 62 and the switch section 131 as described above can be easily integrated by a bipolar transistor or the like. For example,
FIG. 27 shows a configuration example of the latch circuit 134 which is an example of a data holding unit used to hold input image data and modulation data. The data to be input now is D, /
If D (differential input) and the held data are Q and / Q, then it can be described as follows: Q = DG + Q (/ G). That is, the latch gate signal G becomes H
When the signal is at the level, the input signal D is output and the latch gate signal G is output.
Is low, the previous data is held. The latch gate signal G is generated by the gate signal generation circuit 1 based on a pulse generated by the pulse generation oscillator 63 or the like or a combination thereof.
It can be easily generated at 46. For example, referring to the time chart shown in FIG. 8, the latch gate signal G ₁ for holding the modulation data D _n for selecting X _n is G ₁
= X ₂ · X ₄ , and the latch gate signal G ₂ for holding the modulation data D _m for selecting X _m is G
₂ = X ₆ · X ₀ .

Further, the latch circuit 14 as shown in FIG.
A signal obtained by inverting two latch gate signals of the preceding stage is connected to the latch gate signal of the preceding stage, or the latch gate signal of the preceding stage is changed to the H level for a certain period during the period of the L level of the preceding latch gate signal. If the signal is If the data holding means has a flip-flop configuration, the data immediately before the fall of the latch gate signal of the preceding stage is held for one clock all the time (only with the latch circuit 144, the gate trigger signal becomes H level).
If it changes during the level, the output also changes), and it is suitable as a means for holding the intensity modulation data.

FIG. 28 shows a part of the logic unit 142 (8).
An example of the logic circuit 157 in which the first equation relating to D _n1 of the equation is constituted by a bipolar transistor is shown. This logic circuit 1
The output of 57 may be held by a latch circuit 144 or the like as shown in FIG.

However, as shown in FIG. 29, the number of elements can be reduced by configuring the logic circuit 158 for simultaneously generating and holding the pulse width modulation data D _n1 . That is, FIG. 29 is configured to execute the logical description of the expression (11).

[0116]

(Equation 6)

In FIG. 29, G ₁ is a latch gate signal. Further, V _th1 and V _th2 are threshold voltages of the respective logic levels, and the input signal such as D ₅ is obtained by using the level shift circuit 159 shown in FIG. It is converted to a level signal. These are voltage-shifted by an emitter follower, a diode, a resistor, etc. as necessary.

The frequency selection signals M and / M are generated from a frequency selection signal Mode from the outside by a selection signal generation circuit 160 as shown in FIG. In FIG. 31, the transistor Q _{1 whose} base is _supplied with the reference potential V _BBp and the resistor R ₁ constitute a constant current source 161 for flowing the current I ₁ . Transistors Q ₂ and Q ₃ are differential switches 1
62 is configured. To the base of the transistor Q _2, a signal obtained by converting the frequency selection signal Mode into an internal level signal by the resistors R ₂ and R ₃ is applied, and the base of the transistor Q ₃ includes the transistors Q _{4 to} Q ₇ and the resistors R _{4 to} R _{4. The} threshold voltage generated by ₆ is applied. Now, when the frequency selection signal Mode is at the H level, the transistor Q ₃ is turned on and its collector current becomes the current I ₁ by the constant current source 161, and the potential of the selection signal M is I ₁ · R ₁ + V.
_BE (V _BE : base-emitter voltage of the transistor) is turned on. On the other hand, the collector current of the transistor Q ₂ is is substantially 0, the selection signal / M is turned off. The opposite is true when the frequency selection signal Mode is at the L level. When these selection signals M and / M are applied to the base of a current switch (for example, the current switch 163 in FIG. 29) composed of a transistor pair and a resistor, a current flows through the collector of either one of the transistors.

The other equations in the equation (8) can be similarly constructed by bipolar transistors. Furthermore,
The other logic formulas can be similarly integrated with bipolar transistors. For example,
In the case of the first expression of the expression (6), a current source may be used in place of the current switch 163 in FIG. 29, and the upper circuit 164 portion may be omitted.

To obtain the intensity modulation data D _PK , the latch circuits may be connected in cascade. FIG. 32 shows a circuit configuration example of the D _p4 generation unit 166 for obtaining D _p4 of the first equation in the equation (9). The data generation logic is incorporated into the latch circuit 168 in the latter stage of the two latch circuits 167 and 168 while holding the data. The latch circuit 167 in the previous stage is configured to take out only the non-inverted output with respect to the configuration shown in FIG. 27, and element saving is achieved. In the figure, D ₄ is converted into an internal level signal through a level shift circuit as shown in FIG. 30, and V _th1 is a threshold voltage. M and / M can be generated by the circuit of FIG. 31 as described above, and G ₁
And G ₃ are respective latch gate signals, G ₁ is as described above, and G ₃ may be G ₃ = X ₀ . Further, in FIG. 32, if the collector of the transistor Q ₁₀ is connected to the resistor R ₇ , D _{p3 to} D _{p0 in the} equation (9) are obtained.
Can be generated.

Next, the pulse width modulator 6 shown in FIG.
Regarding No. 2, for example, a bipolar transistor can be configured as shown in FIGS. Figure 33
FIG. 2 shows a circuit which constitutes the logical description of the first equation of the equation (5).
6 corresponds to the multiplexer 147. Figure 34 is (10)
26 shows a circuit that constitutes the logical description of the first expression of the equation, and corresponds to the multiplexers 151, 152, 155, AND gates 154a, 154c, and OR gate 154e in FIG.

First, in FIG. 33, the transistor Q ₁₁ and the resistor R ₈ having the base to which the reference potential V _BB is applied have a current I.
Is a current source 169 for flowing a current, and 170 to 172 are differential switches, respectively, and one of the transistors of the differential switches 170 and 171 is turned on by the pulse width modulation data D _n1 and D _n2 , and each of them is turned on. Any differential switch 173, 174, 17 connected to the collector
A current flows through 5,176. Pulses having different phases generated in the pulse generation oscillator 63 are applied to these four differential switches 173-176. A selected pulse X _i (i = 1 to 4 from the left) is applied to the transistors on the right side of the differential switches 173 to 176, and an inverted signal thereof is applied to the transistors on the left side (of course, the transistors on the left side). The base may be fixed at a certain potential). However, as shown in the drawing, the differential input requires a smaller swing voltage for switching, and the differential input is preferable in the case where a large number of transistors are stacked in multiple stages as shown in FIG.

At the input of X _i , the linearity of the generated pulse width modulation is also improved. For example, D _n2 =
0, D _n1 = 1. In this case, the transistor on the right side of the differential switch 170 is turned on, a current flows through the differential switch 174, and the other three differential switches 17
No flow to 3,175,176. That is, pulse X ₆
Is selected, a current flows through the differential switch 177 while the pulse X ₆ is at the H level and a current flows through the differential switch 178 during the L level. These differential switches 17
Pulse width modulation data D _n3 and D _n4 are added to 7 and 178, respectively, and when both are at the H level, the terminal voltage of the resistor R ₉ becomes a signal equal to the pulse X _6, and when both are at the L level, the pulse X ₂ ( (Inversion of X ₆ ), always at L level when D _n3 = 0, D _n4 = 1 regardless of pulse X ₆ , and always at H level when D _n3 = 1 and D _n4 = 0
Level. This becomes a pulse X _n via the emitter follower and the diode, and its inverted signal is similarly generated. Further, X _n ′, X _m , and X _m ′ can be configured by appropriately changing the input signal in FIG. 33 according to the equation (5). Furthermore, X _n according to another formula
Can be similarly configured.

Since FIG. 34 is also basically constructed in the same manner as FIG. 33, it will be briefly described. CK ₀ is the pulse X ₀
The are of only the voltage shift, which is the internal clock (the correspondence between the above-mentioned formulas, described in X ₀ in the following description). When X ₀ is at H level, current flows through the transistor on the left side of the differential switch 172a, and D _n5 = 0.
In the case of, the current that is the logical product of X _n and X ₀ flows to the differential switch 177a, and in the case of D _n5 = 1, the current that is the logical product of X _n ′ and X ₀ flows to the differential switch 177a. . X
_{When 0} is L level, X _m or X _m ′ and / X according to D _m5
A current that is the logical product of ₀ and ₀ flows. Therefore, the logical sum of these currents flows through the differential switch 177a, and the inverted current flows through the differential switch 178a. Therefore, when both the forced extinction command signal S _W1 and the forced light emission command signal S _W2 are at the L level, the signal obtained by the logical sum becomes the terminal voltage of the resistor R ₃ ′ and becomes PW _da via the emitter follower.
When only the forced turn-off command signal S _W1 is at the H level, it is always at the L level regardless of the pulse width modulation data, that is, the forced turn-off command signal S _W1 and the forced light emission command signal S _W2 are the same signal PW _on. The laser 3 is forced off. When only the forced light emission command signal _SW2 is at the H level, the H level is always maintained, that is, the semiconductor laser 3 is forcibly turned on. PW _on
Can be generated by changing the input signal in the configuration of FIG.

In these embodiments, the pulse width generator / data modulator 2 and the semiconductor laser controller / driver 5 shown in FIG. 1 and the like are all integrated into one-chip integrated circuits 9 and 32 using bipolar transistors. However, it is also possible to integrate them into one chip by using only C-MOS transistors, or to integrate them into one chip as a hybrid circuit of bipolar transistors and C-MOS transistors. If the one-chip integrated circuit is formed by C-MOS transistors, it becomes easy to configure the pulse width generation / data modulation section 2 side of the digital control system, and the degree of integration can be increased. If a one-chip integrated circuit is formed by a hybrid circuit of a bipolar transistor and a C-MOS transistor, an analog drive system amplifier such as the error amplifier 8 and the constant current source 7 can be easily configured by the bipolar transistor, and digital control can be performed. The pulse width generation / data modulation unit 2 of the system can be easily configured by the C-MOS transistor, and the circuit design becomes easy.

[0126]

According to the first aspect of the present invention, the pulse width modulation / intensity modulation signal generator for generating the light emission command signal for simultaneously performing pulse width modulation and intensity modulation on the input data based on the input data. A semiconductor laser and a light receiving element that monitors the optical output of this semiconductor laser together with an optical / electrical negative feedback loop to form a light receiving signal and pulse width modulation that is proportional to the optical output of the semiconductor laser obtained from the light receiving element. The semiconductor laser is controlled by the sum or difference of the error amplification unit that controls the forward current of the semiconductor laser so that the emission command signal obtained from the intensity modulation signal generation unit becomes equal to the control current of the optical / electrical negative feedback loop. Drive current corresponding to a light emission command signal generated from the pulse width modulation / intensity modulation signal generation unit to control the driving of the Since the drive unit is composed of a one-chip integrated circuit, the semiconductor laser control device can be made compact and save power, and the pulse width intensity mixing method within one dot can be realized at higher speed and higher accuracy. it can.

Here, regarding the pulse width modulation / intensity modulation signal generation section, in the invention described in claim 2, the data conversion means for converting the input data into the pulse width modulation data and the intensity modulation data, and the pulse width modulation data. Pulse width modulation means for generating a plurality of pulses pulse width modulated based on;
Since the semiconductor laser device has a light emission command signal generation unit that simultaneously performs pulse width modulation and intensity modulation on the basis of the outputs of the data conversion unit and the pulse width modulation unit, the pulses forming a digital control system are provided. The configuration for integrating the width modulation / intensity modulation signal generation unit into one chip becomes clear.

According to the third aspect of the present invention, since the one-chip integrated circuit is formed by the bipolar transistors, it is easy to construct an analog drive system amplifier such as an error amplifying section or a current driving section. Therefore, the input level can be set freely and the input level can be reduced.

According to the invention described in claim 4, since the one-chip integrated circuit is formed by the C-MOS transistor, it is particularly easy to configure the pulse width modulation / intensity modulation signal generation section side. In addition, the degree of integration can be increased.

According to the fifth aspect of the present invention, since the one-chip integrated circuit is formed by the hybrid circuit of the bipolar transistor and the C-MOS transistor, the analog drive such as the error amplification section and the current drive section is performed. The system amplifier can be easily configured with bipolar transistors, and the digital control system such as the pulse width modulation / intensity modulation signal generation unit can be easily configured with C-MOS transistors, thus facilitating the design of the entire circuit. Can be

[Brief description of drawings]

FIG. 1 is a block diagram showing a block configuration of a semiconductor laser control device according to a first embodiment of the present invention which is made into one chip.

FIG. 2 is a block diagram showing a basic schematic configuration.

FIG. 3 is a schematic diagram showing a relationship between a pulse width intensity modulation mixing method optical output and a dot image.

FIG. 4 is a time chart showing the waveform generation method.

FIG. 5 is a characteristic diagram showing an example of optical output control _depending on the presence / absence of addition output associated with I _DA2 .

FIG. 6 is a block diagram showing a specific block configuration of a light emission command signal generation unit.

FIG. 7 is a block diagram showing a specific block configuration of a data conversion unit and a pulse width modulation unit.

FIG. 8 is a time chart showing a pulse width generation method.

FIG. 9 is a schematic block diagram showing an overall configuration of a second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration example of an error amplification unit and a voltage shift unit.

FIG. 11 is a circuit diagram showing a configuration example of a light emission command signal setting unit.

FIG. 12 is a circuit diagram showing a configuration example of a first light emission command signal generation unit.

FIG. 13 is a circuit diagram showing a configuration example of a second light emission command signal generation unit.

14A is a schematic configuration diagram in the vicinity of an input unit, and FIG. 14B is a schematic configuration diagram showing a modified example thereof.

FIG. 15 is a time chart showing a modification of the input method.

FIG. 16 is a schematic block diagram showing a modified example of the overall configuration.

FIG. 17 is a circuit diagram showing a configuration example of an oscillation circuit.

FIG. 18 is a circuit diagram showing a configuration example of a latch circuit.

FIG. 19 is a circuit diagram showing a configuration example of a final stage latch circuit.

FIG. 20 is a time chart showing the waveform of each part.

FIG. 21 is a circuit diagram showing a configuration example of a differential quantum efficiency detection unit.

FIG. 22 is a circuit diagram showing a configuration example of a power supply section.

FIG. 23 is a circuit diagram showing a configuration example of a startup unit.

FIG. 24 is a circuit diagram showing a modified example of a light emission command signal generator.

FIG. 25 is a circuit diagram showing a configuration example of a semiconductor deterioration detection unit.

FIG. 26 is a block diagram showing a specific configuration example of the third embodiment of the present invention.

FIG. 27 is a circuit diagram showing a configuration example of a part of the latch circuit.

FIG. 28 is a circuit diagram showing a configuration example for executing a part of the logical description.

FIG. 29 is a circuit diagram showing a configuration example for executing a part of the logical description.

FIG. 30 is a circuit diagram showing a level shift circuit.

FIG. 31 is a circuit diagram showing a frequency selection signal generation circuit.

FIG. 32 is a circuit diagram showing a configuration example for obtaining an intensity modulation signal.

FIG. 33 is a circuit diagram showing a configuration example of a multiplexer in the pulse width modulation unit.

FIG. 34 is a circuit diagram showing a configuration example of another portion in the pulse width modulation portion.

[Explanation of symbols]

 3 semiconductor laser 4 light receiving element 6 optical / electrical negative feedback loop 7,44 current driver 8,43 error amplifier 9,32 1-chip integrated circuit 11 pulse width modulation / intensity modulation signal generator 12,42 emission command signal generation Part 16,61 Data conversion means 17,62 Pulse width modulation means

Claims (5)

[Claims] 1. A pulse width modulation / intensity modulation signal generation section for generating a light emission command signal for simultaneously performing pulse width modulation and intensity modulation on the input data based on the input data, a semiconductor laser, and this semiconductor laser. A light receiving element that monitors the optical output of
The forward current of the semiconductor laser is controlled so that the received light signal obtained from the light receiving element and proportional to the optical output of the semiconductor laser is equal to the light emission command signal obtained from the pulse width modulation / intensity modulation signal generation unit. And an error amplification section for generating a pulse width modulation / intensity modulation signal generation section that is generated so as to control the driving of the semiconductor laser by a current that is the sum or difference of the control current of the optical / electrical negative feedback loop. 2. A semiconductor laser control device, wherein: a current drive unit for supplying a drive current corresponding to a light emission command signal to the semiconductor laser as a forward current, and an integrated circuit of 1 chip. 2. The pulse width modulation / intensity modulation signal generation section includes data conversion means for converting input data into pulse width modulation data and intensity modulation data, and a plurality of pulse width modulated signals based on the pulse width modulation data. It has pulse width modulation means for generating a pulse, and a light emission command signal generation section for simultaneously performing pulse width modulation and intensity modulation for a semiconductor laser based on the outputs of these data conversion means and pulse width modulation means. The semiconductor laser control device according to claim 1, wherein: 3. The semiconductor laser control device according to claim 1, wherein the one-chip integrated circuit is formed by a bipolar transistor. 4. A semiconductor laser control device according to claim 1, wherein the one-chip integrated circuit is formed by a C-MOS transistor. 5. The semiconductor laser control device according to claim 1, wherein the one-chip integrated circuit is formed by a hybrid circuit of a bipolar transistor and a C-MOS transistor.