KR101765014B1 - Twin Codes System - Google Patents

Abstract

The present invention relates to a twin codes system and a method for implementing the same. According to an embodiment of the present invention, the twin codes system comprises: an information source (100); a first encoder (200); a second encoder (300); a modulator (400); a transmitting end (500); a receiving end (600); a demodulator (700); a first decoder (800); a second decoder (900); and a data destination (1000). The present invention maximizes reliability of an encoded information sequence by selectively combining bits or words with high decoding reliability.

Description

Twin Codes System and its Implementation Method [

The present invention relates to a twin code system and an implementation method thereof, and more particularly, to a twin code implementation technique capable of improving the performance of a digital communication system through application of different error control capabilities. The twin code according to the present invention may be a binary code or an error code which is a bit sequence output from a binary signal generator or an error- correcting codes, the output bitstreams have almost the same external characteristics but different error control capabilities are implemented.

The twin codes are similar in appearance, such as code rate, codeword length, constraint length, generator matrix size, or generator polynomial order, However, it means different codes with different error control capability or characteristics. This means that a bit sequence, which is the output of a binary source or a binary signal generator, can be input to an input of an error-correcting codes device having a different design method or structure So that the output bit strings have substantially the same external characteristics but have different error control capabilities.

A similar prior art for initiating a twin code system according to the present invention includes: 1) Korean Patent Laid-Open No. 10-2005-0002294, entitled " Transcode apparatus and method for preparing transmission errors of video bit streams. The decoding apparatus includes a decoder for decoding a bitstream and decoding the bitstream, and an intra-mode decoder for decoding the error signal and a header for decoding the error- Wherein the encoding unit comprises: a DCT unit for performing DCT on the decoded video signal; A positive magnetization part for quantizing the video signal obtained by performing the DCT on the DCT section; A variable length coding unit for performing variable length coding by adding a header according to a transmission error rate to the quantized video signal obtained by the quantization unit; An inverse quantization unit and an inverse discrete cosine transform unit for reconstructing the quantized video signal by inverse quantization and inverse discrete cosine transform; A memory for storing a video signal re-decoded by the inverse quantum and inverse DCT unit; And a motion correcting unit for correcting the motion of the video signal into motion vector information extracted in the decoding step of the decoding unit bit stream in the memory.

Other similar prior art techniques include 2) Korean Patent Application Publication No. 10-2011-0081946, entitled " Method for transmitting multiple codewords in a multiple antenna system ". The similar prior art method comprising: generating a plurality of parallel codewords by encoding a plurality of parallel information bit streams; Modulating the plurality of parallel codewords to generate a plurality of parallel modulation symbol streams; Performing a DFT on the modulation symbol stream to generate a plurality of frequency domain symbol streams; Performing precoding on the plurality of frequency domain symbol streams; Mapping the precoded frequency domain symbol streams to resource elements; Performing IFFT on the plurality of frequency-domain symbol streams to generate SC-FDMA symbols; Performing shifting to change a layer to which the plurality of parallel codewords, the plurality of parallel modulation symbol streams or the plurality of frequency domain symbol streams are mapped to a predetermined time period; And transmitting the SC-FDMA symbol.

Another similar prior art is disclosed in Korean Patent Application Publication No. 10-2004-0035289, entitled " Transmission Device and Transmission Method of Digital Broadcasting System Having Complex Error Correction Coding Function ". Wherein the pseudo prior art includes an RS encoder for performing RS (Reed-Solomon) encoding on an input first TS stream; The encoding may be performed by an external encoder; First and second external interleavers for rearranging the data encoded by the RS encoder and the data encoded by the external encoder, respectively; First and second convolutional encoders respectively performing convolutional coding on rearranged data in the first and second outer interleavers; An inner interleaver for rearranging the data encoded by the first and second convolutional encoders, respectively; And a modulator for digitally modulating and transmitting data rearranged from the internal interleaver.

However, by using a bit string, which is the output of a binary information source or a binary signal generator, as an input of an error correcting code apparatus having a different design method or structure depending on the purpose, the output bit strings have substantially the same external characteristics, No technology has been proposed to implement the capability.

KR10-2005-0002294 (A) KR10-2011-0081946 (A) KR10-2004-0035289 (A)

The present invention aims to satisfy the technical needs required from the background of the above-mentioned invention. More specifically, it is an object of the present invention to provide a method and an apparatus for error correcting code which are different from each other in design method or structure according to a purpose by using a bit string which is an output of a binary information source or a binary signal generator, The present invention is directed to providing a technique in which different error control capabilities are realized.

The technical objects to be achieved by the present invention are not limited to the above-mentioned problems, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description. There will be.

이 I_max1인지 확인하는 단계; 오류 포함 대상이 트랩핑 세트인지를 판단하는 단계; 변수노드의 비트 확률을 초기화시키는 단계; 실패 검사노드 패턴과 경판정 천이패턴에 대한 검사영역을 설정하는 단계; 변수노드들의 비트를 반전시키는 단계(S800); 수정 합-곱 알고리즘 분석 단계; 신드롬 검사를 재수행하여 그 결과가 0인지 확인하는 단계; 상기 신드롬 검사 결과가 0이 아니면

이 I_max1인지 재확인하는 단계; 상기

이 I_max1이면 반복복호를 종료하는 단계;가 포함되는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a twin code system comprising: an information source for generating a bit string b; A first encoder for encoding the bit string b and outputting an error correction code c ₁ ; A second encoder for encoding the bit string b simultaneously with the first encoder and outputting an error correction code c ₂ ; A modulator for independently modulating a signal encoded through the first encoder and the second encoder; A transmitter for receiving a modulated signal through the modulator; A receiving end for decoding the twin code; A demodulator for dividing the signal sequence received through the receiver into two sub signal sequences and independently demodulating the signal sequence to generate a demodulation bit stream c ₁ 'and a demodulation bit stream c ₂ '; A first decoder for decoding the demodulation bit stream c ₁ '; A second decoder for decoding the demodulation bit stream c ₂ '; Decoding a is decoded independently generated by the first decoder bit sequence b _1, the final decoded bit sequence b 'data destination to the destination consists of' and the second decoder to a decoded bit string b ₂ generated is decoded independently by ';≪ / RTI > According to another aspect of the present invention, there is provided a twin code system comprising: calculating an initial probability value of a variable node; Storing a hard decision transition result of a failure check node and a bit probability; Performing a syndrome test to check whether the result is 0; The counter of the number of decodes performed

Confirming that this is I _max1 ; Determining whether the error inclusion target is a trapping set; Initializing a bit probability of a variable node; Setting an inspection region for a failure check node pattern and a hard decision transition pattern; Inverting the bits of the variable nodes (S800); A correction sum-product algorithm analysis step; Re-executing the syndrome test and checking whether the result is 0; If the syndrome test result is not 0

_{Re-confirming} that I _max1 ; remind

And terminating the iterative decoding if I _max1 is included.

As described above, according to the present invention, a bit string, which is the output of a binary information source or a binary signal generator, is used as an input of an error correcting code apparatus having a different design method or structure, But different error control capabilities are implemented. Further, there is an effect that a bit string of each encoder is independently modulated and transmitted to a transmitter, and a bit or a word having a high decoding reliability can be selectively combined, thereby maximizing the reliability of the decoded information string. It is possible to apply and apply the present invention to a wide variety of fields in which improvements are required.

It is to be understood that the technical advantages of the present invention are not limited to the technical effects mentioned above and that other technical effects not mentioned can be clearly understood by those skilled in the art from the description of the claims There will be.

1 is a block diagram of a twin coder and a transmitter structure including the twin coder according to the present invention;
2 is a block diagram of a receiver structure including a decoder for decoding a twin code according to the present invention;
3 is an example of a bit error rate of a turbo code or a low density parity check code;
4 is a flowchart illustrating a method of implementing the twin code system according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, It is not. In the following description of the present embodiment, the same components are denoted by the same reference numerals and symbols, and further description thereof will be omitted.

Prior to the detailed description of each step of the invention, terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary meanings, and the inventor shall design his own invention in the best manner It should be interpreted in the meaning and concept consistent with the technical idea of the present invention based on the principle that the concept of the term can be properly defined. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are only the most preferred embodiments of the present invention and do not represent all the technical ideas of the present invention. Therefore, It is to be understood that equivalents and modifications are possible.

In the twin code system according to the present invention, the bit streams of the first coder 100 and the second coder 200 are independently modulated and transmitted to the transmitter. An antenna may be used when the transmitter is applied to a wireless communication system. Another characteristic that can be achieved using the twin code system is the decoding process. Referring to FIG. 2, a simple type comparator is added to a twin decoder to compare reliability information between the first decoder (decoder 1) and the second decoder (decoder 2), thereby selecting a bit or word having a high decoding reliability As shown in FIG. Therefore, the twin code technique can be a useful method for greatly improving the error performance of the digital communication system by maximizing the reliability of the decoded information sequence.

The signal sequence received through the receiver-end is demultiplexed into two subordinate signal sequences and becomes bit streams c ₁ 'and c ₂ '. These bit strings are independently decoded by the first decoder and the decoder 2 for decoding the twin code, and become bit strings b ₁ 'and b ₂ '. In such a twin decoder, the reliability information generated in the decoding process of c ₁ 'and the reliability information generated in the decoding process of c ₂ ' are designed to be used mutually so that the reliability of the decoded bit streams b ₁ 'and b ₂ ' Can be further increased. Also the process of reproducing the final decoded bit sequence b 'from the decoded bit sequence b _1' and b ₂ 'are applied to a reverse process of generating a two bit sequence in the source (source) of FIG.

A typical error performance curve of a turbo code or a low density parity-check code (LDPC) is shown in FIG. 3 in order to illustrate the applicable examples of the twin codes and the advantages that can be obtained therefrom. The twin code is one of useful methods for simultaneously improving the performance of the error fall or water fall area and the error floor area appearing in the error characteristic curve of the turbo code or the low density parity check code shown in FIG. Can be utilized. For example, an array low-density parity-check code (LDPC) with a structured uniform row and column distribution has the property of reducing the error floor, while the non-uniform random low-density parity check with random and non- The code has a disadvantage that the performance of the error waterfall region is excellent but the error floor becomes high. Therefore, the first encoder constituting the twin coder of FIG. 1 uses an H-matrix for generating an array low-density parity check code, the second encoder uses a non-uniform random low-density parity check code and reflects all twin code characteristics By applying the modified structure of the decoder, the performance of the error waterfall area and the error floor area can be improved at the same time.

The algorithm applied to reduce the error floor is a sum-product algorithm. The sum-product algorithm does not correct bit errors trapped in a trapping set even if iterative decoding is performed. In order to solve such a problem, it is necessary to considerably reduce the bit error rate area where the error flooring phenomenon does not occur or occurs even if the error flooring occurs. The present invention proposes an adaptive sum-product algorithm of a method that does not require dictionary information for a trapping set by complementing the sum-product algorithm. The modified sum-product algorithm uses not only the hard decision transition pattern, which is a characteristic of the error variable node, but also the pattern of the failure check node. This is characterized by a two-stage decoding process as shown in the flowchart of FIG. Where I _max1 and I _max2 represent the maximum number of iterations of the iterative decoding in the first and second step decoding processes, respectively. And n is a counter indicating the number of times of decoding performed. The modified sum-product algorithm starts with step S100 of calculating an initial probability value of each variable node as in the original algorithm. And a step S200 of storing a hard decision transition result of the failure check node and the bit probability after performing the conventional sum-product algorithm is added. This information is used to detect the variable nodes included in the trapping set in the two-step decoding process. Next, a syndrome check is performed to determine whether the result is 0 (S300). If the syndrome test result is 0, the decoding is completed (S1200) because the equation (1) is satisfied .

...수식(1)

... (1)

는

부호어 벡터,

는

의 전치행렬(transpose),

은

영행렬(zero matrix)이다.here,

The

Codeword vector,

The

Transpose,

silver

Zero matrix.

이 I_max1인지 확인하는 단계(S400);를 거쳐서 I_max1으로 정해진 1단계의 최대 횟수까지 반복복호를 수행한다. 제안된 알고리즘은 1단계의 반복복호가 완료되었음에도 불구하고 상기 수식(1)이 만족되지 않으면 그 원인이 트랩핑 세트인지를 판단하는 단계(S500);을 수행하여 트랩핑 세트가 원인이 아니면 1단계 과정만으로 복호를 종료한다. 여기서 상기 S400 단계에서

이 I_max1이 아니라면 상기 S200 단계로 회귀한다. 상기 트랩핑 세트에 의한 복호오류가 아닐 경우 불필요한 추가 연산에 의한 복호 복잡도의 증가와 시간지연을 방지한다. 하지만 트랩핑 세트가 원인인 것으로 판단되면 2단계 복호과정이 시작된다. 본 발명의 수정 합-곱 알고리즘에서는 이 판단을 위한 기준으로 실패 검사노드의 최소 개수를 이용하는 것을 특징으로 한다. 상기 실패 검사노드의 개수가 가장 적은 경우 비트오류의 수도 가장 적어지는 경향이 있으므로 2단계 복호과정은 모든 변수노드의 비트 확률을 이때의 값으로 초기화시키는 단계(S600);로 시작된다. 그리고 트랩핑 세트에 해당하는 변수노드를 찾기 위하여 1단계에서 저장된 실패 검사노드 패턴과 경판정 천이패턴에 대한 적절한 검사영역(check region)을 설정하는 단계(S700);를 수행한 다음 해당 영역에 존재하는 실패 검사노드들의 집합을 만든다. 그리고 비트 확률의 경판정 천이패턴을 이용하여 데이터의 천이가 발생하면서 실패 검사노드와 연결된 변수들의 집합을 만든다. 트랩핑 세트에 포함된 변수노드들은 이 세트에 속한 검사노드에만 연결되는 특성이 있으므로 검색된 변수 노드에 연결된 모든 검사노드가 실패 검사노드 집합의 원소이면 이 변수노드는 트랩핑 세트에 포함된 것으로 간주한다. 이러한 방법으로 구한 변수노드들의 비트를 반전시키는 단계(S800);를 수행하여 오류의 일부를 인위적으로 수정한 다음 합-곱 알고리즘 분석 단계(S900);를 수행하고 신드롬 검사를 재수행하여 그 결과가 0인지 확인하는 단계(S1000);를 수행하여 그 결과가 0이면 반복복호를 종료하는 단계(S1200)를 수행하고 그 결과가 0이 아니면

이 I_max1인지 재확인하는 단계(S1100);를 수행하며

이 I_max1이면 반복복호를 종료하는 단계(S1200)를 수행한다. 전술한 바와 같이 본 발명의 수정 합-곱 알고리즘은 반복복호를 수행함으로써 트랩핑 세트 구조를 해체하고 이에 포함된 오류를 정정하는 것을 특징으로 한다.However, if it is determined in step S300 that the syndrome test result is not 0, a counter indicating the number of times of decoding

The I step (S400) to determine whether _max1; via performs iterative decoding to the maximum number of times the step designated by I _max1. The proposed algorithm performs step S500 if it is determined that the cause is a trapping set (S500) even though the iterative decoding of the first step is completed, if the above equation (1) is not satisfied, The decoding is terminated only by the process. In step S400,

If it is not I _max1 , the process returns to step S200. If the decoding error is not caused by the trapping set, the increase in decoding complexity and time delay due to unnecessary additional operations are prevented. However, if it is determined that the trapping set is the cause, the two-step decoding process starts. In the modification-multiplication algorithm of the present invention, the minimum number of failure check nodes is used as a criterion for this determination. If the number of failure check nodes is the smallest, the number of bit errors tends to be smallest. Therefore, the two-step decoding process initializes the bit probabilities of all the variable nodes to the value at this time (S600). In step S700, an appropriate check region for the failure check node pattern and the hard decision transition pattern stored in step 1 is searched to find a variable node corresponding to the trapping set. Create a set of failed check nodes. Then, a set of variables connected to the failure check node is generated while a data transition occurs by using a hard decision transition pattern of bit probability. Since the variable nodes included in the trapping set are connected only to the check nodes belonging to this set, if all the check nodes connected to the detected variable node are elements of the failure check node set, this variable node is regarded as being included in the trapping set . (S800) of inverting the bits of the variable nodes obtained by the above method, and then performing artificial correction of a part of the error, performing a sum-product algorithm analysis step (S900), re-executing the syndrome test, (S1000); and if the result is 0, ending the iterative decoding (S1200). If the result is not 0

(S1100) of _confirming whether or not I _max1 is performed

If it is I _{max1, the} iterative decoding is terminated (S1200). As described above, the modification-multiplication algorithm of the present invention is characterized by disassembling the trapping set structure by performing iterative decoding and correcting the errors contained therein.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, will be. Accordingly, the true scope of the present invention should be determined only by the appended claims.

100: information source 110: bit string b
200: first coder 210: error correction code c ₁
300: second coder 310: error correction code c ₂
400: modulator 500: transmitter
600: Receiving terminal 700: Demodulator
710: demodulation bit string c ₁ '720: demodulation bit string c ₂ '
800: first decoder 810: decoded bit string b ₁ '
900: second decoder 910: decoded bit string b ₂ '
1000: Data destination 1010: Final decoded bit string b '

Claims (5)

In the twin code system,
An information source 100 for generating bit stream b 110;
A first encoder 200 for encoding the bit string b 110 and outputting an error correction code c ₁ 210;
A second coder 300 for encoding the bit string b 110 simultaneously with the first coder 200 and outputting an error correction code c ₂ 310;
A modulator for independently modulating a signal encoded by the twin coder including the error correcting code c ₁ 210 and the error correcting code c ₂ 310 through the first encoder 200 and the second encoder 300, (400);
A transmitter 500 receiving the modulated signal through the modulator 400;
A receiving end 600 for decoding the twin code;
A demodulator 700 demultiplexing the signal sequence received through the receiver 600 into two sub signal sequences and independently demodulating to generate a demodulation bit stream c ₁ '710 and a demodulation bit stream c ₂ '720;
A first decoder 800 for decoding the demodulation bit stream c ₁ '710;
A second decoder 900 for decoding the demodulation bit stream c ₂ '720;
Wherein in a first decoder 800. The decoded bit sequence b ₁ are decoded independently generated by the '810 and the second decoder 900, the decoded bit string b ₂ generated is decoded independently via "910 And a data destination 1000 where a configured final decoded bit string b '1010 arrives,
The trapping set structure is disassembled by performing iterative decoding to reduce the error floor appearing in the error characteristic curve of the low density parity check code, and the error included in the trapping set structure is corrected to obtain the advance information on the trapping set The twin code system using the modified sum-product algorithm. The method according to claim 1,
In order to increase the reliability of the decoded bit string b ₁ '810 and the decoded bit string b ₂ ' 910, the demodulation bit string c ₁ '710 and the demodulation bit string c ₂ ' A twin code system that utilizes the reliability information generated during the decoding process. delete A method for implementing a twin code system using a twin code system as set forth in any one of claims 1 to 2,
Calculating an initial probability value of the variable node (S100);
Storing a hard decision transition result of the failure check node and the bit probability (S200);
Performing a syndrome test and checking whether the result is 0 (S300);
The counter of the number of decodes performed

Confirming that the I _max1 (S400);

... (1)
here,

The

Codeword vector,

The

≪ / RTI >

silver

Young Matrix
Determining whether the cause is a trapping set if the equation (1) is not satisfied (S500);
Initializing a bit probability of the variable node (S600);
(S700) setting an inspection region for the failure check node pattern and the hard decision transition pattern;
Inverting the bits of the variable nodes (S800);
A correction sum-product algorithm analysis step S900;
Re-executing the syndrome test and checking whether the result is 0 (S1000);
If the syndrome test result is not 0

(S1100) _confirming whether I _max is I _max1 ;
remind

And terminating the iterative decoding if the _Imax is equal to _Imax1 (S1200). delete

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