KR101736927B1 - Liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same. A gate line and a data line arranged on the lower substrate so as to cross each other at right angles to define a pixel region; A light blocking pattern disposed on both sides of the data line and spaced apart from and parallel to the data line; A thin film transistor formed at a point of intersection of the gate line and the data line; A projection disposed on a predetermined portion of the gate wiring; An active layer disposed under the data line and the protrusion, the active layer protruding from the side surface of the data line and the protrusion; A protection layer formed on the entire surface of the lower substrate including the data lines and the protrusions and exposing the thin film transistors; A pixel electrode formed on the protective film and electrically connected to the thin film transistor; A first column spacer formed on an upper substrate facing and bonded to the lower substrate, the first column spacer corresponding to the projection provided on the lower substrate, and the second column spacer corresponding to the non-pixel region of the lower substrate; And a liquid crystal layer formed in a space between the lower substrate and the upper substrate.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that effectively utilizes a tail of an active layer.

As the information society has developed, the demand for display devices has been gradually increasing in various forms. In response to this demand, recently, a liquid crystal display device (LCD), a plasma display panel (PDP), an organic electro luminescent display (OELD) Vacuum Fluorescent Display) have been studied, some of which have already been used as display devices in various devices.

Among them, the LCD is the most widely used in place of a CRT (Cathode Ray Tube) for the purpose of a portable image display device because of its excellent image quality, light weight, thinness and low power consumption, A television monitor for receiving and displaying a broadcast signal, a computer monitor, and the like.

In order to use such a liquid crystal display device as a general screen display device in various parts, it is said that it is important to realize high quality image such as high definition, high brightness, and large area while maintaining characteristics of light weight, thin shape and low power consumption .

Such a liquid crystal display device can be divided into a liquid crystal injection method and a liquid crystal dropping method depending on its manufacturing method.

Among them, a liquid crystal dropping liquid crystal display device is subjected to a lapping process after dropping a liquid crystal. When a ball spacer is used, the ball spacer rolls along with the liquid crystal on the substrate surface, and it may be difficult to maintain a proper cell gap.

Therefore, a column spacer which is fixed to a predetermined portion on a substrate has been proposed in a liquid crystal display device of a liquid crystal dropping method. This liquid crystal drop type liquid crystal display device is formed by forming a column spacer on a color filter substrate, dropping liquid crystal on a TFT substrate, and attaching two substrates together to form a panel.

However, although not shown in the drawings, the liquid crystal display device of the liquid drop loading type has a large contact area between the column spacers and the lower substrate facing the column spacer, The upper substrate can not be restored to the original state for a long time after moving in the touch direction. In such a case, a portion where the liquid crystal (which is filled in the space between the upper and lower substrates except the column spacer) around the touch is higher than the cell gap of the other portion defined by the height of the column spacer, and a finger, Liquid crystal is scattered in the past touch area, and normal liquid crystal is not driven due to insufficient or excessive liquid crystal in the touch area and the touch peripheral area, resulting in a touch failure in which the touch area and its boundary are observed as unevenness.

The reason why such a touch failure occurs in a liquid crystal display device in which a column spacer is formed is that the column spacer is fixed on one substrate and contacts with the counter substrate in a planar shape (upper surface contact) have.

Accordingly, a liquid crystal display device having a gap maintaining column spacer and an anti-dropping column spacer has been proposed in order to solve such a problem that a touch defect occurs in the touch portion and the boundary thereof.

A conventional liquid crystal display device having a gap maintaining column spacer and an anti-dropping column spacer will be described with reference to FIGS. 1 to 4. FIG.

1 is a plan view of a conventional liquid crystal display device having a dual column spacer.

FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, and is a cross-sectional view of a conventional liquid crystal display device having a dual column spacer.

3 is an enlarged cross-sectional view of a laminated structure of an active layer and a projection formed on a gate wiring in a liquid crystal display device having a dual color spacer according to the related art.

4 is an enlarged cross-sectional view of a stacked structure of an active layer and a data line of a data line in a liquid crystal display device having a dual color spacer according to the related art.

FIG. 5 is a cross-sectional view taken along the line V-V in FIG. 1, and schematically shows a light leakage occurring through spaced gaps between a data line and a light blocking pattern and a shear phenomenon at the time of adhesion.

6 is a cross-sectional view taken along line V-V in Fig. 1, and is a plan view of a data line and a light blocking pattern.

1 and 2, a liquid crystal display device according to the related art includes a lower substrate 11 and an upper substrate 41 which are largely opposed to each other, and a lower substrate 11 and an upper substrate 41 which are opposed to each other and between the lower substrate 11 and the lower substrate 41 And a filled liquid crystal layer 51.

A gate line 13 and a data line 21a are vertically arranged so as to cross each other to define a pixel region on the lower substrate 11. Each of the gate lines 13 and the data lines 21a A thin film transistor T is formed at a crossing portion, and a pixel electrode 29 is formed in each pixel region.

The thin film transistor T includes a gate electrode 13a protruded from the gate wiring 13, an active layer 17a covering the gate electrode 13a, and an active layer 17a covering both sides of the active layer 17a. A source electrode 21c protruding from the data line 21a and a drain electrode 21d spaced apart from the source electrode 21c by a predetermined distance.

Further, as shown in FIG. 3, a projection 23 is formed on a predetermined portion of the gate wiring 13. The protrusion 23 has a stacked structure of a metal layer pattern 21d at the time of forming the data line 21a and an ohmic contact layer 19a and an active layer 17a located under the metal layer pattern 21d. At this time, the active layer 17a under the metal layer pattern 21d constituting the protrusion 23 slightly protrudes laterally to form a tail as shown in "A" in Fig. 3, And acts as an additional contact surface of the gap column spacer 49a.

The gate wiring 13 is formed on the lower substrate 11 for insulation between the metal wirings and the gate insulating film 15 is formed on the entire surface of the substrate including the gate wiring 13. The gate insulating film 15, the protective film 27 is formed. Here, the protrusion 23 maintains the insulation between the gate wiring 13 and the data wiring 21a under the gate insulating film 15 at the lower part thereof.

4, the active layer 17a is formed to be inclined from the side surfaces of the source electrode 21c and the drain electrode 21d. This phenomenon occurs when a part of the active layer 17a is etched by a wet etching process or a dry etching process in forming the source electrode 21c and the drain electrode 21d.

A pixel electrode 29 is formed on the entire surface of the pixel region formed by intersecting the gate line 13 and the data line 21a and is electrically connected to the drain electrode 21d.

In addition, a light blocking pattern 13b is formed on the side of the data line 21a so as to block light incident on the data line 21a in parallel and away from the data line 21a.

On the other hand, a black matrix layer 43 (not shown) for blocking non-pixel regions (for example, gate lines, data lines, and thin film transistors) except for the pixel region is formed on the upper substrate 41, And a color filter layer 45 in which R, G, and B pigments are formed in correspondence with the respective pixel regions that are recognized in the black matrix layer 43 are formed in the color filter layer 45. The color filter layer 45, A common electrode 47 is formed on the entire surface of the substrate 41.

In addition, a first column spacer 49a for maintaining a cell gap at a predetermined portion above the common electrode 47, a second column spacer 49a spaced apart from the lower substrate 11 by a predetermined distance, A spacer 49b is formed.

The arrangement position of the first column spacer 49a corresponds to the projection 23 and the arrangement position of the second column spacer 49b is the position of the gate wiring 13 excluding the projection 21, Or the upper portion of the data wiring 23.

In this case, when the lower substrate 11 and the upper substrate 41 are attached to each other, the first column spacer 49a is brought into contact with the projection 23 by the pressure at the time of adhering, and the second column spacer 49b are spaced apart from the uppermost protective film 27 of the lower substrate 11 to some extent.

A method of manufacturing a liquid crystal display device according to the related art having the above structure will be described with reference to FIGS. 7A to 7E.

7A to 7E are cross-sectional views of a manufacturing process of a liquid crystal display according to a related art.

7A, a gate wiring 13 and a gate electrode 13a protruding from the gate wiring 13 are first formed on a transparent lower substrate 11, and a data wiring (not shown) formed in a subsequent process, (See 21a in FIG. 7B), a light blocking pattern 13b is formed which is spaced apart from the data line 21a and blocks light in parallel.

Next, a gate insulating film 15, an amorphous silicon layer 17, an amorphous silicon layer 19 containing impurities, and a conductive metal layer 21 are sequentially deposited on the entire surface of the substrate including the gate wiring 13.

Then, a photoresist having a high transmittance is applied on the conductive metal layer 21 to form a photoresist layer 23.

The photoresist layer 23 is then subjected to an exposure process using a diffraction mask 25 consisting of a light shielding portion 25a, a transflective portion 25b and a transmissive portion 25c. The light shielding portion 25a of the diffraction mask 25 is located above the photoresist layer 23 corresponding to the source and drain electrode formation regions and the protrusion formation region and the data wiring formation region, The transflective portion 25b is located above the photoresist film 237 corresponding to the channel formation region of the thin film transistor.

Then, as shown in FIG. 7B, the photoresist layer 23 is selectively patterned through the exposure process and then the development process to form a photoresist pattern 23 on the source and drain electrode formation areas, the projection formation areas, and the data wiring formation area, A photoresist pattern 23b is formed in the channel forming region. At this time, the photoresist pattern 23a on the source and drain electrode formation areas and the upper surface of the protrusion formation area maintains the thickness of the photoresist pattern 23a because the photoresist pattern 23a does not transmit light. However, ) Is transmitted through a part of the light and is removed by a predetermined thickness.

Next, the conductive metal layer 21, the amorphous silicon layer 19 containing impurities and the amorphous silicon layer 17 are sequentially patterned using the photoresist pattern 23a and 23b as a mask to form the gate wiring 13 The active layer 17a, the ohmic contact layer 19a and the conductive metal layer pattern 21 are formed on the gate insulating film 15 corresponding to the gate electrode 13a together with the data line 21a forming the pixel region crossing vertically, And an active layer 17a, an ohmic contact layer 19a and a metal layer pattern 21b are formed on the gate insulating film 15 corresponding to a predetermined portion of the gate wiring 13. [ At this time, the laminated structure of the active layer 17a, the ohmic contact layer 19a, and the metal layer pattern 21b constitutes the protrusion 23.

Then, although not shown in the drawing, the photoresist pattern 25b on the channel formation region is completely removed through an ashing process. At this time, a part of the thickness of the photoresist pattern 23a located at the source electrode and drain electrode formation regions and the data wiring formation region is also removed during the ashing process.

Then, as shown in FIG. 7C, the exposed conductive metal layer 21 is selectively patterned using the photoresist pattern 23a having a part of the thickness removed as a mask to form the source electrode 21b and the source electrode 21c, And a drain electrode 21d spaced apart from each other.

7D, a protective film 27 is deposited on the entire surface of the substrate including the data line 21a, the source electrode 21c, the drain electrode 21d, and the protrusion 23. Next, as shown in FIG.

Then, the protective film 27 is selectively patterned by photolithography using a mask to form a drain contact hole (not shown) for exposing the drain electrode 21d.

Subsequently, a transparent conductive material layer (not shown) is deposited on the passivation layer 27 including the drain contact hole (not shown), and then selectively patterned to selectively electrically pattern the pixel electrode with the drain electrode 21d By forming the pixel electrode 29 to be connected, the process of manufacturing the lower array substrate is completed.

 Thereafter, a black matrix layer 41 is formed on a predetermined portion of the upper substrate 41, which is adhered to the lower substrate 11, to block light incident on the region excluding the pixel region.

Next, R, G, and B color filter layers 45 are formed on the pixel regions of the upper substrate 41 divided by the black matrix layer 43 for each pixel region.

Next, a common electrode 47 is formed on the entire surface of the upper substrate 41 including the black matrix layer 43 and the color filter layer 45.

Then, a photosensitive resin layer (not shown) is coated on the common electrode 47, and then the photosensitive resin layer (not shown) is patterned through a patterning process using a mask to form projections The upper substrate array manufacturing process is completed by forming the first column spacer 49a for holding the gap and the second column spacer 49b for preventing contact in contact with the substrate 23.

7E, liquid crystal is dropped on the lower substrate 11 to form a liquid crystal layer 51, and then the lower substrate 11 and the upper substrate 41 are bonded together. At this time, when the lower substrate 11 and the upper substrate 41 are attached to each other, the first column spacer 49a comes into contact with the projection 23 by the pressure at the time of adhering, and the second column spacer 49b Is spaced apart from the protective film 27, which is the uppermost layer of the lower substrate 11, to some extent.

As described above, according to the conventional liquid crystal display device and the manufacturing method thereof, there are the following problems.

According to the conventional liquid crystal display, when an electroconductive metal layer is etched to form a data line, an active layer tail is generated as indicated by "A" in FIG. 3, tail is formed in the protrusion portion including the source electrode, the drain electrode and the data line, and it is impossible to increase a local active layer tail.

According to the prior art, as shown in "B" of FIG. 4, the active layer is etched in a sloped shape while being subjected to a wet etching process, a dry etching process, and an ashing process performed for patterning the conductive metal layer Thereby forming a tail.

According to the related art, if the light blocking pattern blocking the light incident from the light source and the distance to the end of the black matrix layer are reduced, light leakage occurs in the stepped portion as shown in FIG.

5 and 6, after the lower array substrate fabrication process and the color filter array substrate fabrication process are completed, the light leakage pattern of the step light mask When the overlay is distorted at the time of cementing in the cell laminating process, the cemented light leakage occurs at the stepped portion, resulting in quality defects.

In addition, according to the related art, if a short between the light blocking pattern and the data wiring occurs, the repair becomes impossible and the defect ratio increases, and the GDS defect due to the step between the unnecessary data wiring and the light blocking pattern weak.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems, and it is an object of the present invention to improve the contact with the column spacers for gap maintenance by using the tail of the active layer, And a liquid crystal display device capable of preventing light leakage.

According to an aspect of the present invention, there is provided a liquid crystal display device including a lower substrate and a lower substrate, the gate lines and the data lines arranged perpendicularly to each other to define pixel regions, A thin film transistor formed at a point of intersection of the gate wiring and the data wiring, a first active layer disposed under the data wiring and including a tail portion projecting from both sides of the data wiring, A pixel electrode formed on the passivation layer and electrically connected to the thin film transistor, an upper substrate and a lower substrate which are adhered to and adhered to the lower substrate, And a liquid crystal layer formed in a space between the first active layer and the second active layer, It can cheopdoel.
Further, the liquid crystal display device according to the present invention may include a projection formed of a laminated structure of metal layer patterns on the second active layer and the second active layer formed at predetermined portions on the gate wiring.
The liquid crystal display according to the present invention may include a first column spacer formed on the upper substrate and corresponding to the projection, and a second column spacer corresponding to the non-pixel region of the lower substrate.
In the liquid crystal display device according to the present invention, the second active layer may include a tail portion protruding from both sides of the metal layer pattern.
Further, in the liquid crystal display device according to the present invention, the first column spacer may be in contact with the frame portion of the second active layer protruding to the side of the projection together with the projection.
In the liquid crystal display device according to the present invention, the second column spacer may be in contact with the frame portion of the first active layer.
The liquid crystal display device according to the present invention includes a black matrix layer formed on the upper substrate corresponding to the gate wiring, the data line, and the thin film transistor, a color filter layer, a black matrix layer, and a color filter layer, And may include a common electrode formed on the substrate.

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According to the liquid crystal display device of the present invention, by increasing the size of the active layer tail of the projection contacting the gap maintaining column spacer, the contact area of the projection contacting the gap maintaining column spacer is increased, .

According to the liquid crystal display device of the present invention, in order to maximize the transmittance of the panel, the tail portion of the active layer protrudes to the side of the data line even if the width of the black matrix layer is reduced, , The light leakage that has been caused by the difference in level between the data line and the light blocking pattern is prevented. That is, when manufacturing a liquid crystal display device using a 4-mask process, the tail portion of the active layer is largely formed on the side of the data line, so that the light coming out from the side surface of the step portion is cut off, So that no covalent light leakage occurs.

Therefore, according to the present invention, even if the width of the black matrix layer is reduced in order to maximize the transmittance of the panel, the tail portion of the active layer overlaps with the light blocking pattern to prevent light leakage, thereby increasing the transmittance of the panel.

1 is a plan view of a conventional liquid crystal display device having a dual column spacer.
FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, and is a cross-sectional view of a conventional liquid crystal display device having a dual column spacer.
3 is an enlarged cross-sectional view of a column spacer for holding a gap in contact with a projection formed on a gate wiring in a liquid crystal display device having a dual color spacer according to the related art.
4 is an enlarged cross-sectional view of a stacked structure of an active layer and a data line of a data line in a liquid crystal display device having a dual color spacer according to the related art.
FIG. 5 is a cross-sectional view taken along the line V-V in FIG. 1, and schematically shows a light leakage occurring through spaced gaps between a data line and a light blocking pattern and a shear phenomenon at the time of adhesion.
6 is a cross-sectional view taken along line V-V in Fig. 1, and is a plan view of a data line and a light blocking pattern.
7A to 7E are cross-sectional views of a manufacturing process of a liquid crystal display according to a related art.
8 is a plan view of a liquid crystal display device having a dual column spacer according to the present invention.
FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 8, and is a cross-sectional view of a liquid crystal display device having a dual column spacer according to the present invention.
10 is an enlarged cross-sectional view schematically showing a gap spacer for holding a gap in contact with an active layer frame formed on a gate wiring in a liquid crystal display device having a dual color spacer according to the present invention.
11 is an enlarged cross-sectional view of an enlarged view of an active layer tail portion of a data line in a liquid crystal display device having a dual color spacer according to the present invention.
FIG. 12 is a cross-sectional view taken along the line XII-XII in FIG. 8, and schematically shows a state in which light leakage is prevented by the active layer tail portion on the data wiring side.
Fig. 13 is a cross-sectional view taken along line XII-XII in Fig. 1, and is a plan view of a data line and a light blocking pattern.
14A to 14V are process sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

8 and 9, a liquid crystal display device including a projection according to the present invention includes a gate wiring 103a and a data wiring 103a, which are arranged on the lower substrate 101 so as to cross each other at right angles, (113a); A light blocking pattern 103c disposed on both sides of the data line 113a and spaced apart from the data line 113a in parallel; A thin film transistor T formed at the intersection of the gate wiring 103a and the data wiring 113a; A projection 114 disposed at a predetermined portion of the gate wiring 103a; An active layer disposed under the data lines 113a and the protrusions 114 and protruding from the side surfaces of the data lines 113a and the protrusions 114; A protective film 119 formed on the entire surface of the lower substrate including the data line 113a and the protrusion 114 and exposing the thin film transistor T; A pixel electrode 125a formed on the passivation layer 119 and electrically connected to the drain electrode 113d; A black matrix layer 143 formed on the upper substrate 141 facing and adhered to the lower substrate 101 to block light; A color filter layer 145 formed in a pixel region divided by the black matrix 143; A common electrode 147 formed on the entire surface of the upper substrate including the color filter layer 145 and the black matrix layer 143; A first column spacer 149a formed on the common electrode 145 and corresponding to the protrusion 114 provided on the lower substrate 101 and a second column spacer 149b corresponding to the non-pixel region of the lower substrate 101 A second column spacer 149b; And a liquid crystal layer 161 formed in a space between the lower substrate 101 and the upper substrate 141.
The active layer may be formed separately at a lower portion of the data line and at a lower portion of the protrusion, and the first active layer and the second active layer, respectively, will be described as necessary. However, the description of the common features will be described as the active layer.

A gate wiring 103a and a data wiring 113a are arranged so as to vertically cross each other to define a pixel region on the lower substrate 101. Each of the gate wiring 103a and the data wiring 113a A thin film transistor T is formed at a crossing portion, and a pixel electrode 129a is formed in each pixel region. At this time, a common electrode (not shown) alternating with the pixel electrode 129a may be formed.

The thin film transistor T includes a gate electrode 103a protruding from the gate wiring 103, an active layer 109a covering the gate electrode 103a, and an active layer 109a covering both sides of the active layer 109a A source electrode 113c protruding from the data line 113a and a drain electrode 113d spaced apart from the source electrode 113c by a predetermined distance.

The protrusion 114 is formed on a predetermined portion of the gate wiring 103a and has a stacked structure of the active layer 109a, the ohmic contact layer 111a, and the metal layer pattern 113b. At this time, as shown by "C" in FIG. 10, a bottom portion 109b of the active layer 109a below the side surface of the projection 114 protrudes.

Therefore, due to the tail portion 109b protruding from the active layer 109a under the protrusion 114, the contact area of the protrusion 114 with the gap maintaining first column spacer 149a provided on the upper substrate 141 increases So that the supporting force by the external force increases accordingly.

The gate wiring 103a is formed on the lower substrate 101 for insulation between the metal lines and the gate insulating film 107 is formed on the entire surface of the substrate including the gate wiring 103a. The protective film 119 is formed. Here, the protrusion 114 maintains insulation between the gate wiring 103 and the data wiring 113a via a gate insulating film 107 at a lower portion thereof.

11, the active layer 109a under the data line 113a protrudes from the side surface of the data line 113a. At this time, as shown in FIGS. 12 and 13, the frame portion 109b overlaps the light blocking pattern 103c that is spaced apart in parallel with the data line 113a and blocks light.

Therefore, in order to maximize the transmittance of the panel, the tail portion 109b of the active layer 109a protrudes to the side of the data line 113a even if the width of the black matrix layer is reduced, and the tail portion 109b of the active layer 109a Is overlapped with the light intercepting pattern 103c, light leakage that has been caused due to the difference in level between the data interconnection and the light intercepting pattern is prevented.

On the other hand, a black matrix layer 143 (not shown) for blocking non-pixel regions (for example, gate lines, data lines, and thin film transistors) except for the pixel region is formed on the upper substrate 141 bonded to the lower substrate 101 And a common electrode 147 formed on the entire surface of the upper substrate 141 including the color filter layer 145 are formed on the color filter layer 145 in which R, G, and B pigments are sequentially formed for each pixel region.

A first column spacer 149a for maintaining a cell gap at a predetermined portion above the common electrode 147 and a second column spacer 149b spaced apart from the lower substrate 101 by a predetermined distance .

Here, the height of the first column spacer 149a is equal to or greater than the height of the second column spacer 149b, all of which are formed on the upper substrate 141. The arrangement position of the first column spacer 149a corresponds to the protrusion 114 and the arrangement position of the second column spacer 149b is the position of the gate wiring 103 or data And corresponds to the upper portion of the wiring 113a.

In this case, when the lower substrate 101 and the upper substrate 141 are attached to each other, the first column spacer 149a is brought into contact with the projection 114 due to the pressure at the time of adhering, and the second column spacer 149b are spaced apart from the protective film 119, which is the uppermost layer of the lower substrate 101, to some extent.

A method of manufacturing a liquid crystal display device according to the present invention will be described with reference to FIGS. 14A to 14V.

14A to 14V are cross-sectional views illustrating manufacturing steps of a liquid crystal display device according to the present invention.

14A, a first conductive metal layer 103 is deposited on a transparent insulating substrate 101 by a sputtering method. At this time, the first conductive metal layer 103 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten At least one selected from the group of conductive metals including titanium (MoTi), copper / moly titanium (Cu / MoTi) is used.

Next, as shown in FIG. 14B, a first photoresist layer 105 is coated on the first conductive metal layer 103, exposed and developed through a photolithography process using a mask to form a first photoresist pattern 105a ).

14C and 14D, the first conductive metal layer 103 is selectively patterned using the first photoresist pattern 105a as a mask to form a gate wiring 103 and a vertical (See Fig. 12, "103c") for preventing light from leaking from the side of the data wiring (not shown) at the same time together with the gate electrode 103b extending so far.

14E, the first photoresist pattern 105a is removed and then a gate insulating film 107 and an amorphous silicon layer (not shown) are formed over the entire surface of the substrate including the gate wiring 103 and the gate electrode 103a 109, an impurity-containing amorphous silicon layer 111, and a second conductive metal layer 113 are sequentially deposited. At this time, the second conductive metal layer 113 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten At least one selected from the group of conductive metals including titanium (MoTi), copper / moly titanium (Cu / MoTi) is used.

Then, as shown in FIG. 14F, a photo-resist having a high transmittance is coated on the second conductive metal layer 113 to form a second photoresist layer 115.

The second photoresist layer 115 is then subjected to an exposure process using a diffraction mask 117 consisting of a light intercepting portion 117a, a transflective portion 117b and a transmissive portion 117c. The light blocking portion 117a of the diffraction mask 117 is located on the second photoresist layer 115 corresponding to the data wiring, the source and drain electrode forming regions and the protrusion forming region, The transflective portion 117b of the TFT is located on the second photoresist layer 115 corresponding to the channel forming region of the thin film transistor and the tee portion forming region of the active layer under the protrusion and the tee forming region of the active layer below the data wiring. At this time, in addition to the diffraction mask 117, a mask using a diffraction or transmission effect of light, for example, a half-tone mask or another mask may be used.

Then, as shown in FIG. 14G, the second photoresist layer 115 is selectively patterned through a development process after the exposure process to form a data line, a source electrode and a drain electrode formation region and a protrusion formation region, And the second photoresist pattern 115a and 117b are formed on the top and bottom portions of the active layer and the bottom portion of the data line, respectively. At this time, since the second photoresist pattern 115a on the data line, the source electrode and the drain electrode formation area and the protrusion formation area does not transmit light, the thickness of the second photoresist layer 115 is maintained, The second photoresist pattern 115b on the top surface of the active layer under the data line and the second photoresist pattern 115b on the bottom of the data line is partially removed and removed by a predetermined thickness. That is, the second photoresist pattern 115b is thinner than the second photoresist pattern 115a on the data line, the source and drain electrode formation areas, and the protrusion formation area.

Next, as shown in FIG. 14H, the second conductive metal layer 113, the amorphous silicon layer 111 containing impurities and the amorphous silicon layer 109 are patterned using the second photoresist pattern 115a and 115b as a mask, The active layer 109a and the metal layer pattern (not shown) are formed on the gate insulating film 107 corresponding to the gate electrode 103b and the active layer 109a and the ohmic contact layer 109b are formed in the data wiring forming region, An active layer 109a, an ohmic contact layer (not shown), and a metal layer pattern (not shown) are formed on the gate insulating film 107 corresponding to a predetermined portion of the gate wiring 103, (Not shown).

Then, as shown in FIG. 14I, the second photoresist pattern 115b on the active layer side of the channel formation region and the lower portion of the protrusion and the upper portion of the active layer side of the data line is completely removed through an ashing process, do. At this time, a part of the thickness of the first photoresist pattern 115a on the data wiring, the source and drain electrodes and the protrusion forming area is also etched through the ashing process. Accordingly, the metal layer pattern (not shown) on the active layer portion of the channel formation region and the lower portion of the protrusion and the active layer tailing region below the data line are exposed to the outside.

Next, as shown in FIG. 14J, the second conductive metal layer 113 is selectively patterned using the second photoresist pattern 115a having a part of the thickness removed as a mask, so as to cross A source electrode 113c extending from the data line 113a and a drain electrode 113d spaced apart from the source electrode 113c are formed with the data line 113a and the projection 113b.

At this time, the active layer 109a under the data line 113a is formed with a tail portion 109b from the side surface of the data line 113a. As shown in FIGS. 12 and 13, the frame portion 109b overlaps the light blocking pattern 103c that is spaced apart in parallel with the data line 113a and blocks light. Therefore, in order to maximize the transmittance of the panel, the tail portion 109b of the active layer 109a protrudes to the side of the data line 113a even if the width of the black matrix layer is reduced, and the tail portion 109b of the active layer 109a Is overlapped with the light intercepting pattern 103c, light leakage that has been caused due to the difference in level between the data interconnection and the light intercepting pattern is prevented.

The active layer 109a under the protrusions 114 is also formed with a tail portion 109b from the side of the protrusions 114. [ At this time, due to the tail portion 109b protruding from the active layer 109a under the protrusion 114, the contact area of the protrusion 114 with the first column spacer 149a provided for the gap between the upper substrate 141 and the upper substrate 141 increases So that the supporting force by the external force increases accordingly.

14K, after the second photoresist pattern 115a is removed, the source electrode 113c and the source electrode 113c extending from the data line 113a together with the data line 113a are formed. Then, A protective film 119 is deposited on the entire surface of the substrate including the spaced drain electrode 113d and then the third photoresist film 121 is coated thereon.

Then, as shown in FIG. 14L, the third photosensitive film 121 is exposed and developed by using a photolithography process using a mask to form a third photosensitive film pattern 121a.

Then, as shown in FIG. 14M, the protective film 121 is selectively patterned using the third photoresist pattern 121a as a mask to form a contact hole 123 exposing the drain electrode 113d.

Next, as shown in FIG. 14N, the third photoresist pattern 121a is removed, and a transparent conductive material layer 125 is deposited on the passivation layer 119 including the contact hole 123 by a sputtering method.

Next, as shown in FIG. 14O, a fourth photoresist layer 127 is coated on the transparent conductive material layer 125, and then exposed and developed using a photolithography process using a mask to form a fourth photoresist pattern 127a ).

14P, the transparent conductive material layer 125 is selectively patterned using the fourth photoresist pattern 127a as a mask to form a pixel electrode 125a electrically connected to the drain electrode 113d To complete the lower substrate array manufacturing process.

Thereafter, as shown in FIG. 14Q, a black matrix layer 143 (not shown) for blocking light incident on a predetermined region on the upper substrate 141, which is adhered to the lower substrate 101, ).

Next, as shown in FIG. 14 (r), R, G, and B color filter layers 145 are formed on the upper substrate 141 including the black matrix layer 143 by regions. At this time, the R, G, and B color filter layers 145 may or may not be formed on the upper substrate region corresponding to the gate and data lines including the pixel region.

A common electrode 147 is formed on the entire surface of the upper substrate 141 including the black matrix layer 143 and the color filter layer 145 as shown in FIG.

Then, as shown in FIG. 14 (t), the photosensitive resin layer 149 is thickly coated on the common electrode 147.

Then, the photosensitive resin layer 149 is selectively patterned through exposure and development using a mask to form first and second column spacers 149a and 149b having predetermined projections on the upper surface of a predetermined height Thereby completing the upper substrate array manufacturing process. At this time, the first column spacer 149a is a spacer for maintaining a cell gap, and the second column spacer 149b is spaced apart from the lower substrate 101 by a predetermined distance, I am responsible. The arrangement position of the first column spacer 149a corresponds to the projection 114 and the arrangement position of the second column spacer 149b is the position of the gate wiring 103a except for the projection 114. [ Or the upper portion of the data line 113a.

Next, liquid crystal is dropped onto the lower substrate 101 to form a liquid crystal layer 161. [

Subsequently, the lower substrate 101 and the upper substrate 141 are bonded together. At this time, when the lower substrate 101 and the upper substrate 141 are attached to each other, the first column spacer 149a comes into contact with the protrusion 114 due to the pressure at the time of adhering, and the second column spacer 149b Is spaced apart to some extent from the protective film 123 which is the uppermost layer of the lower substrate 101.

As described above, according to the liquid crystal display device according to the present invention, by increasing the size of the active layer tail of the protrusions contacting the gap maintaining column spacer, the contact area of the protrusions contacting the gap spacing column spacer increases, Thereby increasing the supporting force.

According to the liquid crystal display device of the present invention, in order to maximize the transmittance of the panel, the tail portion of the active layer protrudes to the side of the data line even if the width of the black matrix layer is reduced, , The light leakage that has been caused by the difference in level between the data line and the light blocking pattern is prevented. That is, when manufacturing a liquid crystal display device using a 4-mask process, the tail portion of the active layer is largely formed on the side of the data line, so that the light coming out from the side surface of the step portion is cut off, So that no covalent light leakage occurs.

Therefore, according to the present invention, even if the width of the black matrix layer is reduced in order to maximize the transmittance of the panel, the tail portion of the active layer overlaps with the light blocking pattern to prevent light leakage, thereby increasing the transmittance of the panel.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

101: lower substrate 103a: gate wiring
103b: gate electrode 103c: light blocking pattern
105: first photosensitive film 107: gate insulating film
109a: active layer 111a: ohmic contact layer
113: second conductive metal layer 113a: data wiring
113b: metal layer pattern 113c: source electrode
113d: drain electrode 114: projection
115: second photoresist film 117: diffraction mask 117a: light blocking portion 117b: semi-transparent portion 117c: transmitting portion 119: protective film 121: third photoresist film 123:
125: transparent conductive material layer 125a: pixel electrode
127: fourth photosensitive film 141: upper substrate
143: Black matrix layer 145: Color filter layer
147: common electrode 149a: first column spacer
149b: second column spacer

Claims (13)

A lower substrate;
A gate line and a data line arranged on the lower substrate so as to cross each other at right angles to define a pixel region;
A light blocking pattern disposed on both sides of the data line and spaced apart from and parallel to the data line;
A thin film transistor formed at a point of intersection of the gate line and the data line;
A first active layer disposed under the data line, the first active layer including a tail portion protruded from both sides of the data line;
A protection layer formed on a lower substrate region including the thin film transistor and the data line and exposing the thin film transistor;
A pixel electrode formed on the protective film and electrically connected to the thin film transistor;
An upper substrate facing and adhered to the lower substrate; And
And a liquid crystal layer formed in a space between the lower substrate and the upper substrate,
Wherein the first active layer overlaps with the light blocking pattern. delete delete The liquid crystal display according to claim 1, further comprising: a black matrix layer formed on the upper substrate in correspondence with the gate line, the data line, and the thin film transistor;
A color filter layer corresponding to the pixel region; And
And a common electrode formed on the upper substrate including the black matrix layer and the color filter layer. delete delete delete delete delete   The liquid crystal display device according to claim 1, further comprising a projection formed of a laminated structure of a second active layer formed on a predetermined portion of the gate wiring and a metal layer pattern formed on the second active layer. The liquid crystal display of claim 10, wherein the second active layer comprises a tail portion protruded from both sides of the metal layer pattern. The liquid crystal display of claim 10, further comprising a first column spacer formed on the upper substrate and corresponding to the projection, and a second column spacer corresponding to the non-pixel region of the lower substrate. 13. The liquid crystal display of claim 12, wherein the first column spacer is in contact with the projection of the second active layer protruding from the projection side.

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