KR101735222B1 - 해제 일관성 메모리 순서화 모델을 갖는 멀티-코어 컴퓨트 캐시 코히어런시 - Google Patents

해제 일관성 메모리 순서화 모델을 갖는 멀티-코어 컴퓨트 캐시 코히어런시 Download PDF

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KR101735222B1
KR101735222B1 KR1020157004705A KR20157004705A KR101735222B1 KR 101735222 B1 KR101735222 B1 KR 101735222B1 KR 1020157004705 A KR1020157004705 A KR 1020157004705A KR 20157004705 A KR20157004705 A KR 20157004705A KR 101735222 B1 KR101735222 B1 KR 101735222B1
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cache
programmable
shared
processor
graphics processor
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보후슬라프 리칠릭
충 렌 쳉
앤드류 에반 그루버
알렉세이 브이 부르드
콜린 크리스토퍼 샤프
에릭 디머스
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/302—In image processor or graphics adapter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020157004705A 2012-08-06 2013-08-05 해제 일관성 메모리 순서화 모델을 갖는 멀티-코어 컴퓨트 캐시 코히어런시 Active KR101735222B1 (ko)

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US201261680201P 2012-08-06 2012-08-06
US61/680,201 2012-08-06
US201361800441P 2013-03-15 2013-03-15
US61/800,441 2013-03-15
US13/958,399 2013-08-02
US13/958,399 US9218289B2 (en) 2012-08-06 2013-08-02 Multi-core compute cache coherency with a release consistency memory ordering model
PCT/US2013/053626 WO2014025691A1 (en) 2012-08-06 2013-08-05 Multi-core compute cache coherency with a release consistency memory ordering model

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KR101735222B1 true KR101735222B1 (ko) 2017-05-24

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JP (1) JP6062550B2 (https=)
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CN104520825B (zh) 2018-02-02
JP6062550B2 (ja) 2017-01-18
WO2014025691A1 (en) 2014-02-13
JP2015524597A (ja) 2015-08-24
US20140040552A1 (en) 2014-02-06
CN104520825A (zh) 2015-04-15
CA2864752A1 (en) 2014-02-13
KR20150040946A (ko) 2015-04-15
US9218289B2 (en) 2015-12-22

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