CA2864752A1 - Multi-core compute cache coherency with a release consistency memory ordering model - Google Patents

Multi-core compute cache coherency with a release consistency memory ordering model

Info

Publication number
CA2864752A1
CA2864752A1 CA2864752A CA2864752A CA2864752A1 CA 2864752 A1 CA2864752 A1 CA 2864752A1 CA 2864752 A CA2864752 A CA 2864752A CA 2864752 A CA2864752 A CA 2864752A CA 2864752 A1 CA2864752 A1 CA 2864752A1
Authority
CA
Canada
Prior art keywords
cache
processor
shared
programmable processor
variable data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CA2864752A
Other languages
English (en)
French (fr)
Inventor
Bohuslav Rychlik
Tzung Ren TZENG
Andrew Evan Gruber
Alexei V. Bourd
Colin Christopher Sharp
Eric Demers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CA2864752A1 publication Critical patent/CA2864752A1/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/302—In image processor or graphics adapter

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA2864752A 2012-08-06 2013-08-05 Multi-core compute cache coherency with a release consistency memory ordering model Pending CA2864752A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201261680201P 2012-08-06 2012-08-06
US61/680,201 2012-08-06
US201361800441P 2013-03-15 2013-03-15
US61/800,441 2013-03-15
US13/958,399 2013-08-02
US13/958,399 US9218289B2 (en) 2012-08-06 2013-08-02 Multi-core compute cache coherency with a release consistency memory ordering model
PCT/US2013/053626 WO2014025691A1 (en) 2012-08-06 2013-08-05 Multi-core compute cache coherency with a release consistency memory ordering model

Publications (1)

Publication Number Publication Date
CA2864752A1 true CA2864752A1 (en) 2014-02-13

Family

ID=50026664

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2864752A Pending CA2864752A1 (en) 2012-08-06 2013-08-05 Multi-core compute cache coherency with a release consistency memory ordering model

Country Status (6)

Country Link
US (1) US9218289B2 (https=)
JP (1) JP6062550B2 (https=)
KR (1) KR101735222B1 (https=)
CN (1) CN104520825B (https=)
CA (1) CA2864752A1 (https=)
WO (1) WO2014025691A1 (https=)

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Also Published As

Publication number Publication date
CN104520825B (zh) 2018-02-02
JP6062550B2 (ja) 2017-01-18
WO2014025691A1 (en) 2014-02-13
JP2015524597A (ja) 2015-08-24
US20140040552A1 (en) 2014-02-06
CN104520825A (zh) 2015-04-15
KR20150040946A (ko) 2015-04-15
US9218289B2 (en) 2015-12-22
KR101735222B1 (ko) 2017-05-24

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