JP6062550B2 - リリース一貫性メモリ順序付けモデルを用いたマルチコア計算キャッシュコヒーレンシ - Google Patents

リリース一貫性メモリ順序付けモデルを用いたマルチコア計算キャッシュコヒーレンシ Download PDF

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JP6062550B2
JP6062550B2 JP2015526608A JP2015526608A JP6062550B2 JP 6062550 B2 JP6062550 B2 JP 6062550B2 JP 2015526608 A JP2015526608 A JP 2015526608A JP 2015526608 A JP2015526608 A JP 2015526608A JP 6062550 B2 JP6062550 B2 JP 6062550B2
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cache
programmable
processor
shared
graphics processor
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Japanese (ja)
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JP2015524597A (ja
JP2015524597A5 (https=
Inventor
ライクリク、ボフスラフ
ゼン、ズン・レン
グルバー、アンドリュー・イバン
ボウルド、アレクセイ・ブイ．
シャープ、コリン・クリストファー
デマーズ、エリック
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/302—In image processor or graphics adapter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2015526608A 2012-08-06 2013-08-05 リリース一貫性メモリ順序付けモデルを用いたマルチコア計算キャッシュコヒーレンシ Active JP6062550B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201261680201P 2012-08-06 2012-08-06
US61/680,201 2012-08-06
US201361800441P 2013-03-15 2013-03-15
US61/800,441 2013-03-15
US13/958,399 2013-08-02
US13/958,399 US9218289B2 (en) 2012-08-06 2013-08-02 Multi-core compute cache coherency with a release consistency memory ordering model
PCT/US2013/053626 WO2014025691A1 (en) 2012-08-06 2013-08-05 Multi-core compute cache coherency with a release consistency memory ordering model

Publications (3)

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JP2015524597A JP2015524597A (ja) 2015-08-24
JP2015524597A5 JP2015524597A5 (https=) 2016-04-07
JP6062550B2 true JP6062550B2 (ja) 2017-01-18

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US (1) US9218289B2 (https=)
JP (1) JP6062550B2 (https=)
KR (1) KR101735222B1 (https=)
CN (1) CN104520825B (https=)
CA (1) CA2864752A1 (https=)
WO (1) WO2014025691A1 (https=)

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Also Published As

Publication number Publication date
CN104520825B (zh) 2018-02-02
WO2014025691A1 (en) 2014-02-13
JP2015524597A (ja) 2015-08-24
US20140040552A1 (en) 2014-02-06
CN104520825A (zh) 2015-04-15
CA2864752A1 (en) 2014-02-13
KR20150040946A (ko) 2015-04-15
US9218289B2 (en) 2015-12-22
KR101735222B1 (ko) 2017-05-24

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