KR101726258B1 - Auto-suspend and auto-resume operations for a multi-die nand memory device - Google Patents

Abstract

In a multi-die memory, such as a solid state drive, subsequent memory operations may be performed in a high current memory, such as an operation to enable the charge pump of the die, an operation to occupy the bit line of the die, or a program / erase loop operation, A method and apparatus for controlling a peak current condition by determining whether an operation is by at least one die of a multi-die memory. If it is determined that the subsequent memory operation is a high current memory operation, the die enters the interrupt operation mode. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically addressed to the die, and a display from another die indicating that a high current memory operation has been completed. Once operation resumes, the die performs a high current memory operation.

Description

[0001] AUTO-SUSPEND AND AUTO-RESUME OPERATIONS FOR A MULTI-DIE NAND MEMORY DEVICE FOR MULTI-

Embodiments of the techniques described herein relate to multi-chip nonvolatile memories, and more particularly, to NAND flash memories of multi-chip (multi-die) NAND flash memory devices, / RTI >

The peak power consumption per die of a multi-NAND device (multi-die configuration) should be controlled in some manner to meet the overall power consumption constraints for multi-NAND devices. One conventional approach that has been used to reduce the combined peak power consumption of multi-die configurations adversely affects the overall execution durations of some NAND memory operations.

The embodiments disclosed herein are illustrated by way of example, and not of limitation, in the figures of the accompanying drawings in which like reference numerals refer to like elements.
Figure 1 shows a simplified block diagram of a portion of an exemplary embodiment of a NAND flash memory according to the subject matter disclosed herein.
FIG. 2 illustrates another exemplary embodiment of a multi-chip NAND flash memory according to the subject matter disclosed herein.
Figure 3 is a block diagram of a portion of a NAND operation performed by a die of the multi-chip NAND flash memory of Figure 2 that automatically halts operation prior to performing an operation that generates a peak current event, in accordance with the subject matter disclosed herein. Figure 2 shows a flow diagram of an exemplary embodiment.
FIG. 4 illustrates an exemplary timing diagram for the reception of a die specific resume command from a system controller for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein.
FIG. 5 illustrates an exemplary timing diagram for resume events based on a system generated clock for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein.
6 illustrates an exemplary timing diagram for resume events based on a die toggled clock for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein.
FIG. 7 illustrates an exemplary timing diagram of a power management mode for an exemplary four-die multi-chip NAND flash memory according to the subject matter disclosed herein.
FIG. 8 illustrates an exemplary timing diagram of an auto-suspend and auto-resume mode for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein.
FIG. 9 illustrates an exemplary timing diagram of a resume operation command for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein.
It will be appreciated that for simplicity and / or clarity of illustration, the components shown in the figures are not necessarily drawn to scale. For example, the dimensions of some components may be exaggerated relative to other components for clarity. The scale of the drawings does not represent exact dimensions and / or dimensional ratios of the various components shown herein. Also, to show corresponding and / or similar elements, where considered appropriate, reference numerals have been repeated among the figures.

BACKGROUND OF THE INVENTION [0002] Embodiments of the techniques described herein relate to semiconductor fabrication, and more particularly, to fabricating vertical NAND strings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, those skilled in the relevant art will recognize that the embodiments described herein may be practiced without one or more of these specific details, or with other methods, components, materials, or the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification.

Reference throughout this specification to "one embodiment" or "one embodiment " means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, the term "exemplary " is used herein to mean" serving as an example, instance, or illustration. &Quot; Any embodiment described herein as "exemplary " is not necessarily to be construed as preferred or advantageous over other embodiments.

The various operations can be described in a manner that is most helpful in understanding the understanding of the claimed subject matter in turn as a number of discrete operations. However, the order of description is not to be construed as implying that such operations are necessarily order dependent. In particular, these operations need not be performed in the order presented. The described operations may be performed in a different order than the described embodiment. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

According to embodiments of the subject matter described herein, the power dissipation peaks of a multi-NAND device (multi-die configuration) that arise during simultaneous operations of a multi-NAND die may be determined by automatically It is controlled and managed by stopping. Each NAND die is then controlled to resume operation based on the determined system conditions to temporarily change the current / power peaks of the individual die without adversely affecting the overall execution durations of some NAND memory operations.

FIG. 1 illustrates a simplified block diagram of a portion of an exemplary embodiment of a NAND flash memory 100 according to the subject matter disclosed herein. In one exemplary embodiment, the NAND flash memory 100 includes, but is not limited to, a portion of a multi-die configuration, such as a solid-state memory array or a solid-state drive. NAND flash memory 100 has been simplified in FIG. 1 to focus on memory features that help to understand the subject matter described herein. It should be understood that a more detailed understanding of the internal circuitry and functions of flash memories is known to those skilled in the art.

The memory 100 includes a memory array 102 that includes a plurality of memory cells arranged in rows and columns. In one exemplary embodiment, each memory cell includes a floating-gate (FG) field effect transistor capable of holding charge for nonvolatile storage of data. In another exemplary embodiment, each memory cell includes a Charge Flash Trap (CFT) device structure. Each cell can be individually electrically programmed by occupying the floating gate. The rows of the memory array 102 are arranged in blocks where one memory block is a part of the discrete portion of the memory array 102. [ The memory cells can generally be erased from the blocks. However, the data may be stored in the memory array 102 in finer increments than the memory block. The row decoder and column decoder circuits 130 and 134 decode memory addresses to access corresponding memory locations in the memory array 102. In one exemplary embodiment, the data register 140 and the optional cache register 142 temporarily store data to be read from or written to the memory array 102.

Command, data and address signals are provided to the I / O control 114 on the device bus 116, which is multiplexed to receive the various signals. Any specific signal among the various signals to be received is determined by the control signals 118 provided to the control logic 128. [ In response to control signals 118 indicating that command signals are being provided to the I / O control 114 on the device bus 116, the command signals are received by the I / O control 114, And is latched by the command register 120. The latched command is provided to control logic 128 via internal command bus 122. The control logic 128 decodes the commands and corresponding internal control signals that perform the requested commands are generated by the control logic 128. In response to control signals 118 indicating that address signals are being provided to the I / O control 114 on the device bus 116, address signals are received and the corresponding addresses are latched into the address register 112. The status register 126 is used to latch the status information provided from the control logic 128 via the internal status bus 127 to the control register. This state information is generated by the control logic 128 in response to receiving a command requesting the state of operation. In one exemplary embodiment, control logic 128 may include an internal oscillator (not shown) that generates an internal clock for synchronizing internal operations of NAND flash memory 100 in response to receiving the command have.

In one exemplary embodiment, the control logic 128 is coupled to a transistor 132 that provides an R / B # (Ready / Busy signal) that can be used to indicate completion of various memory operations, where "#" Corresponds to die identification. The R / B # signal is normally HIGH and transitions to LOW after the command is written to the NAND flash memory 100. [ When the current memory operation is completed, the R / B # signal transitions back to HIGH.

Timer 146, coupled to control logic 128, may be used to timing the time delay. As will be described in more detail below, the timer 146 selectively delays the resume operation by the individual NAND flash memories of the multi-chip NAND flash memory to avoid all of the NAND flash memories starting to commence the resume operation at the same time . Timer 146 may be implemented using conventional circuits and designs that are conventional. The control logic 128 is also coupled to the Multi-Die Enable (MDE) logic 150. The MDE logic receives an MDE signal used to identify a particular NAND flash memory 100 for multi-chip applications. For example, in a multi-chip application with four NAND flash memories, the input to the MDE logic 150 for one of the memories may be connected to the power supply VCC and the input to the MDE logic 150 for the other memories Can be connected to ground VSS. Based on the signal applied to the MDE logic 150, the control logic 128 is provided with identification information for the NAND flash memory. In configurations in which a greater number of NAND flash memories are used, the MDE logic 150 may be modified to receive more signals such that each of the memories can be uniquely identified, as is known in the art.

The latches 148 connected to the control logic 128 are used to store various information regarding the state of the NAND flash memory 100. [ Each latch included in the latches 148 may be set to the first state or the second state by the control logic 128. Based on the state of the latch, the control logic 128 sets the mode of operation of the memory (e.g., to a first state indicating operation of the first mode and to a second state indicating operation of the second mode) (E.g., set to a first state for initial power-up of memory 100 and set to a second state after an event has occurred). Latches 148 are conventional and can be designed and operated as is well known to those skilled in the art.

In operation, the memory array 102 may be accessed by providing a combination of control, command, and address signals. For example, to perform a read operation, the control logic 128 is provided with a first set of control signals 118 indicating that command signals are applied to the device bus 116. The control logic 128 generates internal control signals in which the I / O control 114 receives the command signals and the corresponding command is latched into the command register 128. The control logic 128 decodes the read command and begins generating internal control signals for accessing the memory array 102.

A second combination of control signals 118 is provided to the control logic 128 indicating that address signals are applied to the device bus 116. The control logic generates internal control signals in which the I / O control 114 receives the address signals and the corresponding addresses are latched into the address register 112. The addresses are provided to the row decoder circuit 130 and the column decoder circuit 134 via the internal address bus 124 to decode the addresses and access the memory locations corresponding to the latched addresses.

A page of memory cells having memory locations to be accessed is read from the memory array 102 and stored in the data register 140. Data from a page of memory is passed to a secondary (and optional) cache register 142 before being provided to the I / O control 114 on the internal data bus 144. The cache register may be used to temporarily store a page of data to empty the data register 140 to store another page of data for subsequent access operations of the memory array 102. [ A page of data is passed from the cache register 142 to the I / O control 114. Based on the addresses, appropriate data is output on the device bus 116 from the page of data.

A third combination of control signals is provided to the control logic 128 indicating that data to be written to the memory locations corresponding to the addresses is being provided on the device bus 116 following the second combination of control signals Except for the point, the write operation occurs in a similar manner. Data received by the I / O control 114 is provided to the cache register 142 for writing to the memory array 102 on the internal data bus 144.

FIG. 2 illustrates another exemplary embodiment of a multi-chip NAND flash memory 200 according to the subject matter disclosed herein. In one exemplary embodiment, the NAND flash memory 200 includes, but is not limited to, a portion of a multi-die configuration, such as a solid-state memory array or a solid-state drive. The multi-chip memory 200 includes N individual NAND flash memories 202-208 sharing a control bus 220 and an I / O (Input / Output) The NAND flash memories 202-208 are typically included in a single device package that provides a high density, low form factor, multi-chip memory.

In one exemplary embodiment, each of the NAND flash memories 202-208 has a separate MDE logic 150 that is programmed as before or electrically connected to have unique identification information. In alternate embodiments, the non-volatile chip identification latches included in the latches 148 are programmed with identification information. As shown in FIG. 2, the first NAND flash memory 202 is identified as die 0 (chip 0), and the second NAND flash memory 204 is identified as die 1 (chip 1). The remaining NAND flash memories are identified by an increasing chip number so that the last two devices 206 and 208 are identified as die N-1 and die N (chip N-1 and chip N), respectively.

An external memory controller (not shown) provides combinations of control signals over the control bus 220 and provides commands, address and data signals over the I / O bus 230 to perform various memory operations do. The control bus 220 includes signal lines for providing various control signals to each device. Examples of control signals are CE #, CLE, ALE, WE #, RE # and WP #, where "#" in various control signals corresponds to a specific die identification. It should be understood that other control signals may also be used. 2, the NAND flash memories 202-208 on the MDE terminals 240, 242, 244 and 246, respectively, are used to set identification information for each of the individual NAND flash memories 202-208. -208) are provided with respective MDE signals. The I / O bus 230 includes multiple signal lines and is shown as an 8-bit wide bus I / O [7: 0]. I / O buses of different pit widths can of course be used alternatively.

In operation, control, command, address, and data signals are provided to both the NAND flash memories 202-208 on the control and I / O busses 220,230. However, only memories activated by the individual CE # signals will receive and respond to signals.

In one exemplary embodiment, a global memory (not shown) may be accessed from the memory controller by activating both the NAND flash memories 202-208 and providing appropriate control and command signals on the control and I / O buses 220,230. A command can be issued. Each of the NAND flash memories 202-208 begins executing memory commands in response to a memory command, which includes two important peak power requirements for a power source (not shown) connected to the multi-die NAND memory 200 . This situation is particularly undesirable in applications where power is supplied by a battery or other limited power source. Since the NAND die operation may be synchronous (i.e., driven by the internal oscillator of the die), events such as current peaks may occur during simultaneous operations on multiple NAND dies. In one exemplary embodiment, each die automatically stops operations prior to performing an operation that generates a peak current event. For example, each die may be automatically activated prior to the operation of enabling the charge pumps of the die, the bit line pre-charge operation, or the program / erase loop operation, But is not limited thereto.

Figure 3 illustrates a portion of a NAND operation performed by a die of a multi-chip NAND flash memory 200 that automatically stops operation prior to performing an operation that generates a peak current event, according to the subject matter disclosed herein A flowchart 300 of an exemplary embodiment is shown. Although three specific peak current events are identified in FIG. 3, it should be understood that the subject matter disclosed herein is not limited thereto, and additional and / or other peak current events may be included in FIG. At 301, the die is performing NAND operations. At 302, it is determined whether an operation to enable the charge pumps of the die should be performed. At 302, if it is determined that an operation to enable charge pumps is to be performed, the flow proceeds to 303 where operation is automatically stopped until a resume operation command is received or a resume operation event occurs.

At 302, if it is determined that an operation to enable charge pumps should not be performed, flow proceeds to 304 where it is determined whether a precharge operation is to be performed on a bit line (BL). At 304, if it is determined that an operation to precharge the bit line should be performed, the flow proceeds to 305 where operation is automatically stopped until a resume operation command is received or a resume operation event occurs.

At 304, if it is determined that the operation of precharging the bit line should not be performed, the flow proceeds to 306 to determine whether an operation that is a program / erase loop operation should be performed. At 306, if it is determined that a program / erase operation should be performed, the flow proceeds to 307 where operation is automatically aborted until a resume operation command is received or a resume operation event occurs.

At 306, if it is determined that a program / erase loop operation should not be performed, the flow proceeds to 308 where NAND operations continue to be performed.

According to the subject matter disclosed herein, exemplary methods in which a resume operation may occur include receiving a die specific resume command from a system controller, initiating a resume operation event based on a system timer / clock and / or an internal die timer / Receiving a systemwide power management command issued to all die and die specific outputs controlling the resume operation on the other die and receiving a die specific resume command from the system controller in response to the indicated high current state of the register on the die Reception, but is not limited thereto.

FIG. 4 illustrates an exemplary timing diagram 400 for the reception of a die specific resume command from a system controller (host controller) for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein. It should be appreciated that a multi-chip NAND flash memory having a different number of dies than the four dice may be used. As shown in Figure 4, die 0-die 3 may be configured to perform operations corresponding to the flowchart of Figure 3 indicating, for example, that a BL (Bit Line) precharge operation should occur, for example, It is in an automatic stop state based on. The die currents (Icc-die 0 to Icc-die 3) are shown in Figure 4 as being in a low current state.

At 401, the system controller issues a resume command on data lines DQ [7: 0] specifically addressed to die 0. In response, die 0 resumes operation at 402 and occurs as the high current condition resulting from bit line precharge is represented by a triangular spike. Later, the system controller issues a resume command on data lines DQ [7: 0], specifically addressed to die 1 at 403. In response, die 1 resumes operation at 404 and a high current condition resulting from bit line precharge occurs. Later, the system controller (host controller) issues a resume command on data lines DQ [7: 0] addressed specifically to die 2 at 405. In response, die 2 resumes operation at 406 and a high current condition resulting from bit line precharge occurs. To complete the description, much later, the system controller issues a resume command on data lines DQ [7: 0], specifically addressed to die 3 at 407. In response, die 3 resumes operation at 408 and a high current condition resulting from bit line precharge occurs. Resume commands are issued by the system controller at appropriate times to avoid high current conditions exceeding the total power consumption constraints for the multi-die device.

FIG. 5 illustrates an exemplary timing diagram 500 for resume events based on a system generated clock for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein. It should be appreciated that a multi-chip NAND flash memory having a different number of dies than the four dice may be used. 5, the die 0-die 3 may be configured to perform operations corresponding to the flowchart of FIG. 3, for example, indicating that a BL (Bit Line) precharge operation should occur, for example, It is in an automatic stop state based on. The die currents (Icc-Die 0 to Icc-Die 3) are shown in Figure 5 as being in a low current state.

At 501, a counter reset Cntr_reset signal is issued by the system controller, which causes all of the internal die counters of the individual dies to reset from 502 to 00h. Each internal die counter is individually trimmed to reset to a different timing value during manufacture. Each internal die counter also responds to counting in a manner well known to the system generated power management signal PM_clk. In one exemplary embodiment, the Cntr_reset signal should be issued in an appropriate timing relationship with the power management signal PM_clk. When the internal die counter for die 0 is 01h for this example, die 0 resumes operation at 503 and a high current condition resulting from bit line precharge occurs. When the internal die counter for die 1 is 02h, die 1 resumes operation at 504 and a high current condition resulting from bit line precharge occurs. When the internal die counter for die 2 is 03h, die 1 resumes operation at 505, and a high current condition resulting from bit line precharge occurs, and when the internal die counter for die 3 is 04h, die 3 Lt; / RTI > resumes operation at 506, and a high current condition due to bit line precharge occurs. The rate of PM_clk and the selected counter value of each internal die counter should be selected to provide appropriate timing to avoid high current conditions exceeding the total power consumption constraints for the multi-die device.

FIG. 6 illustrates an exemplary timing diagram 600 for resume events based on a die toggled clock for an exemplary four die multi-chip NAND flash memory according to the subject matter disclosed herein. It should be appreciated that a multi-chip NAND flash memory having a different number of dies than the four dice may be used. As shown in FIG. 6, die 0-die 3 includes, for example, receiving a Cntr_reset signal from a system controller (host controller) and indicating that a BL (Bit Line) For example, it is in an automatic break state based on performing actions corresponding to the flow chart of FIG. The die currents (Icc-die 0 to Icc-die 3) are shown in Figure 6 as being in a low current state.

More specifically, at 601, a counter reset signal CNT_reset is issued by the system controller, which causes all of the internal die counters of the individual dies to reset from 602 to 00h. In one exemplary embodiment, the CNT_reset signal also enables an auto break mode for die 0-die 3. Additionally, each internal die counter is trimmed individually to be reset to a different timing value during manufacture, and each internal die counter responds to counting in a manner well known to the system clock PM_clk. When die 0 enters the auto-suspend state, the system-wide power management signal PM_clk is toggled at 603 and die 0's internal die counter begins counting. Similarly, PM_clk is toggled (events 604, 605, and 606) when die 1-die 3 enters the auto-pause state. While toggling of PM_clk is shown as being periodically spaced in time, it should be appreciated that toggling will be a function when each individual die determines that it should enter an auto-off state. PM_clk continues to toggle, and ultimately the internal die counter of die 0 becomes, in this example, 604 to 04h, and die 0 resumes operation at 607, resulting in a high current condition due to bit line precharge. A high current condition is detected at 608 and causes PM_clk to toggle at 609. When the internal die counter of die 1 becomes 04h at 610, die 1 resumes operation at 611 and a high current condition resulting from bit line precharge occurs. A high current condition is detected at 611 and causes PM_clk to toggle at 612. When the internal die counter of die 2 goes from 613 to 04h, die 1 resumes operation at 614 and a high current condition resulting from bit line precharge occurs. The high current condition is detected at 614 and causes PM_clk to toggle at 615. When the internal die counter of die 3 becomes 04h from 616, die 1 resumes operation at 617 and a high current condition resulting from bit line precharge occurs. A high current condition is detected at 614 and causes PM_clk to toggle at 618. The process continues in the same manner. The toggle rate of PM_clk and the selected count value of each internal die counter should be selected to provide the appropriate timing to avoid high current conditions exceeding the total power consumption constraints for the multi-die device.

FIG. 7 illustrates an exemplary timing diagram 700 of a power management mode for an exemplary four-die multi-chip NAND flash memory according to the subject matter disclosed herein. It should be appreciated that a multi-chip NAND flash memory having a different number of dies than the four dice may be used. As shown in FIG. 7, die 0-die 3 is initially in a normal operating mode (i.e., not automatically interrupted). The die currents (Icc-die 0 to Icc-die 3) are shown in Figure 7 as being in a low current state.

After receiving the power management command at 701, all of the dies each stop any subsequent operation prior to the predefined high current operation 702-705. Although individual dies are shown as sequentially stopping operation, this is not necessarily the case. To resume operations, the system controller issues, at 706, a PM_END command indicating, for example, the end of the power management mode. Upon receipt of the PM_END command, each individual die resumes operation with respect to each other based on a unique delay that can be defined during manufacture at 707-710 by a fixed trimmable delay and / or die address.

FIG. 8 illustrates an exemplary timing diagram 800 of an auto-suspend and auto-resume mode for an exemplary four-die multi-chip NAND flash memory according to the subject matter disclosed herein. It should be appreciated that a multi-chip NAND flash memory having a different number of dies than the four dice may be used. As shown in FIG. 8, die 0-die 3 is initially in a normal operating mode (i.e., not automatically interrupted) until one die, e.g., die 0, determines that high current operation is followed It is working. For this particular example, because die 0 is not in an auto-suspended state, die 0 is pulled to the next high current operation detected at the other die by, for example, pulling HC # signal line low at 801 Lt; / RTI > In one exemplary embodiment, the HC # signal line may be implemented similarly to the R / B # signal line in FIG. When the signal HC # goes low at 801, the other die of the multi-die memory is based on executing the operations corresponding to the flowchart of FIG. 3 indicating that, for example, a BL (bit line) And enters the automatic stop state. The die currents (Icc-die 0 to Icc-die 3) are marked as being in the low current state in FIG.

Die 0 is fabricated to have a zero delay after HC # goes low, and immediately performs the detected subsequent high current operation. When die 0 is finalized with a high current operation, signal HC # is released at 802, causing die 1 to remain in an automatically interrupted state for a delay of delay 1. At the end of delay 1, die 1 automatically resumes and determines that HC # should be pulled low at 803 to indicate that high current operation has been detected to be followed. When die 1 is finalized with a high current operation, signal HC # is released at 804, causing die 2 to remain in an automatically interrupted state for a delay of delay 2. [ At the end of delay 2, die 3 automatically resumes and determines that HC # should be pulled low at 806 to indicate that high current operation has been detected to be followed. When die 3 is finished in high current operation, signal HC # is released at 807. The process continues in the same manner.

FIG. 9 illustrates an exemplary timing diagram 900 of a resume operation command for an exemplary four-die multi-chip NAND flash memory according to the subject matter disclosed herein. It should be appreciated that a multi-chip NAND flash memory having a different number of dies than the four dice may be used. As shown in Figure 9, die 0-die 3 includes an auto-stop state based on executing operations corresponding to the flow chart of Figure 3 indicating, for example, that a BL (bit line) . The die currents (Icc-die 0 to Icc-die 3) are shown in Figure 9 as being in a low current state. Additionally, each die includes a high current resistor that stores an indicator of whether the die is in an automatic break mode. Each high current resistor can be read in a well known manner by a system controller (host controller). Based on the status displayed in the high current registers of the individual die, the system controller can determine the appropriate time to issue the resume command to the die.

As shown in FIG. 9, the system controller reads the state of the high current register of die 0 at 901 and issues a resume command at 902. In response to the resume command, die 0 resumes operation at 903, and a high current condition resulting from bit line precharge occurs. The decision to issue a resume command by the system controller at 902 is based on the overall peak current conditions of the multi-die memory, but is not limited thereto. At 904, the system controller reads the state of the high current register of die 1 and issues a resume command at 905. In response to the resume command, die 1 resumes operation at 906 and a high current condition resulting from bit line precharge occurs. At 907, the system controller reads the state of the high current register of die 2 and issues a resume command at 908. In response to the resume command, die 2 resumes operation at 909, and a high current condition resulting from bit line precharge occurs. At 910, the system controller reads the state of the high current register of die 3 and issues a resume command at 911. In response to the resume command, die 3 resumes operation at 912 and a high current condition resulting from bit line precharge occurs. Similar to the determination made to issue the resume command by the system controller at 902, the decisions made for the resume command issued at 905, 908, and 911 are based on the overall peak current conditions of the multi-die memory, but are not limited thereto . For example, based on executing the operations corresponding to the flowchart of FIG. 3, each individual die enters an auto-suspend state and the process continues to monitor the state of the individual high-current registers.

These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed as limiting the scope of the specific embodiments disclosed herein and in the claims. Rather, the scope of the embodiments disclosed herein should be determined by the following claims, which should be understood in accordance with established policies of claim interpretation.

Claims (27)

As a method,
Determining whether a subsequent memory operation is a high current memory operation by at least one die of the multi-die memory;
Entering the shutdown mode of operation by the at least one die if the subsequent memory operation is a high current memory operation;
Resuming operation by the at least one die in response to a resume operation event;
Performing the subsequent memory operation;
Receiving a counter reset signal from a controller of the multi-die memory;
Resetting the internal die counter in response to the counter reset signal;
Counting a first clock signal using the internal die counter;
Resuming the operation by the at least one die in response to a predetermined count by the internal die counter, the predetermined count of the internal die counter including the resume operation event;
Performing the subsequent memory operation;
Receiving a command from a controller of the multi-die memory to enter a mode for determining whether the subsequent memory operation is a high current memory operation;
Performing, by the at least one die of multi-die memory, the step of determining whether the subsequent memory operation is a high current memory operation in response to receiving the command;
Receiving a resume command addressed specifically to the at least one die from the controller, the resume command including the resume operation event;
Performing said resume operation by said at least one die in response to said resume command, said resume command being specifically addressed to said at least one die; And
Performing the subsequent memory operation
≪ / RTI > The method according to claim 1,
Wherein determining by the at least one die that the subsequent memory operation is a high current memory operation is characterized in that the subsequent memory operation comprises an operation of enabling a charge pump of the at least one die, A line-occupying operation, a program / erase loop operation, or a combination thereof. The method according to claim 1,
Wherein the step of determining by the at least one die that the subsequent memory operation is a high current memory operation further comprises outputting an indication of the subsequent memory operation to the multi-die memory. delete delete delete The method according to claim 1,
Wherein performing the subsequent memory operation by the at least one die includes delaying a predetermined period of time after receiving the second indication prior to performing the subsequent memory operation. delete The method according to claim 1,
Receiving a command from a controller of the multi-die memory to enter a mode for determining whether the subsequent memory operation is a high current memory operation;
Toggling the signal line in response to determining by the at least one die that the subsequent memory operation is a high current memory operation;
Performing said resume operation by said at least one die in response to a predetermined number of times said signal line is toggled, wherein said predetermined number of times said signal line is toggled comprises said resume operation event;
Performing the subsequent memory operation; And
Toggling the signal line in response to performing the subsequent memory operation
≪ / RTI > The method according to claim 1,
Wherein the multi-die memory comprises a solid state drive. A method of controlling peak current conditions in a solid state drive,
Determining whether a subsequent memory operation is a high current memory operation by at least one die of the solid state drive, the high current memory operation comprising: enabling a charge pump of the at least one die; An operation that occupies the bit line of the die, or a program / erase loop operation, or a combination thereof;
Entering the shutdown mode of operation by the at least one die if the subsequent memory operation is a high current memory operation;
Resuming operation by the at least one die in response to a resume operation event;
Performing the subsequent memory operation;
Receiving a counter reset signal from a controller of the solid state drive;
Resetting the internal die counter in response to the counter reset signal;
Counting a first clock signal using the internal die counter;
Resuming the operation by the at least one die in response to a predetermined count by the internal die counter, the predetermined count of the internal die counter including the resume operation event;
Performing the subsequent memory operation;
Receiving a command from the controller of the solid state drive to determine whether the subsequent memory operation is a high current memory operation;
Responsive to receiving the command, determining by the at least one die of multi-die memory that the subsequent memory operation is a high current memory operation;
Receiving a resume command addressed specifically to the at least one die from the controller of the solid state drive, the resume command including the resume operation event;
Performing said resume operation by said at least one die in response to said resume command, said resume command being specifically addressed to said at least one die; And
Performing the subsequent memory operation
≪ / RTI > delete delete delete 12. The method of claim 11,
Wherein the step of determining by the at least one die that the subsequent memory operation is a high current memory operation further comprises outputting an indication of the subsequent memory operation to the multi-die memory. delete 12. The method of claim 11,
Receiving a command from a controller of the solid state drive to enter a mode for determining whether the subsequent memory operation is a high current memory operation;
Toggling the signal line in response to determining by the at least one die that the subsequent memory operation is a high current memory operation;
Performing said resume operation by said at least one die in response to a predetermined number of times said signal line is toggled, wherein said predetermined number of times said signal line is toggled comprises said resume operation event;
Performing the subsequent memory operation; And
Toggling the signal line in response to performing the subsequent memory operation
≪ / RTI > delete delete delete An apparatus for controlling a peak current condition in a solid state drive,
Means for determining whether a subsequent memory operation is a high current memory operation by at least one die of the solid state drive, the high current memory operation comprising: enabling a charge pump of the at least one die; An operation that occupies the bit line of the die, or a program / erase loop operation, or a combination thereof;
Means for entering the shutdown mode by the at least one die if the subsequent memory operation is a high current memory operation;
Means for resuming operation by the at least one die in response to a resume operation event;
Means for performing the subsequent memory operation;
Means for receiving a counter reset signal from a controller of the solid state drive;
Means for resetting an internal die counter in response to a counter reset signal;
Means for counting a first clock signal using the internal die counter;
Means for resuming the operation by the at least one die in response to a predetermined count by the internal die counter, the predetermined count of the internal die counter including the resume operation event;
Means for performing the subsequent memory operation;
Means for receiving a command from the controller of the solid state drive to determine whether the subsequent memory operation is a high current memory operation;
Means responsive to receiving the command determining whether the subsequent memory operation is a high current memory operation by the at least one die of the multi-die memory;
Means for receiving a resume command addressed specifically to the at least one die from the controller of the solid state drive, the resume command including the resume operation event;
Means responsive to the resume command for performing the resume operation by the at least one die in response to the resume command being specifically addressed to the at least one die; And
Means for performing the subsequent memory operation
/ RTI > delete delete delete 22. The method of claim 21,
Wherein the means for determining by the at least one die that the subsequent memory operation is a high current memory operation further comprises means for outputting an indication of the subsequent memory operation to the multi-die memory. delete 22. The method of claim 21,
Means for receiving a command from a controller of the solid state drive to enter a mode for determining whether the subsequent memory operation is a high current memory operation;
Means for toggling the signal line in response to determining by the at least one die that the subsequent memory operation is a high current memory operation;
Means for performing said resume operation by said at least one die in response to a predetermined number of times said signal line is toggled, wherein said predetermined number of times said signal line is toggled comprises said resume operation event;
Means for performing the subsequent memory operation; And
Means for toggling said signal line in response to performing said subsequent memory operation
Lt; / RTI >

Images