KR101725152B1 - Manufacturing Method Of Metal line of Semiconductor Device - Google Patents

Manufacturing Method Of Metal line of Semiconductor Device Download PDF

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KR101725152B1
KR101725152B1 KR1020100112272A KR20100112272A KR101725152B1 KR 101725152 B1 KR101725152 B1 KR 101725152B1 KR 1020100112272 A KR1020100112272 A KR 1020100112272A KR 20100112272 A KR20100112272 A KR 20100112272A KR 101725152 B1 KR101725152 B1 KR 101725152B1
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layer
etching
forming
amorphous carbon
titanium nitride
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KR20120050827A (en
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신수범
문준영
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에스케이하이닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations

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Abstract

본 발명에 의한 반도체 소자의 금속 배선 형성 방법은 금속층을 형성하는 단계, 상기 금속층 위에 티타늄나이트라이드(TiN)층이 최상부에 배치되는 접착층을 형성하는 단계, 상기 티타늄나이트라이드층에 대해 질소 플라즈마 처리를 수행하여 상기 티타늄나이트라이드층 표면에서의 나이트로젠(N) 농도를 증가시키는 단계, 상기 질소 플라즈마로 처리된 티타늄나이트라이드층의 상부에 접촉하여 비정질 탄소(Amorphous Carbon)로 이루어진 하드마스크층 패턴을 형성하는 단계, 및 상기 하드마스크층 패턴을 식각마스크로 한 식각으로 상기 접착층 및 금속층을 식각하는 단계를 포함한다.A method of forming a metal line of a semiconductor device according to the present invention includes the steps of forming a metal layer, forming an adhesive layer on the top of the metal layer, the titanium nitride layer being disposed on the top of the metal layer, (N) concentration on the surface of the titanium nitride layer; forming a hard mask layer pattern made of amorphous carbon by contacting the top of the titanium nitride layer treated with the nitrogen plasma; And etching the adhesive layer and the metal layer by etching using the hard mask layer pattern as an etching mask.

Description

반도체 소자의 금속 배선 형성 방법{Manufacturing Method Of Metal line of Semiconductor Device}[0001] METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR DEVICE [0002]

본 발명은 반도체 소자의 형성 방법에 관한 것이다. 보다 상세하게는 반도체 소자의 금속 배선의 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device. And more particularly, to a method of forming a metal wiring of a semiconductor device.

일반적으로 반도체 소자에는 소자와 소자 사이 또는 배선과 배선 사이를 전기적으로 연결하기 위해 금속배선이 형성된다. 반도체 소자의 고집적화 추세에 의한 디자인 룰(Design Rule) 감소에 따라 배선이 차지하는 하부면적을 줄이면서 동시에 높이를 크게 형성할 수밖에 없어 금속배선을 형성하는 공정의 난이도와 중요성이 증가되는 추세이다. 이러한 금속배선의 재료로는 전기전도도가 우수한 알루미늄(Al) 및 구리(Cu)가 주로 이용된다. In general, a metal wiring is formed in a semiconductor device to electrically connect the element and the element or between the wiring and the wiring. As the design rule is reduced due to the high integration of semiconductor devices, the bottom area occupied by the wirings is reduced, and at the same time, the height is increased. Therefore, the difficulty and importance of the process of forming the metal wirings are increasing. Aluminum (Al) and copper (Cu), which have excellent electrical conductivity, are mainly used as the material of the metal wiring.

금속배선을 형성하는 과정에서 금속배선의 프로파일을 형성하고 잔류금속층을 제거하여 식각잔류 금속층에 의한 금속배선의 하부 브릿지의 발생을 억제하기 위하여는 금속층을 충분히 과도 식각(over-etch)하는 것이 필요하다. 그러나, 금속층의 상부를 노출시킨 상태에서 금속층을 과도 식각하는 경우에는 형성된 금속 배선에 상부어택(top attack)이 발생하여 금속 배선 프로파일의 열화를 가져오게 된다. 따라서 상부어택의 발생을 억제하고 충분한 과도식각을 하기 위하여 비정질 탄소(amorphous carbon)을 이용한 하드 마스크층을 형성한 후, 이를 패터닝한 비정질 탄소 하드마스크 패턴을 식각마스크로 이용하여 금속배선을 형성하였다. 그러나, 비정질 탄소 하드마스크는 그 하부의 티타늄나이트라이드층(TiN)을 최상층으로 하는 접착층과 접착성(adhesivity)이 좋지 않아 비정질 탄소 하드마스크가 들뜨는 리트팅(lifting)현상이 빈번하게 발생하였다. 리프팅 현상의 발생을 억제하기 위하여 흡착층으로 실리콘옥시나이트라이드(SiON)층을 비정질 탄소 하드마스크 층과 접착층의 사이에 형성하였다.It is necessary to sufficiently overetch the metal layer in order to form the profile of the metal wiring and to remove the residual metal layer to suppress generation of the lower bridge of the metal wiring by the etching residual metal layer . However, when the metal layer is excessively etched in the state that the upper part of the metal layer is exposed, a top attack occurs in the formed metal wiring, thereby deteriorating the metal wiring profile. Thus, a hard mask layer using amorphous carbon was formed to suppress the occurrence of upper attack and sufficient transient etching, and a metal interconnection was formed using the patterned amorphous carbon hard mask pattern as an etching mask. However, since the amorphous carbon hard mask has poor adhesiveness with the adhesive layer having the titanium nitride layer (TiN) as the uppermost layer, the amorphous carbon hard mask frequently experiences lifting due to the amorphous carbon hard mask. A silicon oxynitride (SiON) layer was formed as an adsorption layer between the amorphous carbon hard mask layer and the adhesive layer to suppress the lifting phenomenon.

그러나, 금속배선을 형성하기 위하여 클로린(Cl), 플로린(F) 등의 기체를 이용하여 실리콘옥시나이트라이드층을 화학적으로 식각하는 과정에서 폴리머(polymer)가 발생하며, 이러한 폴리머에 의하여 브릿지가 형성되어 금속배선 사이의 절연이 파괴되는 문제가 있었다. 또한, 접착층이 식각되기 이전에 하드마스크 흡착층의 화학적 식각에 의하여 프로파일의 불량이 발생하며 결국 전체 금속 배선 프로파일의 불량을 가져오는 문제점이 있었으며, 리프팅 문제 해소를 위한 하드마스크 흡착층의 추가에 따라 금속배선 식각시 공정시간이 증가하여 경제적인 면에서도 불리한 점이 있었다.However, in order to form a metal wiring, a polymer is generated in a process of chemically etching the silicon oxynitride layer using a gas such as chlorine (Cl) or fluorine (F), and a bridge is formed So that there is a problem that the insulation between metal wires is destroyed. Further, before the adhesive layer is etched, the profile of the hard mask is deteriorated due to the chemical etching of the adsorption layer, resulting in a failure of the entire metal wiring profile. In addition, due to the addition of the hard mask adsorption layer for solving the lifting problem The etching time of the metal wiring is increased, which is disadvantageous in terms of economy.

본 발명은 흡착층으로서의 실리콘옥시나이트라이드층의 사용을 배제하여 종래 기술의 문제점인 폴리머에 의한 브릿지 형성, 금속 배선 프로파일의 불량 및 공정시간의 증가를 막고자 하는데 주된 목적이 있다.The main object of the present invention is to prevent the formation of bridges by polymer, defective metal wiring profile, and increase of process time, which is a problem in the prior art by excluding the use of a silicon oxynitride layer as an adsorption layer.

본 발명에 의한 반도체 소자의 금속 배선 형성 방법은 금속층을 형성하는 단계, 상기 금속층 위에 티타늄나이트라이드(TiN)층이 최상부에 배치되는 접착층을 형성하는 단계, 상기 티타늄나이트라이드층에 대해 질소 플라즈마 처리를 수행하여 상기 티타늄나이트라이드층 표면에서의 나이트로젠(N) 농도를 증가시키는 단계, 상기 질소 플라즈마로 처리된 티타늄나이트라이드층의 상부에 접촉하여 비정질 탄소(Amorphous Carbon)로 이루어진 하드마스크층 패턴을 형성하는 단계, 및 상기 하드마스크층 패턴을 식각마스크로 한 식각으로 상기 접착층 및 금속층을 식각하는 단계를 포함한다.A method of forming a metal line of a semiconductor device according to the present invention includes the steps of forming a metal layer, forming an adhesive layer on the top of the metal layer, the titanium nitride layer being disposed on the top of the metal layer, (N) concentration on the surface of the titanium nitride layer; forming a hard mask layer pattern made of amorphous carbon by contacting the top of the titanium nitride layer treated with the nitrogen plasma; And etching the adhesive layer and the metal layer by etching using the hard mask layer pattern as an etching mask.

일 예에서, 상기 식각은 아르곤(Ar)을 이용한 플라즈마 식각공정으로 수행한다.In one example, the etching is performed by a plasma etching process using argon (Ar).

일 예에서, 상기 플라즈마 식각공정은 아르곤(Ar)의 유량은 50 내지 200sccm, 압력은 5 내지 50 mT 및 전력은 300 내지 500W의 조건으로 수행한다.In one example, the plasma etching process is performed under conditions of a flow rate of argon (Ar) of 50 to 200 sccm, a pressure of 5 to 50 mT and a power of 300 to 500 W.

일 예에서, 상기 티타늄나이트라이드층에 대하여 질소 플라즈마 처리를 수행하는 단계 이전에 상기 티타늄나이트라이드층 표면의 수분을 제거하는 단계를 더 포함한다.In one example, the method further comprises removing moisture from the surface of the titanium nitride layer prior to performing the nitrogen plasma treatment on the titanium nitride layer.

일 예에서, 상기 비정질 탄소막 내지 상기 금속층을 물리적 식각하는 단계 이전에 상기 비정질 탄소막의 상부에 실리콘옥시나이트라이드(SiON)층과 감광막을 형성하여 리소그래피(lithography) 공정을 수행하는 단계를 더 포함한다.In one embodiment, the method further comprises performing a lithography process by forming a photoresist layer on the amorphous carbon film and a silicon oxynitride (SiON) layer prior to the step of physically etching the amorphous carbon film to the metal layer.

본 발명은 실리콘옥시나이트라이드층의 형성을 배제하여 폴리머에 의한 브릿지 형성을 막을 수 있으며, 양호한 금속 배선 프로파일을 제공하고 나아가 공정시간을 감소시킬 수 있다.The present invention excludes the formation of a silicon oxynitride layer to prevent the formation of bridges by the polymer, provides a good metallization profile and further reduces the processing time.

도 1 내지 도 5는 본 발명에 의한 반도체 소자의 금속 배선 형성 방법을 설명하기 위하여 나타내 보인 단면도들이다.1 to 5 are sectional views for explaining a method of forming a metal wiring of a semiconductor device according to the present invention.

도 1을 참조하면, 반도체 기판 위에 형성된 층간절연막(100)에 제1 접착층(first adhesive layer, 110)을 형성한다. 제1 접착층(110)은 그 상부에 형성될 층과 아래에 위치하는 층과의 접착성(adhesivity)을 향상시키는 기능을 가지며, 단일층으로 형성하거나 또는 서로 다른 두 층을 적층하여 형성할 수 있다. 일 예에서, 제1 접착층(110)은 대략 100Å의 두께를 가지는 티타늄(Ti)층과 대략 100Å의 두께를 가지는 티타늄나이트라이드(TiN)층을 적층하여 형성한다. 제1 접착층(110)의 상부에 금속층(120)을 형성한다. 금속층(120)은 식각되어 금속배선으로 형성되므로, 전기전도도가 높은 물질로 형성한다. 일 예에서, 금속층(120)은 대략 6000 내지 8000Å의 두께를 가지는 알루미늄(Al)층으로 형성한다. 금속층(120)의 상부에 제2 접착층(130)을 형성한다. 제2 접착층(130)은 그 상부의 층과 하부층 사이의 접착성을 향상시키는 기능을 수행하며, 단일층으로 형성하거나 또는 서로 다른 두 층을 적층하여 형성할 수 있다. 제2 접착층(130)의 최상부는 티타늄나이트라이드(TiN)로 형성한다. 일 예에서, 제2 접착층(130)은 대략 100Å의 두께를 가지는 티타늄층과 대략 700 내지 1000Å의 두께를 가지는 티타늄나이트라이드(TiN)층을 적층하여 형성한다. 이는 제2 접착층(130) 하단의 금속층(120)과 제2 접착층(130) 상단에 형성될 비정질 탄소(Amorphous Carbon) 하드마스크층과의 접착성을 향상시키기 위해서이다.Referring to FIG. 1, a first adhesive layer 110 is formed on an interlayer insulating layer 100 formed on a semiconductor substrate. The first adhesive layer 110 has a function of improving adhesiveness between a layer to be formed on the first adhesive layer and a layer on the lower layer and may be formed as a single layer or may be formed by laminating two different layers . In one example, the first adhesive layer 110 is formed by laminating a titanium (Ti) layer having a thickness of about 100 angstroms and a titanium nitride (TiN) layer having a thickness of about 100 angstroms. A metal layer 120 is formed on the first adhesive layer 110. Since the metal layer 120 is etched and formed of metal wiring, it is formed of a material having high electrical conductivity. In one example, the metal layer 120 is formed of an aluminum (Al) layer having a thickness of approximately 6000 to 8000 ANGSTROM. A second adhesive layer 130 is formed on the metal layer 120. The second adhesive layer 130 functions to improve the adhesiveness between the upper layer and the lower layer, and may be formed as a single layer or by laminating two different layers. The uppermost portion of the second adhesive layer 130 is formed of titanium nitride (TiN). In one example, the second adhesive layer 130 is formed by laminating a titanium layer having a thickness of approximately 100 ANGSTROM and a titanium nitride (TiN) layer having a thickness of approximately 700 to 1000 ANGSTROM. This is to improve the adhesion between the metal layer 120 at the lower end of the second adhesive layer 130 and the amorphous carbon hard mask layer to be formed at the upper end of the second adhesive layer 130.

도 2를 참조하면, 제2 접착층(130)의 최상부에 위치하는 티타늄나이트라이드층의 표면을 질소 플라즈마로 처리한다. 질소 플라즈마 처리를 통하여 티타늄나이트라이드층의 표면(132)은 나이트로젠(N) 농도가 증가하여 N rich 필름의 상태로 된다.Referring to FIG. 2, the surface of the titanium nitride layer located at the top of the second adhesive layer 130 is treated with a nitrogen plasma. Through the nitrogen plasma treatment, the surface 132 of the titanium nitride layer increases in the concentration of nitrogen (N) and becomes a state of the N rich film.

도 3을 참조하면, 질소 플라즈마 처리된 제2 접착층(130)의 상부에 비정질 탄소(amorphous carbon) 하드마스크층(140)을 형성한다. 질소 플라즈마로 처리된 제2 접착층(130)의 최상층인 티타늄나이트라이드층의 표면(132) 및 비정질 탄소 하드마스크층(140)의 표면에는 도 4에 도시된 바와 같이 비정질 탄소 하드마스크층의 C와의 반응에 의한 카본-나이트로젠 글루층(C-N glue layer, 142)이 형성되고, 이러한 카본 나이트로젠 글루층(142)에 의하여 비정질 탄소 하드마스크층(140)과 티타늄나이트라이드층 사이의 접착성이 향상된다. 비정질 탄소 하드마스크층(140)은 추후에 형성될 금속배선의 상부어택(top attack)의 발생을 막으며, 충분한 과도식각(over etch)을 가능하게 하여 브릿지의 발생을 억제할 수 있도록 기능한다. 일 예에서, 비정질 탄소 하드마스크층(140)은 2500 내지 3500Å의 두께로 형성된다. 비정질 탄소 하드마스크층(140)의 상부에 실리콘옥시나이트라이드(SiON)층(미도시) 및 감광막(미도시)을 형성하고 리소그래피공정을 통하여 패턴을 형성한 후, 식각공정을 통하여 형성된 패턴을 식각마스크로 식각하여 금속배선을 형성한다. 이 때, 클로린(Cl), 플로린(F) 등의 식각 기체를 사용하는 화학적 식각공정을 이용하지 않고, 물리적 식각공정을 수행하여 금속배선을 형성한다. 이러한 물리적 식각 공정은 아르곤(Ar)을 이용하며, 공급되는 아르곤(Ar)의 유량은 대략 50 내지 200 sccm, 대략 5 내지 50 mT의 압력조건과 대략 300 내지 500 W의 파워 조건으로 수행한다. 도 5에 도시된 바와 같이 금속배선이 형성된 상태를 보면, 층간 절연막(100)의 상부에 제1 접착층 패턴(115), 금속패턴(125), 및 제2 접착층 패턴(135)이 금속배선을 형성하고 있으며, 비정질 탄소 하드마스크층(도 3의 140 참조)이 배선의 형성과정중 식각되어 최상부에 위치한다(145).Referring to FIG. 3, an amorphous carbon hard mask layer 140 is formed on the second adhesive layer 130 subjected to nitrogen plasma treatment. The surface 132 of the titanium nitride layer and the surface of the amorphous carbon hard mask layer 140, which are the uppermost layers of the second adhesive layer 130 treated with the nitrogen plasma, The CNG layer 142 is formed by the reaction and the adhesiveness between the amorphous carbon hard mask layer 140 and the titanium nitride layer is improved by the carbon nitride rubber layer 142 do. The amorphous carbon hardmask layer 140 prevents the occurrence of a top attack of the metal wiring to be formed at a later stage and enables sufficient over etch to suppress the generation of bridges. In one example, the amorphous carbon hardmask layer 140 is formed to a thickness of 2500 to 3500 ANGSTROM. A silicon oxynitride (SiON) layer (not shown) and a photoresist layer (not shown) are formed on the amorphous carbon hard mask layer 140, a pattern is formed through a lithography process, A metal wiring is formed by etching with a mask. At this time, a physical etching process is performed without using a chemical etching process using an etching gas such as chlorine (Cl) or fluorine (F) to form a metal wiring. This physical etching process uses argon (Ar), and the flow rate of argon (Ar) supplied is approximately 50 to 200 sccm, a pressure of approximately 5 to 50 mT and a power condition of approximately 300 to 500 W. 5, the first adhesive layer pattern 115, the metal pattern 125, and the second adhesive layer pattern 135 are formed on the upper surface of the interlayer insulating layer 100 to form metal wirings And an amorphous carbon hardmask layer (see 140 in FIG. 3) is etched (145) at the top during the formation of the wiring.

제2 접착층(130)의 상부에 실리콘옥시나이트라이드층을 형성하지 않으므로 종래 실리콘옥시나이트라이드층의 식각시 발생하던 폴리머가 발생하지 않아 브릿지의 발생을 막을 수 있으며, 물리적 식각공정을 통하여 금속배선을 형성하므로 이방성(anisotropic) 식각이 가능하여 전체 금속배선의 프로파일을 향상시키는 것이 가능하며, 나아가 실리콘 옥시나이트라이드층의 식각과정을 생략할 수 있어 전체적인 공정수를 감소시킬 수 있다.Since the silicon oxynitride layer is not formed on the second adhesive layer 130, the generation of bridges can be prevented because no polymer is generated during the etching of the conventional silicon oxynitride layer, Anisotropic etching can be performed to improve the profile of the entire metal wiring. Further, the etching process of the silicon oxynitride layer can be omitted, thereby reducing the overall process number.

100: 층간절연막 110: 제1 접착층
120: 금속층 130: 제2 접착층
140: 비정질 탄소 하드마스크층 100: interlayer insulating film 110: first adhesive layer
120: metal layer 130: second adhesive layer
140: amorphous carbon hard mask layer

Claims (5)

금속층을 형성하는 단계;
상기 금속층 위에 티타늄나이트라이드(TiN)층이 최상부에 배치되는 접착층을 형성하는 단계;
상기 티타늄나이트라이드층에 대해 질소 플라즈마 처리를 수행하여 상기 티타늄나이트라이드층 표면에서의 나이트로젠(N) 농도를 증가시키는 단계;
상기 질소 플라즈마로 처리된 티타늄나이트라이드층의 상부와 접촉하는 비정질 탄소(Amorphous Carbon) 하드마스크층 패턴을 형성하여 상기 질소 플라즈마로 처리된 티타늄나이트라이드층 표면 및 상기 비정질 탄소 하드마스크층 패턴 표면에 카본-나이트로젠 글루층을 형성하는 단계; 및
상기 비정질 탄소 하드마스크층 패턴을 식각마스크로 한 식각으로 상기 접착층 및 금속층을 식각하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법.Forming a metal layer;
Forming an adhesive layer on top of the metal layer, the titanium nitride layer being disposed on top;
Performing a nitrogen plasma treatment on the titanium nitride layer to increase the concentration of nitrogen (N) on the surface of the titanium nitride layer;
Forming an amorphous carbon hard mask layer pattern in contact with an upper portion of the titanium nitride layer treated with the nitrogen plasma to form a titanium nitride layer surface treated with the nitrogen plasma and a carbon nitride layer on the amorphous carbon hard mask layer pattern surface, - forming a nitroglyglue layer; And
And etching the adhesive layer and the metal layer by etching using the amorphous carbon hard mask layer pattern as an etching mask. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제1항에 있어서,
상기 식각은 아르곤(Ar)을 이용한 플라즈마 식각공정인 반도체 소자의 금속 배선 형성 방법.The method according to claim 1,
Wherein the etching is a plasma etching process using argon (Ar). 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 has been abandoned due to the setting registration fee. 제2항에 있어서,
상기 플라즈마 식각공정은 아르곤(Ar)의 유량은 50 내지 200sccm, 압력은 5 내지 50 mT 및 전력은 300 내지 500W의 조건으로 수행되는 반도체 소자의 금속 배선 형성 방법.3. The method of claim 2,
Wherein the plasma etching process is performed under conditions of a flow rate of argon (Ar) of 50 to 200 sccm, a pressure of 5 to 50 mT and a power of 300 to 500 W. 삭제delete 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 has been abandoned due to the setting registration fee. 제1항에 있어서,
상기 비정질 탄소 하드마스크층 패턴 내지 상기 금속층을 물리적 식각하는 단계 이전에 상기 비정질 탄소 하드마스크층 패턴의 상부에 실리콘옥시나이트라이드(SiON)층과 감광막을 형성하여 리소그래피(lithography) 공정을 수행하는 단계를 더 포함하는 반도체 소자의 금속 배선 형성 방법.
The method according to claim 1,
Forming a photoresist layer on the amorphous carbon hard mask layer pattern and a photoresist layer on the amorphous carbon hardmask layer pattern prior to the step of physically etching the amorphous carbon hardmask layer pattern or the metal layer to perform a lithography process; Thereby forming a metal wiring pattern.
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