KR101719670B1 - Wafer level packaged GaN power device and the manufacturing method thereof - Google Patents

Wafer level packaged GaN power device and the manufacturing method thereof Download PDF

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Publication number
KR101719670B1
KR101719670B1 KR1020100127921A KR20100127921A KR101719670B1 KR 101719670 B1 KR101719670 B1 KR 101719670B1 KR 1020100127921 A KR1020100127921 A KR 1020100127921A KR 20100127921 A KR20100127921 A KR 20100127921A KR 101719670 B1 KR101719670 B1 KR 101719670B1
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South Korea
Prior art keywords
pad
gallium nitride
module substrate
sub
nitride compound
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KR1020100127921A
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Korean (ko)
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KR20120054495A (en
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주철원
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한국전자통신연구원
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Priority to US13/185,780 priority Critical patent/US8519548B2/en
Publication of KR20120054495A publication Critical patent/KR20120054495A/en
Priority to US13/950,368 priority patent/US8691627B2/en
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Publication of KR101719670B1 publication Critical patent/KR101719670B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaN (gallium nitride) compound semiconductor device and a manufacturing method thereof, and more particularly, to a GaN power semiconductor device and a method of manufacturing the same, The present invention relates to a GaN-based compound power semiconductor device for forming individual bumps in a bonding pad of a module substrate to be mounted, and a manufacturing method thereof. According to the present invention, an AlGaN HEMT device is flip-chip bonded on the substrate to efficiently dissipate heat generated in the device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power semiconductor device and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaN (gallium nitride) compound semiconductor device and a manufacturing method thereof, and more particularly, to a GaN semiconductor device having a contact pad formed on a GaN power semiconductor device for flip- The present invention relates to a GaN-based compound semiconductor power semiconductor device in which bumps are formed on bonding pads of module substrates on which GaN power semiconductor devices are to be mounted to modularize individual semiconductor devices, and a manufacturing method thereof.

The AlGaN / GaN HEMT (High Electron Mobility Transistor) device is a power semiconductor device widely used in fields requiring high output, and is bonded by wire bonding or flip-chip bonding . GaN (gallium nitride) HEMT devices as power semiconductors have high power output of several hundred W or more at a few watts, so heat dissipation should be good, and parasitic inductance should be small for RF HEMTs .

Therefore, the high output RF HEMT device should be flip chip bonding that has good heat dissipation characteristics and small parasitic inductance, and should be designed so that the heat can be released well when designing the device. In addition, the substrate on which the HEMT device is to be mounted should be designed and manufactured as a substrate of a material and structure with good heat dissipation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a GaN-based compound semiconductor power semiconductor device having a contact pad having a structure capable of releasing heat generated in an active device well, and a method of manufacturing the same.

An object of the present invention is to provide a GaN-based compound power semiconductor device and a method of manufacturing the same that form pad positions and structures of a substrate on which an active device is to be mounted so that heat generated from the active device can be well emitted.

An object of the present invention is to provide a GaN-based compound semiconductor power semiconductor device which forms a bump having a diameter of about 15 to 20 mu m by forming a bump for flip chip bonding at a wafer level, And a manufacturing method thereof.

It is an object of the present invention to provide a GaN-based compound power semiconductor device and a method of manufacturing the same, in which a substrate structure is formed so that heat generated from an active device is well emitted through a substrate.

To this end, a power semiconductor device according to a first aspect of the present invention includes: a gallium nitride compound device grown on a wafer; A contact pad for forming a source, a drain, and a gate in the gallium nitride compound semiconductor device; A module substrate on which the gallium nitride compound device is flip-chip bonded; A bonding pad formed on the module substrate; And a bump formed on the bonding pad of the module substrate so that the contact pad of the gallium nitride compound device and the bonding pad of the module substrate are bonded so that the gallium nitride compound device and the module substrate can be flip- .

According to a second aspect of the present invention, there is provided a method of fabricating a power semiconductor device including: forming a device layer by growing a gallium nitride compound semiconductor device on a wafer; Forming a contact pad for forming a source, a drain, and a gate in the gallium nitride compound semiconductor device; Forming a bonding pad on the module substrate substrate at a position corresponding to the contact pad formed; And forming a bump on the bonding pad of the module substrate, bonding the contact pad of the gallium nitride compound device and the bonding pad of the module substrate by the bump to bond the gallium nitride compound device and the module substrate And flip chip bonding the semiconductor chip.

The present invention has an effect that a sub contact pad (sub-drain contact pad) is formed at a drain contact portion where a large amount of heat is generated in an AlGaN / GaN HEMT device and heat can be efficiently discharged through bumps bonded to the pad .

In addition, since the contact pads and the sub contact pads of the active device using the bonding pad structure and the substrate structure of the AlGaN / GaN HEMT device according to the present invention are connected to the substrate pads by the bumps, the heat dissipation is good.

Further, the present invention has the effect of reducing the process cost by forming the bumps at the wafer level.

In addition, the present invention has the advantage of less work risk than forming bumps on the active element pad by forming bumps on the substrate pad.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an AlGaN / GaN HEMT device according to an embodiment of the present invention flip-chip bonded on a module substrate. FIG.
2 is a view illustrating a bonding pad of an AlGaN / GaN HEMT device according to an embodiment of the present invention.
3 is a view showing a bonding pad of a module substrate for flip chip bonding according to an embodiment of the present invention.
FIG. 4 is a schematic view showing a thermal via and a backside metal of a module substrate according to an embodiment of the present invention. FIG.

The present invention relates to a GaN-based compound power semiconductor device and a method of manufacturing the same. In an active device used for power semiconductor, a chip pad capable of performing flip chip bonding is formed in order to increase heat dissipation efficiency. At this time, according to the embodiment of the present invention, a structure capable of efficiently discharging heat generated in the drain adjacent to the gate, which is the region where the most heat is generated among the active elements, is formed.

Accordingly, in the present invention, a bonding pad is formed on the module substrate on which the active device is to be mounted, so that the active device can be flip-chip bonded. Further, a bump is formed on the bonding pad of the module substrate to realize flip chip bonding. At this time, the bumps are formed at the wafer level.

In addition, in accordance with embodiments of the present invention, a thermal via is formed in the substrate such that heat generated in the active device is well emitted through the substrate.

Meanwhile, according to the embodiment of the present invention, the source contact pads of the active device form a plurality of thermal pads at the edge of the active device except for the drain contact pads and gate pads for ground stability and heat dissipation .

According to the embodiment of the present invention, the drain contact pad can be formed as a single drain contact pad by bundling a plurality of drain contact portions, but has a sub contact pad (i.e., a sub drain contact pad) for each drain contact portion And a contact pad (drain contact pad) connecting each drain to one drain contact pad.

Meanwhile, in the active device according to the embodiment of the present invention, passivation of the contact pad must be opened for flip chip bonding. In addition, according to the embodiment of the present invention, the substrate material must be such that heat generated from the active device is effectively radiated through the substrate.

In accordance with an embodiment of the present invention, a thermal via is formed in the substrate such that heat generated in the active device is well ejected through the substrate, and the via is filled with metal. At this time, the thermal via is filled with metal using a printing process. Finally, according to the embodiment of the present invention, the active element is mounted on the front surface (front surface) of the substrate, and the back surface of the substrate is thinly deposited with a metal such as Au to directly contact the module surface.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The configuration of the present invention and the operation and effect thereof will be clearly understood through the following detailed description. Before describing the present invention in detail, the same components are denoted by the same reference symbols as possible even if they are displayed on different drawings. In the case where it is judged that the gist of the present invention may be blurred to a known configuration, do.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram illustrating flip chip bonding of an AlGaN / GaN HEMT device according to an embodiment of the present invention on a module substrate. FIG.

1, an AlGaN / GaN layer 13 in an AlGaN / GaN HEMT device 10 according to an embodiment of the present invention includes a wafer 14 made of silicon carbide (SiC), sapphire, silicon (Si) ).

In the AlGaN / GaN HEMT device process, an active, such as a source, a drain, and a gate, is formed, and a contact pad 11 for connecting a signal line to an ohmic contact of a source and a drain is formed. In Fig. 1, the contact pad 11 is a source or drain contact pad. A gate contact pad 12 is also formed which connects the signal line to the gate ohmic contact.

On the other hand, a signal line 21 and a bonding pad 24 are formed on the upper surface of the substrate, and an AlGaN / GaN HEMT element (not shown) is formed through the bumps 23, 10 are mounted on the substrate 20.

The metal material forming the bumps 23 for the flip chip bonding preferably uses a metal material having a composition similar to that of the metal material forming the contact pads 11 of the HEMT element and the bonding pads 24 of the substrate.

In order for the HEMT device 10 to be flipped and bonded to the substrate 20, the HEMT device 10 and the substrate 20 must be heated to a temperature at which the bumps 23 are melted, It is preferred that the temperature is kept below the process temperature of the active device so that the device is not subject to damage due to bonding and the bump 23 should be a material that melts at a temperature lower than the process temperature of the active device.

2 is a configuration diagram illustrating an AlGaN / GaN HEMT device according to an embodiment of the present invention.

In the HEMT device of FIG. 2, the region where the source 31, the drain 41 and the gate 51 are formed is denoted by the active region 60, the source contact pad 30 is denoted by S, The pad 40 is denoted by D and the contact pad 50 of the gate is denoted by G. [

When the HEMT device is mounted on the substrate, the source, drain, and gate contact pads 30, 40 and 50 of the HEMT device are bonded to the source, drain, and gate contact bonding pads of the substrate, respectively, and are bonded in a vertically symmetrical or bilaterally symmetrical structure. Therefore, the contact pad of the HEMT device should be designed to be symmetrical with the bonding pad of the substrate.

In order to flip-chip bond a HEMT device according to an embodiment of the present invention, a source contact pad 30, a drain contact pad 40, a gate contact pad (not shown) may be formed at the time of opening a bonding pad of a passivated HEMT device The source contact pad 32 and the sub drain contact pad 42 are opened to the source and drain of the active region 60 in addition to the source contact pad 50 and the sub drain contact pad 42.

The shapes and sizes of the sub-source contact pad 32 and the sub-drain contact pad 42 are determined by the shapes and sizes of the bumps to be formed on the sub-source contact bonding pad 91 and the sub-drain contact bonding pad 71 of the corresponding substrate, And is smaller than the size of the source 31 and the drain 41 in accordance with the size.

3 is a block diagram showing a module substrate and bumps for flip chip bonding of a HEMT device according to an embodiment of the present invention.

3, the source contact bonding pad 90, the drain contact bonding pad 70 and the gate contact bonding pad 80 of the module substrate are electrically connected to the source contact pad 30, the drain contact pad 40, (50).

The sub-source contact bonding pad 91 and the sub-drain contact bonding pad 71 of the substrate are formed to correspond to the shapes and sizes of the sub-source contact pad 32 and the sub-drain contact pad 42 of the HEMT device, respectively. At this time, the bumps to be formed for chip chip bonding use a metal material having a composition similar to that of the metal material forming the pad of the HEMT element and the pad of the substrate.

In general, in the AlGaN / GaN HEMT device, the source 31 and drain 41 of the active region 60 include ohmic contact metals such as Au and include a source contact pad 30, a drain contact pad 40 Source contact bonding pad 90, drain contact bonding pad 70, gate contact bonding pad 80 and sub-source contact bonding pad 91, and the gate contact pad 50, The sub-drain contact bonding pad 71 preferably includes Au. In addition, because the device process temperature is about 300 ° C., a material such as SnAu having a bonding temperature of about 250 ° C. is deposited by e-beam evaporation to form bumps.

According to yet another embodiment, the source contact bonding pad 90, the drain contact bonding pad 70 and the gate contact bonding pad 80 of the substrate are connected to the source contact pad 30 of the HEMT device, the drain contact pad 40, And may be formed in a symmetrical structure with the contact pad 50.

4 is a structural view showing a thermal via of a module substrate and a metal formed on a rear surface of the substrate according to an embodiment of the present invention.

The source contact bonding pad 140 bonded to the source contact pad 30 of the HEMT device in the module substrate 100 is formed with a through via 110 penetrating the substrate on the bottom surface thereof, back side metal 160. As shown in FIG.

Signals that are bonded to the source contact pad 30 of the HEMT device and to the drain and gate of the HEMT device are applied through traces 130 on the substrate. The bonding pad 120 on the substrate represents a drain or gate contact bonding pad of the substrate bonded to the drain or gate contact pads of the HEMT device. The substrate bonding pad 150 represents the sub-drain contact bonding pad 150 of the substrate to be bonded to the sub-drain contact pad 42 of the HEMT device.

The substrate bonding pad 180 also represents the sub-source contact bonding pad 180 of the substrate to be bonded to the sub-source contact pad 32 of the HEMT device.

The backside metal 160 is coated on the backside of the substrate to contact the metal housing module to quickly dissipate the heat generated by the HEMT device and reduce the noise by widening the ground plane of the device.

The through vias 110 of the module substrate are formed with a laser having the same size as the substrate source contact pads or a size slightly smaller than the source contact pads and then printed with a metal having high thermal conductivity such as copper, Fill the hole. Subsequently, the substrate backside metal 160 is formed by depositing a copper film of about 5 탆 by a printing method or depositing Ti / Au at a thickness of 0.5 탆 or less by sputtering or e-beam evaporation, 3 mu m of Au is deposited.

The formation of the source contact bonding pad 140, the sub drain contact bonding pad 150, the sub-source contact bonding pad 180, the gate contact bonding pad 120 and the trace 130 of the substrate may be performed using a chromium mask, .

 A photoresist is coated on the entire surface of the substrate, and then the photoresist is exposed and developed using a mask to form a source contact bonding pad 140, a sub-drain contact bonding pad 150, a sub-source contact bonding pad 180, After the bonding pad 120 and the trace 130 are opened and Ti / Au is deposited to a thickness of about 0.5 탆 by e-beam evaporation, the photoresist film is removed.

Thereafter, Ti / Au is sputtered on the entire surface of the substrate to a thickness of about several hundreds of angstroms / several tens of Angstroms, a photoresist is coated on the entire surface of the substrate, and then the photoresist is exposed and developed using a mask, The sub-source contact bonding pad 150, the sub-source contact bonding pad 180, the gate contact bonding pad 120, and the trace 130 are opened and Au plating is performed to a thickness of about 1 μm.

After the photoresist layer is completely removed, the photoresist layer is coated on the entire surface of the substrate. Then, the photoresist layer is exposed and developed using a mask to form a source contact bonding pad 140, a sub-drain contact bonding pad 150, 180, the gate contact bonding pad 120 is opened, and Au is plated to a thickness of about 5 占 퐉 by electroplating to form bumps 170. Then, the photoresist film is removed and the seed metal is removed by wet-etching.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

10: HEMT element 11: contact pad
12: gate contact pad 13: AlGaN / GaN layer
14: wafer 20: substrate
21: Signal line 22: Substrate compound
23: Bump 24: Bonding pad
30: source contact pad 31: source
32: Sub-source contact pad 40: Drain contact pad
41: drain 42: sub drain contact pad
50: gate contact pad 51: gate
60: active region 70: drain contact bonding pad
71: Sub-drain contact bonding pad 80: Gate contact bonding pad
90: source contact bonding pad 91: sub-source contact bonding pad
100: module substrate 110: through vias
120: bonding pad 130: trace
140: source contact bonding pad 150: sub drain contact bonding pad
160: back metal 170: bump
180: Sub-source contact bonding pad

Claims (14)

A gallium nitride compound device grown on a wafer;
A contact pad for forming a source, a drain, and a gate in the gallium nitride compound semiconductor device;
A module substrate on which the gallium nitride compound device is flip-chip bonded;
A bonding pad formed on the module substrate; And
A bump formed on the bonding pad of the module substrate so that the contact pad of the gallium nitride compound device and the bonding pad of the module substrate are bonded to each other so that the gallium nitride compound device and the module substrate can be flip chip bonded; , ≪ / RTI &
Wherein the gallium nitride compound semiconductor device forms a sub-source contact pad or a sub-drain contact pad at a source or a drain of an active region,
Wherein the module substrate further comprises a sub-source contact bonding pad or a sub-drain contact bonding pad corresponding to the sub-source contact pad or the sub-drain contact pad, respectively. The gallium nitride compound semiconductor device according to claim 1,
Wherein the semiconductor chip is disposed in a vertically symmetrical or horizontally symmetrical configuration with the bonding pad formed on the module substrate. delete delete The method of claim 1,
Wherein the gallium nitride compound semiconductor device is melted at a temperature lower than the process temperature of the gallium nitride compound device. The module substrate according to claim 1,
Wherein a through hole is formed in a size smaller than that of the contact pad to dissipate heat generated in the gallium nitride compound semiconductor device. 7. The module board according to claim 6,
And a metal is formed on a back surface of the module substrate so that heat through the through vias is radiated through the housing. Growing a gallium nitride compound semiconductor device on a wafer to form an element layer;
Forming a contact pad for forming a source, a drain, and a gate in the gallium nitride compound semiconductor device;
Forming a bonding pad on the module substrate at a position corresponding to the formed contact pad; And
The bump is formed on the bonding pad of the module substrate, and the contact pad of the gallium nitride compound device and the bonding pad of the module substrate are bonded to each other by the bump formed on the module substrate, Flip chip bonding,
Wherein the gallium nitride compound semiconductor device forms a sub-source contact pad or a sub-drain contact pad at a source or a drain of an active region,
Wherein the module substrate further comprises a sub-source contact bonding pad or a sub-drain contact bonding pad corresponding to the sub-source contact pad or the sub-drain contact pad, respectively. 9. The device according to claim 8, wherein the contact pads of the gallium nitride compound semiconductor device
Wherein the bonding pad is disposed in a vertically symmetrical or horizontally symmetrical configuration with the bonding pad formed on the module substrate. delete delete 9. The bump of claim 8,
And melting at a temperature lower than the process temperature of the gallium nitride compound semiconductor device. 9. The module substrate according to claim 8,
Wherein a through hole is formed in a size smaller than that of the contact pad to dissipate heat generated in the gallium nitride compound semiconductor device. 14. The module according to claim 13,
And a metal is formed on a back surface of the module substrate so that heat through the through vias is dissipated through the housing.
KR1020100127921A 2010-11-19 2010-12-14 Wafer level packaged GaN power device and the manufacturing method thereof KR101719670B1 (en)

Priority Applications (2)

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US13/185,780 US8519548B2 (en) 2010-11-19 2011-07-19 Wafer level packaged GaN power device and the manufacturing method thereof
US13/950,368 US8691627B2 (en) 2010-11-19 2013-07-25 Wafer level packaged GaN power device and manufacturing method thereof

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KR1020100115894 2010-11-19
KR20100115894 2010-11-19

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US10651107B2 (en) 2017-09-26 2020-05-12 Electronics And Telecommunications Research Institute Semiconductor device and method for fabricating the same
CN109935561A (en) * 2017-12-18 2019-06-25 镓能半导体（佛山）有限公司 A kind of packaging method of gallium nitride device and gallium nitride device
KR102304613B1 (en) * 2019-12-26 2021-09-24 알에프에이치아이씨 주식회사 Gallium nitride-based semiconductor package and method for fabricating thereof

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JP2001185561A (en) 2000-10-30 2001-07-06 Nec Corp Semiconductor device
JP2005079550A (en) 2003-09-03 2005-03-24 Toyoda Gosei Co Ltd Composite substrate for forming semiconductor light-emitting element and manufacturing method thereof, and method for semiconductor light-emitting element
JP2009176839A (en) 2008-01-22 2009-08-06 Mitsubishi Electric Corp Heat dissipation structure of semiconductor element

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US6825559B2 (en) * 2003-01-02 2004-11-30 Cree, Inc. Group III nitride based flip-chip intergrated circuit and method for fabricating

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JP2001185561A (en) 2000-10-30 2001-07-06 Nec Corp Semiconductor device
JP2005079550A (en) 2003-09-03 2005-03-24 Toyoda Gosei Co Ltd Composite substrate for forming semiconductor light-emitting element and manufacturing method thereof, and method for semiconductor light-emitting element
JP2009176839A (en) 2008-01-22 2009-08-06 Mitsubishi Electric Corp Heat dissipation structure of semiconductor element

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