KR20120054495A - Wafer level packaged gan power device and the manufacturing method thereof - Google Patents

Wafer level packaged gan power device and the manufacturing method thereof Download PDF

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Publication number
KR20120054495A
KR20120054495A KR1020100127921A KR20100127921A KR20120054495A KR 20120054495 A KR20120054495 A KR 20120054495A KR 1020100127921 A KR1020100127921 A KR 1020100127921A KR 20100127921 A KR20100127921 A KR 20100127921A KR 20120054495 A KR20120054495 A KR 20120054495A
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South Korea
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gallium nitride
module substrate
pad
nitride compound
sub
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KR1020100127921A
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Korean (ko)
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KR101719670B1 (en
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주철원
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한국전자통신연구원
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Priority to US13/185,780 priority Critical patent/US8519548B2/en
Publication of KR20120054495A publication Critical patent/KR20120054495A/en
Priority to US13/950,368 priority patent/US8691627B2/en
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Publication of KR101719670B1 publication Critical patent/KR101719670B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: A GaN system compound power semiconductor device and a manufacturing method thereof are provided to efficiently release heat created in an AlGaN HEMT after the AlGaN HEMT is flip-chip-bonded to a substrate. CONSTITUTION: A gallium nitride-based compound device grows on a wafer. A contact pad(11) forms a source, a drain, and a gate in the gallium nitride-based compound device. The gallium nitride-based compound device is flip-chip-bonded on a module substrate. A bonding pad(24) is formed on the module substrate. A bump(23) is formed in the bonding pad of the module substrate so that the gallium nitride-based compound device is flip-chip-bonded on the module substrate. A sub source contact pad and a sub drain source contact pad are formed in the source and the drain.

Description

Wafer-based compound power semiconductor device and manufacturing method therefor {Wafer level packaged GaN power device and the manufacturing method}

The present invention relates to a GaN (gallium nitride) compound power semiconductor device and a method for manufacturing the same, and more specifically, to form a contact pad in the GaN power semiconductor device for flip-chip (bond flip-chip) bonding (bonding), The present invention relates to a GaN compound power semiconductor device for forming individual bumps by forming bumps on a bonding pad of a module substrate on which a GaN power semiconductor device is to be mounted, and a method of manufacturing the same.

AlGaN / GaN HEMT (High Electron Mobility Transistor) devices are power semiconductor devices that are widely used in high power applications and are bonded by wire bonding or flip-chip. . As a power semiconductor device, GaN (gallium nitride) HEMT device generates a lot of heat because the output is high at 100W or more at several W. Therefore, the heat dissipation should be good. In the case of RF HEMT, parasitic inductance should be small. .

Therefore, high-power RF HEMT devices should have flip chip bonding, which has good heat dissipation characteristics and low parasitic inductance, and should be designed to have good heat dissipation. In addition, when the module is manufactured, the board on which the HEMT device is to be mounted should be designed and manufactured with a board having a material and structure that emits heat well.

SUMMARY OF THE INVENTION An object of the present invention is to provide a GaN compound power semiconductor device having a contact pad having a structure capable of dissipating heat generated from an active device well and a method of manufacturing the same.

An object of the present invention is to provide a GaN-based compound power semiconductor device and a method of manufacturing the same to form the pad position and structure of the substrate on which the active device is mounted so that heat generated in the active device can be well discharged.

An object of the present invention is a GaN compound power semiconductor device for forming a bump having a diameter of about 15 ~ 20 ㎛ by forming a bump for flip chip bonding that can emit heat generated in the active device at the wafer level and its size It is to provide a manufacturing method.

An object of the present invention is to provide a GaN compound power semiconductor device for forming a substrate structure so that heat generated in the active device is well discharged through the substrate and a method of manufacturing the same.

To this end, the power semiconductor device according to the first aspect of the present invention, a gallium nitride compound device formed by growing on a wafer; A contact pad forming a source, a drain, and a gate in the gallium nitride compound device; A module substrate on which the gallium nitride compound device is flip chip bonded; Bonding pads formed on the module substrate; And bumps formed on the bonding pads of the module substrate such that the contact pads of the gallium nitride compound elements and the bonding pads of the module substrate are bonded to flip-bond the gallium nitride compound elements and the module substrate. It includes;

According to a second aspect of the present invention, there is provided a method of manufacturing a power semiconductor device, the method comprising: forming a device layer by growing a gallium nitride compound device on a wafer; Forming contact pads for forming a source, a drain, and a gate in the gallium nitride compound device; Forming a bonding pad on a module substrate substrate at a position corresponding to the formed contact pad; And forming bumps on the bonding pads of the module substrate, and bonding the contact pads of the gallium nitride compound elements and the bonding pads of the module substrate by the formed bumps to bond the gallium nitride compound elements and the module substrate. And flip chip bonding.

According to the present invention, a sub-contact pad (sub-drain contact pad) is formed in a drain contact portion that generates a lot of heat in an AlGaN / GaN HEMT device, and heat can be efficiently discharged through a bump bonded to the pad. .

In addition, since the contact pads and the sub contact pads of the active device using the bonding pad structure and the substrate structure of the AlGaN / GaN HEMT device according to the present invention are connected to the substrate pads with bumps, heat dissipation is well performed.

In addition, the present invention has the effect of reducing the process cost by forming the bump at the wafer level.

In addition, the present invention has the advantage of less risk of operation than forming bumps on active element pads by forming bumps on substrate pads.

1 is a block diagram illustrating flip chip bonding of an AlGaN / GaN HEMT device according to an embodiment of the present invention on a module substrate;
2 is a diagram illustrating a bonding pad of an AlGaN / GaN HEMT device according to an exemplary embodiment of the present invention.
3 is a block diagram illustrating a bonding pad of a module substrate for flip chip bonding according to an embodiment of the present invention.
4 is a block diagram illustrating a thermal via and a backside metal of a module substrate according to an embodiment of the present invention.

The present invention relates to a GaN-based compound power semiconductor device and a method of manufacturing the same, to form a chip pad in the form of flip chip bonding in the active (active) device used in the power semiconductor to increase the heat dissipation efficiency. At this time, according to an embodiment of the present invention to form a structure capable of efficiently dissipating the heat generated from the drain adjacent to the gate which is the site where the most heat generated among the active elements.

Therefore, in the present invention, a bonding pad is formed on the module substrate on which the active element is to be mounted so that the active element can be flip chip bonded. In addition, flip chip bonding is implemented by forming bumps on the bonding pads of the module substrate. At this time, the bump is formed at the wafer level.

In addition, according to an embodiment of the present invention, a thermal via is formed in the substrate so that heat generated in the active device is well discharged through the substrate.

Meanwhile, according to an embodiment of the present invention, the source contact pad of the active device may form a plurality of thermal pads at the edges of the active device except for the drain contact pad and the gate pad for ground stability and heat dissipation. Can be.

According to an embodiment of the present invention, the drain contact pad may be a drain contact pad by tying several drain contact portions, but each drain contact portion has a sub contact pad (ie, a sub-drain contact pad). Each drain may be formed as a contact pad (drain contact pad) that is connected to each other and bundled into one drain contact pad.

On the other hand, in the active device according to an embodiment of the present invention that can implement the above characteristics, the passivation of the contact pad must be open to flip chip bonding. In addition, according to an embodiment of the present invention, the heat generated from the active element should be a substrate material that is effectively released through the substrate.

In addition, according to an embodiment of the present invention, a thermal via is formed on the substrate so that heat generated in the active device is well discharged through the substrate, and the via is filled with a metal. In this case, the thermal via fills the metal using a printing process. Finally, according to an embodiment of the present invention, an active element is mounted on the front surface (front side) of the substrate, and the back surface (back side) of the substrate is thinly deposited with a metal such as Au to directly contact the module surface so that heat is well released.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The configuration of the present invention and the operation and effect thereof will be clearly understood through the following detailed description. Prior to the detailed description of the present invention, the same components will be denoted by the same reference numerals even if they are displayed on different drawings, and the detailed description will be omitted when it is determined that the well-known configuration may obscure the gist of the present invention. do.

1 is a block diagram illustrating flip chip bonding of an AlGaN / GaN HEMT device on a module substrate according to an embodiment of the present invention.

Referring to FIG. 1, in an AlGaN / GaN HEMT device 10 according to an embodiment of the present invention, the AlGaN / GaN layer 13 may include a wafer 14 made of silicon carbide (SiC), sapphire, silicon (Si), or the like. Is grown on).

In an AlGaN / GaN HEMT device process, an active source, a drain, a gate, and the like are formed, and a contact pad 11 connecting a signal line to an ohmic contact of the source and the drain is formed. In FIG. 1 the contact pad 11 is a source or drain contact pad. In addition, a gate contact pad 12 for connecting a signal line to the gate ohmic contact is formed.

Meanwhile, the substrate 20 for modularization uses alumina (Al 2 O 3) or AlN, and a signal line 21 and a bonding pad 24 are formed on an upper surface of the substrate, and the AlGaN / GaN HEMT element (Bump 23) is formed on the substrate 20. 10 is mounted on the substrate 20.

The metal material forming the bumps 23 for flip chip bonding preferably uses a metal material similar to that of the metal material forming the contact pads 11 of the HEMT element and the bonding pads 24 of the substrate.

In addition, in order for the HEMT element 10 to be flipped and bonded to the substrate 20, the HEMT element 10 and the substrate 20 must be heated to a temperature at which the bumps 23 are melted. The temperature is preferably heated to a temperature lower than the process temperature of the active device so that the device is not damaged by bonding, and the bump 23 should be a material that melts at a temperature lower than the process temperature of the active device.

2 is a block diagram showing an AlGaN / GaN HEMT device according to an embodiment of the present invention.

In the HEMT device of FIG. 2, the region in which the source 31, the drain 41, and the gate 51 are formed is denoted as an active region 60, the contact pad 30 of the source is denoted as S, and the drain contacts The pad 40 is labeled D, and the contact pad 50 of the gate is labeled G.

When the HEMT device is mounted on a substrate, the source, drain, and gate contact pads 30, 40, and 50 of the HEMT device are bonded to the source, drain, and gate contact bonding pads of the substrate, respectively, and are bonded in a vertically or symmetrical structure. Therefore, the contact pad of the HEMT device should be designed to be symmetrical with the bonding pad of the substrate.

In addition, the source contact pads 30, the drain contact pads 40, and the gate contact pads when the bonding pads of a passivated HEMT device are opened to flip-chip a HEMT device according to an exemplary embodiment of the present invention. In addition to 50, a sub source contact pad 32 and a sub drain contact pad 42 are opened at the source and the drain of the active region 60.

The shape and size of the sub-source contact pad 32 and the sub-drain contact pad 42 may correspond to the shape of the bump to be formed on the sub-source contact bonding pad 91 and the sub-drain contact bonding pad 71 of the corresponding substrate, respectively. The opening is smaller than the size of the source 31 and the drain 41 according to the size.

3 is a block diagram illustrating a module substrate and bumps for flip chip bonding an HEMT device according to an exemplary embodiment of the present invention.

In FIG. 3, the source contact bonding pad 90, the drain contact bonding pad 70, and the gate contact bonding pad 80 of the module substrate are the source contact pad 30, the drain contact pad 40, and the gate contact pad of the HEMT device. It has a vertically and symmetrical structure with (50).

The sub source contact bonding pads 91 and the sub drain contact bonding pads 71 of the substrate are formed to correspond to the shapes and sizes of the sub source contact pads 32 and the sub drain contact pads 42 of the HEMT element, respectively. In this case, the bump to be formed for full chip chip bonding uses a metal material similar to that of the metal material forming the pad of the HEMT element and the pad of the substrate.

In general, in the AlGaN / GaN HEMT device, the source 31, the drain 41, and the ohmic contact metal of the active region 60 include Au, the source contact pad 30, and the drain contact pad 40. ), Since the gate contact pad 50 also contains Au, the source contact bonding pad 90, the drain contact bonding pad 70, the gate contact bonding pad 80 and the sub-source contact bonding pad 91 of the substrate, and The sub-drain contact bonding pads 71 preferably include Au. In addition, since the device process temperature is about 300 ° C., a material such as SnAu having a bonding temperature of about 250 ° C. is deposited by e-beam evaporation to form bumps.

According to another embodiment, the source contact bonding pads 90, the drain contact bonding pads 70, and the gate contact bonding pads 80 of the substrate may include the source contact pads 30, the drain contact pads 40, and the gates of the HEMT device. The contact pad 50 may be formed in a symmetrical structure.

FIG. 4 is a diagram illustrating a thermal via and a metal formed on a back surface of a module substrate according to an exemplary embodiment of the present invention.

The source contact bonding pad 140 bonded to the source contact pad 30 of the HEMT device in the module substrate 100 has a through via 110 penetrating the substrate at the bottom thereof, so that the back surface ( back side) is connected to the metal 160.

A signal that is bonded to the source contact pad 30 of the HEMT device and sent to the drain and gate of the HEMT device is applied through a trace 130 on the substrate. The bonding pad 120 on the substrate represents the drain or gate contact bonding pad of the substrate bonded with the contact pad of the drain or gate of the HEMT device. The bonding pad 150 on the substrate represents the sub-drain contact bonding pad 150 of the substrate bonded with the sub-drain contact pad 42 of the HEMT device.

In addition, the bonding pads 180 on the substrate represent the sub-source contact bonding pads 180 of the substrate bonded to the sub-source contact pads 32 of the HEMT device.

A backside metal 160 is coated on the back side of the substrate to quickly dissipate heat generated from the HEMT device in contact with the metal housing module, and to reduce noise by widening the ground plane of the device.

The through vias 110 of the module substrate are formed with a laser the same size as the substrate source contact pads or slightly smaller than the source contact pads, and then printed vias with good thermal conductivity metals such as copper. Fill the hall. Subsequently, the substrate backside metal 160 may form a copper film having a thickness of about 5 μm by printing, or electroplating after depositing Ti / Au to 0.5 μm or less by sputtering or e-beam evaporation, respectively. Au is deposited by 3 µm.

In addition, the source contact bonding pads 140, the sub-drain contact bonding pads 150, the sub-source contact bonding pads 180, the gate contact bonding pads 120, and the traces 130 may be formed using a chrome mask. Form by process.

 In the process, the photoresist is first applied to the entire surface of the substrate, and then the photoresist is exposed and developed by using a mask. The source contact bonding pad 140, the sub drain contact bonding pad 150, the sub source contact bonding pad 180, and the gate contact The bonding pad 120 and the trace 130 are opened and Ti / Au is deposited by about 0.5 μm by e-beam evaporation to remove the photoresist.

Subsequently, after sputtering Ti / Au with a seed metal on the front of the substrate to about several hundreds / s and several tens of micrometers, the photoresist is applied to the entire surface of the substrate, and then the photoresist is exposed and developed using a mask to perform source contact bonding pads 140. The sub-drain contact bonding pad 150, the sub-source contact bonding pad 180, the gate contact bonding pad 120, and the trace 130 are opened, and Au plating is performed about 1 μm.

After removing the photoresist film, the photoresist film is applied to the entire surface of the substrate, and then the photoresist film is exposed and developed by using a mask to perform a source contact bonding pad 140, a sub-drain contact bonding pad 150, and a sub-source contact bonding pad ( 180), the gate contact bonding pad 120 is opened and Au is plated by about 5 μm by electroplating to form a bump 170. The photoresist layer is removed, and the seed metal is removed by wet etching.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the claims below, and all techniques within the scope equivalent thereto will be construed as being included in the scope of the present invention.

10 HEMT element 11: contact pad
12 gate contact pad 13 AlGaN / GaN layer
14 wafer 20 substrate
21: signal line 22: substrate compound
23: bump 24: bonding pad
30: source contact pad 31: source
32: sub source contact pad 40: drain contact pad
41 Drain 42 Sub Drain Contact Pad
50: gate contact pad 51: gate
60: active area 70: drain contact bonding pad
71: sub-drain contact bonding pad 80: gate contact bonding pad
90 source contact bonding pad 91 sub source contact bonding pad
100: module substrate 110: through via
120: bonding pad 130: trace
140: source contact bonding pad 150: sub-drain contact bonding pad
160: back metal 170: bump
180: sub source contact bonding pad

Claims (14)

A gallium nitride compound device formed by growing on a wafer;
A contact pad forming a source, a drain, and a gate in the gallium nitride compound device;
A module substrate on which the gallium nitride compound device is flip chip bonded;
Bonding pads formed on the module substrate; And
A bump formed on the bonding pad of the module substrate such that the contact pad of the gallium nitride compound device and the bonding pad of the module substrate are bonded to flip-bond the gallium nitride compound device and the module substrate; Gallium nitride-based compound power semiconductor device comprising a. The method of claim 1, wherein the contact pad of the gallium nitride compound device,
Gallium nitride-based compound power semiconductor device, characterized in that arranged in the vertical symmetrical or symmetrical structure with the bonding pad formed on the module substrate. The method of claim 1, wherein the gallium nitride compound device,
A gallium nitride compound power semiconductor device comprising forming a sub source contact pad or a sub drain contact pad in a source or a drain of an active region. The method of claim 3, wherein the module substrate,
And a sub source contact bonding pad or a sub drain contact bonding pad respectively corresponding to the sub source contact pad or the sub drain contact pad, respectively. The method of claim 1, wherein the bump,
Gallium nitride compound power semiconductor device, characterized in that the melting at a temperature lower than the process temperature of the gallium nitride compound device. The method of claim 1, wherein the module substrate,
Gallium nitride-based compound power semiconductor device, characterized in that the through via to form a smaller than the contact pad to dissipate heat generated in the gallium nitride-based compound element. The method of claim 6, wherein the module substrate,
Gallium nitride-based compound power semiconductor device, characterized in that to form a metal on the back of the module substrate so that heat through the through via heat dissipation through the housing. Growing a gallium nitride compound device on the wafer to form a device layer;
Forming contact pads for forming a source, a drain, and a gate in the gallium nitride compound device;
Forming a bonding pad on a module substrate substrate at a position corresponding to the formed contact pad; And
A bump is formed on the bonding pad of the module substrate, and the contact pad of the gallium nitride compound device and the bonding pad of the module substrate are bonded by the formed bump to form the gallium nitride compound device and the module substrate. Flip chip bonding step; manufacturing method of a gallium nitride compound semiconductor device comprising a. The method of claim 8, wherein the contact pad of the gallium nitride compound device,
The method of manufacturing a gallium nitride compound power semiconductor device, characterized in that arranged in the vertical symmetrical or symmetrical structure with the bonding pad formed on the module substrate. The method of claim 8, wherein the gallium nitride compound device,
A method of manufacturing a gallium nitride compound power semiconductor device comprising forming a sub-source contact pad or a sub-drain contact pad in a source or a drain of an active region. The method of claim 10, wherein the module substrate,
Further comprising a sub source contact bonding pad or a sub drain contact bonding pad corresponding to the sub source contact pad or the sub drain contact pad, respectively. The method of claim 8, wherein the bump,
A method for producing a gallium nitride compound power semiconductor device, characterized in that the melting at a temperature lower than the process temperature of the gallium nitride compound element. The method of claim 8, wherein the module substrate,
And a through via having a smaller size than the contact pad to dissipate heat generated by the gallium nitride compound device. The method of claim 13, wherein the module substrate,
And forming a metal on the back surface of the module substrate so that heat through the through via is radiated through the housing.
KR1020100127921A 2010-11-19 2010-12-14 Wafer level packaged GaN power device and the manufacturing method thereof KR101719670B1 (en)

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Application Number Priority Date Filing Date Title
US13/185,780 US8519548B2 (en) 2010-11-19 2011-07-19 Wafer level packaged GaN power device and the manufacturing method thereof
US13/950,368 US8691627B2 (en) 2010-11-19 2013-07-25 Wafer level packaged GaN power device and manufacturing method thereof

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Application Number Priority Date Filing Date Title
KR1020100115894 2010-11-19
KR20100115894 2010-11-19

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109935561A (en) * 2017-12-18 2019-06-25 镓能半导体（佛山）有限公司 A kind of packaging method of gallium nitride device and gallium nitride device
US10651107B2 (en) 2017-09-26 2020-05-12 Electronics And Telecommunications Research Institute Semiconductor device and method for fabricating the same
KR20210082826A (en) * 2019-12-26 2021-07-06 알에프에이치아이씨 주식회사 Gallium nitride-based semiconductor package and method for fabricating thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001185561A (en) * 2000-10-30 2001-07-06 Nec Corp Semiconductor device
JP2005079550A (en) * 2003-09-03 2005-03-24 Toyoda Gosei Co Ltd Composite substrate for forming semiconductor light-emitting element and manufacturing method thereof, and method for semiconductor light-emitting element
KR20050090438A (en) * 2003-01-02 2005-09-13 크리, 인코포레이티드 Group iii nitride based flip-chip integrated circuit and method for fabricating
JP2009176839A (en) * 2008-01-22 2009-08-06 Mitsubishi Electric Corp Heat dissipation structure of semiconductor element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001185561A (en) * 2000-10-30 2001-07-06 Nec Corp Semiconductor device
KR20050090438A (en) * 2003-01-02 2005-09-13 크리, 인코포레이티드 Group iii nitride based flip-chip integrated circuit and method for fabricating
JP2005079550A (en) * 2003-09-03 2005-03-24 Toyoda Gosei Co Ltd Composite substrate for forming semiconductor light-emitting element and manufacturing method thereof, and method for semiconductor light-emitting element
JP2009176839A (en) * 2008-01-22 2009-08-06 Mitsubishi Electric Corp Heat dissipation structure of semiconductor element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10651107B2 (en) 2017-09-26 2020-05-12 Electronics And Telecommunications Research Institute Semiconductor device and method for fabricating the same
US10784179B2 (en) 2017-09-26 2020-09-22 Electronics And Telecommunications Research Institute Semiconductor device and method for fabricating the same
CN109935561A (en) * 2017-12-18 2019-06-25 镓能半导体（佛山）有限公司 A kind of packaging method of gallium nitride device and gallium nitride device
KR20210082826A (en) * 2019-12-26 2021-07-06 알에프에이치아이씨 주식회사 Gallium nitride-based semiconductor package and method for fabricating thereof

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