KR101712202B1 - Display Device - Google Patents

Abstract

An embodiment of the present invention is a display panel comprising: a panel; A scan driver for supplying a scan signal to the panel; And a data driver for supplying a data signal to the panel and compensating a potential difference between the target voltage and the drive voltage when the drive voltage supplied to the power supply terminal of the output circuit portion does not reach the target voltage do.

Description

[0001]

An embodiment of the present invention relates to a display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the display devices described above, for example, a liquid crystal display device or an organic light emitting display device, are driven by a timing driver, a data driver, and a scan driver. The data driver generates a data signal based on the driving signal supplied from the timing driver, and supplies the data signal to the sub-pixels included in the panel. The data signal generated from the data driver is generated based on the reference voltage supplied from the outside.

On the other hand, a display device displays a specific pattern, for example, a screen saver or the like, rather than a general image, when the panel displays a specific pattern, the amount of current output from the output terminal of the data driver differs from that when a general image is displayed. The conventional data driver can not cope with fluctuations in the output voltage as in the case of displaying a general image or a specific pattern, so that stable driving can not be ensured. Therefore, in the conventional display device, a method for compensating the output voltage variation in correspondence with the image displayed on the panel should be provided.

According to an aspect of the present invention, there is provided a display device capable of reducing the occurrence of defective (e.g., crosstalk) phenomena due to the driving capability of a data driver by ensuring stable driving of the data driver will be.

According to an embodiment of the present invention, A scan driver for supplying a scan signal to the panel; And a data driver for supplying a data signal to the panel and compensating a potential difference between the target voltage and the drive voltage when the drive voltage supplied to the power supply terminal of the output circuit portion does not reach the target voltage do.

The compensation circuit section includes a first compensation circuit section for generating a compensation voltage based on a drive voltage supplied from the outside and outputting a difference voltage through comparison between a drive voltage and a compensation voltage, And a third compensation circuit part for selectively outputting one of a driving voltage and a compensation voltage according to the difference voltage.

The first compensation circuit section may include a switch for switching driving in a section in which the output circuit section is not driven and a compensation voltage generation section including a capacitor for charging the charge so as to have the same potential as the drive voltage by driving the switch.

The section in which the output circuit section is not driven may include a back porch section and a front porch section.

The first compensation circuit includes a first comparator including a first terminal receiving a driving voltage, a second terminal receiving a compensation voltage, and a third terminal outputting a differential voltage through comparison between the driving voltage and the sub voltage And may include a differential voltage generating unit including the differential voltage generating unit.

The second compensation circuit section may include a weighted addition circuit section for adding the driving voltage and the differential voltage to output the output voltage and an inverting circuit section for inverting the potential of the output voltage outputted through the weighted addition circuit section.

The weighted addition circuit includes a first terminal receiving a drive voltage and a difference voltage, a second terminal receiving a ground voltage, and a second comparator including a third terminal outputting an output voltage by adding the drive voltage and the difference voltage Section.

The inversion circuit section includes a first terminal supplied with the output voltage outputted through the weighted addition circuit section, a second terminal supplied with the ground voltage, and a third terminal inverting the potential of the output voltage to output a compensation voltage 3 comparison unit.

The third compensation circuit part includes a selection part for switching driving to selectively output one of a driving voltage and a compensation voltage according to the difference voltage, and the voltage output through the selection part can be supplied to the power supply terminal of the output circuit part.

The selecting section may include a stabilizing element for stabilizing a voltage output from the selecting section.

The embodiment of the present invention compensates the output fluctuation of the driving voltage of the internal circuit of the data driving unit to ensure stable driving of the data driving unit, thereby reducing the defective (for example, crosstalk) phenomenon due to the driving ability of the data driving unit There is an effect of providing a display device capable of performing a display operation.

1 is a schematic block diagram of a display device according to an embodiment of the present invention;
2 is a schematic block diagram of a scan driver;
3 is a schematic block diagram of a data driver;
4 is a block diagram showing a part of a data driver;
5 is a diagram for explaining a section in which a compensation voltage is generated;
6 is a detailed configuration diagram of the first compensation circuit;
7 is a detailed configuration diagram of a second compensation circuit;
8 is a detailed configuration diagram of a third compensation circuit section;
9 is a circuit configuration diagram for explaining the normal drive mode of the data driver;
10 is a circuit configuration diagram for explaining a compensation drive mode of the data driver;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a display device according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of a scan driver, and FIG. 3 is a schematic block diagram of a data driver.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a panel PNL, a timing driver TCN, a scan driver SDRV, and a data driver DDRV.

The timing driver TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK and a data signal DDATA from the outside. The timing driver TCN is connected to the data driver DDRV and the data driver DDRV using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. And controls the operation timing of the driving unit SDRV. The timing driver TCN can count the data enable signal DE in one horizontal period to determine the frame period so that the externally supplied vertical sync signal Vsync and horizontal sync signal Hsync can be omitted. The control signals generated in the timing driver TCN include a gate timing control signal GDC for controlling the operation timing of the scan driver SDRV and a data timing control signal DDC for controlling the operation timing of the data driver DDRV. ) May be included. The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The gate start pulse (GSP) is supplied to a gate drive IC (Integrated Circuit) generating the first scan signal. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The data timing control signal DDC includes source start pulses (Source, Start Pulse, SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and the like. The source start pulse SSP controls the data sampling start timing of the data driver DDRV. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver DDRV based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver DDRV. On the other hand, the source start pulse SSP supplied to the data driver DDRV may be omitted depending on the data transfer method.

The panel (PNL) is formed of a liquid crystal display panel or an organic light emitting display panel including subpixels (SP). When the panel (PNL) is formed of a liquid crystal display panel, the subpixels SP include a switching thin film transistor, a storage capacitor, a pixel electrode, a common electrode, a liquid crystal layer, a color filter, and a black matrix. The subpixels SP formed in the liquid crystal display panel are supplied with scan signals and data signals from the scan driver SDRV and the data driver DDRV, and the data voltages are stored in the storage capacitors by driving the switching thin film transistors. Then, a data voltage is supplied to the pixel electrode, a common voltage is supplied to the common electrode, and the liquid crystal layer is tilted by the electric field formed therebetween. In the liquid crystal display panel, the transmittance of the light provided from the backlight unit is controlled by the liquid crystal layer in the above process, thereby displaying an image. Alternatively, when the panel (PNL) is formed of an organic light emitting display panel, each of the subpixels SP includes a switching thin film transistor, a driving thin film transistor, a capacitor, and an organic light emitting diode. The subpixels SP formed in the liquid crystal display panel are supplied with the scan signals and the data signals from the scan driver SDRV and the data driver DDRV, and the data voltages are stored in the capacitors by driving the switching thin film transistors. Thereafter, when the driving thin film transistor is driven by the data voltage, current flows to the anode and the cathode of the organic light emitting diode. In the organic electroluminescence display panel, light is controlled by a current flowing through the organic light emitting diode in the above process, thereby displaying an image.

In response to the gate timing control signal GDC supplied from the timing driver TCN, the scan driver SDRV supplies a signal SWG to the scan driver SDRV in accordance with the swing width of the gate drive voltage at which the transistors of the subpixels SP included in the panel PNL are operable. And sequentially generates a scan signal while shifting the level of the scan signal. The scan driver SDRV supplies the scan signals generated through the scan lines SL1 to SLm to the subpixels SP included in the panel PNL. As shown in FIG. 2, the scan driver SDRV includes gate drive ICs. Each of the gate drive ICs includes a shift register 61, a level shifter 63, a plurality of AND gates 62 connected between the shift register 61 and the level shifter 63, And an inverter 64 for inverting the gate output enable signal GOE. The shift register 61 shifts the gate start pulse GSP sequentially in accordance with the gate shift clock GSC using a plurality of D flip-flops depending thereon. The AND gates 62 logically multiply the output signal of the shift register 61 and the inverted signal of the gate output enable signal GOE to generate an output. The inverter 64 inverts the gate output enable signal GOE and supplies it to the AND gates 62. The level shifter 63 shifts the output voltage swing width of the AND gate 62 to the swing width of the scan voltage at which the transistors included in the panel PNL are operable. The scan signal output from the level shifter 63 is sequentially supplied to the scan lines SL1 to SLm. On the other hand, the shift register 61 may be formed on the panel (PNL) together with the transistors in the process of manufacturing the transistors included in the panel (PNL). In this case, the level shifter 63 may not be formed on the panel PNL, but may be formed together with the timing driver TCN, or may be formed on a printed circuit board together with the source drive ICs.

The data driver DDRV samples and latches the digital data signal DDATA supplied from the timing driver TCN in response to the data timing control signal DDC supplied from the timing driver TCN, . The data driver DDRV converts the digital data signal DDATA into a gamma reference voltage and converts the digital data signal DDATA into an analog data signal ADATA. The data driver DDRV supplies the data signal ADATA converted through the data lines DL1 to DLn to the subpixels SP included in the panel PNL. As shown in FIG. 3, the data driver DDRV is composed of source drive ICs. Each of the source drive ICs includes a shift register 51, a data register 52, a first latch 53, a second latch 54, a conversion section 55, an output circuit section 56, and the like. The shift register 51 shifts the source sampling clock SSC supplied from the timing driver TCN. The shift register 51 transfers the carry signal CAR to the shift register of the next source drive IC in the neighboring stage. The data register 52 temporarily stores the digital data signal DDATA supplied from the timing driver TCN and supplies it to the first latch 53. The first latch 53 samples and latches the digital data signal DDATA serially inputted according to the clocks sequentially supplied from the shift register 51, and outputs the latched data at the same time. The second latch 54 latches the data supplied from the first latch 53 and simultaneously outputs the latched data in synchronization with the second latch of the other source drive ICs in response to the source output enable signal SOE . The conversion unit 55 maps the digital data signal DDATA and the gamma gradation voltages G1 to Gn input from the second latch 54 and converts them into an analog data signal ADATA. The output circuit portion 56 supplies the analog data signal ADATA to the data lines DL1 to DLn. The output circuit portion 56 drives the output terminal based on the drive voltage DDVDH1 supplied from the power supply circuit portion 140 included in the data driver DDRV.

Hereinafter, the data driver will be described in more detail.

FIG. 4 is a block diagram showing a part of the data driver, FIG. 5 is a view for explaining a period in which a compensation voltage is generated, FIG. 6 is a detailed configuration diagram of the first compensation circuit, 8 is a detailed configuration diagram of the third compensation circuit portion.

1 to 5, the power supply circuit 140 boosts the input voltage VCI to the drive voltage DDVDH1 and supplies the power supply voltage V to the output buffer BUF included in the output circuit 56, And supplies a basic driving voltage DDVDH1 and a current (or electric charge). The power supply circuit 140 may be configured as a charge pump circuit to form the driving voltage DDVDH1 and may be connected to the first capacitor C1 for stabilizing the output stage.

The output buffer BUF included in the output circuit section 56 drives the output stage O based on the driving voltage DDVDH1 supplied from the power supply circuit section 140 and outputs the analog data signal ADATA) through the data line DL. The input terminal I of the output buffer BUF is connected to the conversion section 55 and the ground terminal G of the output buffer BUF is connected to the ground voltage GND and the output terminal BUF O are connected to the data line DL.

The amount of current required by the output buffer BUF included in the output circuit portion 56 of the data driver DDRV is determined by the panel (PNL) PNL) is different from when displaying a specific pattern and displaying ordinary images. That is, the output buffer BUF included in the output circuit section 56 requires a larger current (or charge) to be supplied as the load of the data signal output through the output stage O becomes larger. The driving voltage DDVDH1 output from the power supply circuit portion 140 is supplied to the power supply terminal V of the output buffer BUF included in the output circuit portion 56 via the compensation circuit portion 160. [ The compensation circuit unit 160 outputs a control signal to the compensation circuit unit 160 when the drive voltage DDVDH1 supplied to the power supply stage V of the output buffer BUF included in the output circuit unit 56 fluctuates and the drive voltage DDVDH1 does not reach the target voltage And serves to compensate the potential difference between the voltage and the driving voltage DDVDH1. That is, the compensation circuit unit 160 compensates for the fluctuation range of the driving voltage DDVDH1 so that the data driving unit DDRV can detect the change of the driving voltage DDVDH1 and perform stable driving.

The compensation circuit unit 160 includes a first compensation circuit unit 163, a second compensation circuit unit 165, and a third compensation circuit unit 167. The first compensation circuit portion 163 generates the compensation voltage DDVDH2 based on the drive voltage DDVDH1 and outputs the difference voltages DDVDH2 to DDVDH1 through comparison between the drive voltage DDVDH1 and the compensation voltage DDVDH2. The second compensation circuit unit 165 generates the compensation voltage DDVDH2 corresponding to the target voltage using the difference voltages DDVDH2-DDVDH1 and the drive voltage DDVDH1. The third compensation circuit unit 167 selectively outputs one of the drive voltage DDVDH1 and the compensation voltage DDVDH2 according to the difference voltages DDVDH2 to DDVDH1.

5, the compensating voltage DDVDH2 generated by the compensating circuit unit 160 includes a back porch period (BP period) and a front porch period (FP period) in which the output circuit unit 56 is not driven . The back porch interval (BP interval) and the front porch interval (FP interval) exist in the interval excluding the display interval of one frame (1 frame). Here, the compensation voltage DDVDH2 is formed to have the same potential as the driving voltage DDVDH1.

Hereinafter, the compensation circuit unit 160 will be described in more detail with reference to FIGS. 6 to 8. FIG.

As shown in FIG. 6, the first compensation circuit unit 163 includes a compensation voltage generation unit 163a and a differential voltage generation unit 163b. The compensation voltage generating section 163a includes a switch SW1 for switching driving in a section in which the output circuit section 56 is not driven and a switch SW1 for charging the charge so as to have the same potential as the drive voltage DDVDH1 And a second capacitor C2. The compensation voltage generating unit 163a supplies the driving voltage DDVDH1 and the driving voltage DDVDH1 in such a manner that the driving voltage DDVDH1 output from the power supply circuit unit 140 is charged to the second capacitor C2 during a period in which the output circuit unit 56 is not driven. And generates a compensation voltage DDVDH2 having the same potential.

The differential voltage generation section 163b includes a first terminal - receiving a driving voltage DDVDH1, a second terminal + receiving a compensation voltage DDVDH2, a driving voltage DDVDH1 and a compensation voltage DDVDH2 And a third terminal o for outputting a difference voltage DDVDH2-DDVDH1 through a comparison between the first and second voltages. The first and second resistors R1 and R2 may be connected to the first terminal (-) and the second terminal (+) of the first comparing unit OP1 and the first terminal (-) and the third terminal (o A fourth resistor R4 connected to the ground voltage GND may be connected to the second terminal (+), but not limited thereto.

As shown in Fig. 7, the second compensation circuit portion 165 includes a weighted addition circuit portion 165a and an inversion circuit portion 165b. The weighted addition circuit 165a adds the driving voltage DDVDH1 and the differential voltages DDVDH2 to DDVDH1 to output the output voltage -DVDH2. The weighted addition circuit 165a includes a first terminal - supplied with the driving voltage DDVDH1 and the differential voltages DDVDH2-DDVDH1, a second terminal supplied with the ground voltage GND, And a second comparator OP2 including a third terminal o for outputting an output voltage -DVDH2 by adding the differential voltages DDVDH1 and DDVDH2-DDVDH1. The fifth and sixth resistors R5 and R6 may be connected to the first terminal (-) of the second comparing unit OP2 and the second terminal (+) may be connected to the ground voltage GND, A seventh resistor R7 may be connected between the terminal (-) and the third terminal (o), but is not limited thereto. Here, the output voltage -DVDH2 becomes negative because the difference voltages DDVDH2-DDVDH1 and the driving voltage DDVDH1 input to the weighted addition circuit 165a are "- [(DDVDH2 - DDVDH1) + DDVDH1] Quot; -DVDH2 ", which means that the potential is inverted.

The inversion circuit portion 165b inverts the potential of the output voltage -DVDH2 output through the weighted addition circuit portion 165a. The inversion circuit part 165b includes a first terminal - supplied with the output voltage -DVDH2 output through the weighted addition circuit part 165a, a second terminal supplied with the ground voltage GND, And a third comparator OP3 including a third terminal o for inverting the potential of the voltage -DVDH2 and outputting the compensation voltage DDVDH2. The eighth resistor R8 may be connected to the first terminal (-) of the third comparing unit OP3 and the second terminal (+) may be connected to the ground voltage GND and the first terminal (- The ninth resistor R9 may be connected between the third terminal o, but is not limited thereto. The compensation voltage DDVDH2 output through the inversion circuit part 165b has the same potential as the voltage generated by the compensation voltage generation part 163a and the compensation voltage DDVDH2 finally output through the inversion circuit part 165b Is supplied to the power supply terminal (V) of the output circuit section (56).

As shown in Fig. 8, the third compensation circuit portion 167 includes a selection portion SW2. The selection section SW2 switches and drives one of the drive voltage DDVDH1 and the compensation voltage DDVDH2 according to the difference voltages DDVDH2 to DDVDH1. Here, the difference voltages DDVDH2 to DDVDH1 are used as a selection signal for driving the selector SW2. The selection unit SW2 is switched to drive to output the compensation voltage DDVDH2 if the difference voltage DDVDH2 to DDVDH1 is higher than a specific value Vth. On the other hand, when the difference voltage DDVDH2-DDVDH1 is lower than a specific value, the selection unit SW2 is switched to drive the driving voltage DDVDH1. The selection unit SW2 includes a third capacitor C3 which functions as a stabilization element that minimizes a change in the voltage output from the selection unit SW2 at the moment when the selection unit SW2 is switched to operate.

Hereinafter, the normal drive mode and the compensation drive mode of the data driver according to the embodiment of the present invention will be described.

FIG. 9 is a circuit configuration diagram for explaining the normal drive mode of the data driver, and FIG. 10 is a circuit configuration diagram for explaining the compensation drive mode of the data driver.

[Example of normal drive mode in which panel (PNL) displays general images]

9, the switch SW1 of the compensation voltage generator 163a included in the first compensation circuit portion 163 of the data driver DDRV is in an open (disconnected) state during the normal drive mode operation . Accordingly, the difference voltage DDVDH2-DDVDH1 output from the difference voltage generation unit 163b becomes a specific value or less, and therefore the selection unit SW2 selects the power supply voltage V (V) of the output buffer BUF included in the output circuit unit 56 The driving voltage DDVDH1 is supplied.

[Operation example of the compensation drive mode in which the panel (PNL) displays a specific image]

10, the switch SW1 of the compensation voltage generator 163a included in the first compensation circuit 163 of the data driver DDRV is in the closed state during the compensation drive mode operation. Accordingly, the difference voltage DDVDH2-DDVDH1 output from the difference voltage generation section 163b becomes equal to or higher than a specific value Vth, so that the selection section SW2 selects the power supply of the output buffer BUF included in the output circuit section 56 And supplies the compensation voltage DDVDH2 to the stage (V).

The data driver DDRV can select one of the normal driving mode and the compensating driving mode using the driving voltage DDVDH1 supplied to the output circuit 56 as described above. The selection made at this time is the difference between the compensation voltage DDVDH2 generated when the load of the data driver DDRV is small and the differential voltage DDVDH2-DDVDH1 corresponding to the difference between the driving voltage DDVDH1 generated in the normal driving state Lt; / RTI > That is, the detection of the occurrence of the output fluctuation of the data driver DDRV and the selection of the drive mode are determined by the differential voltages DDVDH2-DDVDH1.

As described above, according to the embodiment of the present invention, it is possible to secure the stable driving of the data driver by compensating the output fluctuation of the driving voltage of the data driver internal circuit, thereby reducing the defective (e.g., crosstalk) There is an effect of providing a display device capable of performing a display operation.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

PNL: panel TCN: timing driver
SDRV: scan driver DDRV: data driver
140: power supply circuit part 56: output circuit part
160: compensation circuit section 163: first compensation circuit section
165: second compensation circuit part 167: third compensation circuit part
DDVDH1: drive voltage DDVDH2: compensation voltage

Claims (11)

panel;
A scan driver for supplying a scan signal to the panel; And
And a compensating circuit for supplying a data signal to the panel and compensating for a potential difference between the target voltage and the driving voltage when the driving voltage supplied to the power supply terminal of the output circuit part does not reach the target voltage,
The data driver may include:
A first compensation circuit for generating a compensation voltage based on the driving voltage and outputting a difference voltage through comparison between the driving voltage and the compensation voltage;
A second compensation circuit for generating the compensation voltage corresponding to the target voltage using the difference voltage and the drive voltage;
And a third compensation circuit part for selectively outputting one of the driving voltage and the compensation voltage according to the difference voltage. delete The method according to claim 1,
Wherein the first compensation circuit unit comprises:
A switch for switching driving in a section in which the output circuit section is not driven,
And a capacitor for charging the charge to have the same potential as the drive voltage by driving the switch. The method according to claim 1,
The section in which the output circuit section is not driven,
A display device including a back porch interval and a front porch interval. The method according to claim 1,
Wherein the first compensation circuit unit comprises:
A first terminal receiving the driving voltage, a second terminal receiving the compensation voltage,
And a third terminal for outputting the difference voltage through comparison between the driving voltage and the compensation voltage. The method according to claim 1,
Wherein the second compensation circuit part comprises:
A weighted addition circuit unit for adding the driving voltage and the difference voltage to output an output voltage,
And an inverting circuit portion for inverting the potential of the output voltage outputted through the weighted addition circuit portion. The method according to claim 6,
Wherein the weighted addition circuit unit comprises:
A second terminal receiving a driving voltage and the difference voltage, a second terminal receiving a ground voltage, and a third terminal including a third terminal for adding the driving voltage and the difference voltage to output an output voltage, A display comprising. The method according to claim 6,
The inversion circuit unit includes:
A second terminal for receiving the ground voltage, and a third terminal for inverting the potential of the output voltage and outputting the compensation voltage, wherein the first terminal receives the output voltage outputted through the weighted addition circuitry, 3 < / RTI > The method according to claim 1,
The third compensation circuit part may include:
And a selection section for switching driving to selectively output one of the driving voltage and the compensation voltage according to the difference voltage,
And the voltage output through the selection unit is supplied to the power supply terminal of the output circuit unit. 10. The method of claim 9,
Wherein the selection unit comprises:
And a stabilization element for stabilizing a voltage output from the selection unit. The method according to claim 1,
The data driver
And an output buffer located in the output circuit portion,
And the driving voltage is supplied to the power supply terminal of the output buffer.

Images