KR101708531B1 - Cap bump structure for reliable wlb(wafer level bonding) and method of manufacture - Google Patents

Cap bump structure for reliable wlb(wafer level bonding) and method of manufacture Download PDF

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KR101708531B1
KR101708531B1 KR1020130099353A KR20130099353A KR101708531B1 KR 101708531 B1 KR101708531 B1 KR 101708531B1 KR 1020130099353 A KR1020130099353 A KR 1020130099353A KR 20130099353 A KR20130099353 A KR 20130099353A KR 101708531 B1 KR101708531 B1 KR 101708531B1
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South Korea
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layer
substrate
microstructure
cap
intermediate layer
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KR1020130099353A
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Korean (ko)
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KR20150021871A (en
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이종성
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주식회사 스탠딩에그
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Abstract

Au-Si eutectic bonding can simplify the microstructure substrate fabrication process, enable vacuum packaging, and have great advantages in electrically connecting the microstructure substrate and the cap substrate. Cu / Ni / Au and Au are mainly used for the bump structure mainly used for the cap substrate. Au-Si eutectic bonding showed that Cu formed a bonding layer that was vulnerable to moisture. It was applied to accelerometer to evaluate reliability (HAST (High Accelerated Stress Test) and PCT (Pressure Cooker Test)). As a result, the phenomenon of yield reduction was confirmed. The present invention fabricates cap substrate bumps using other materials that can replace the Cu material and improves various process problems during this process. Au-Si eutectic bonding of the fabricated cap substrate and the microstructured substrate confirmed that bonding was completely formed on the entire 8-inch wafer. In the reliability evaluation (HAST (High Accelerated Stress Test)), good results without yield reduction were obtained.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a cap wafer bump structure for reliable wafer level bonding and a method of manufacturing the cap wafer bump structure. 2. Description of the Related Art [0002] CAP BUMP STRUCTURE FOR RELIABLE WLB (WAFER LEVEL BONDING) AND METHOD OF MANUFACTURE [

The present invention relates to a cap substrate having a bump structure for Au-Si eutectic bonding, which is one of reliable wafer-level hermetic packaging technologies, and a method of manufacturing the cap substrate, and a microstructure such as a sensor chip or a semiconductor chip is formed The present invention relates to a bump structure and a fabrication method for fabricating a microstructure substrate by bonding to a cap substrate and sealingly mounting the microstructure substrate using other materials that can substitute for a Cu material that reduces reliability due to its vulnerability to moisture.

In recent years, MEMS (Micro Electro Mechanical Systems) technology has been expanding into the field of miniaturization of innovative systems that will lead various technology fields in the mobile and automobile fields. MEMS technology is a technology for forming a specific part of a system on a substrate such as a silicon substrate in a precise shape of micro or nanometer unit by using special silicon technology of only MEMS in various existing technologies of semiconductor.

Most of the devices manufactured using the MEMS technology are sensitive to the external environment such as temperature, humidity, fine dust, vibration and impact, and thus do not perform the operation Or an error occurs frequently during operation. Accordingly, there is a need for wafer-level hermetic packaging that forms a seal-mounted MEMS package by disposing a cap substrate on top of the sensor substrate where the MEMS element is located, thereby shielding the MEMS element from the external environment.

There are various methods for wafer-level hermetic packaging, but Au-Si fusion bonding has various advantages as follows. First, since it is not necessary to further fabricate a layer for bonding to the microstructure substrate, the fabrication process of the microstructure substrate can be simplified. Second, it is applicable to a gyro sensor requiring a vacuum package because various substrates can be used and the sealing property is good. Third, since the microstructure substrate and the cap substrate are electrically connected to each other, it is possible to fabricate a structure capable of power connection through the cap substrate. Fourth, if the signal processing device is integrated on the cap wafer in the future, there are great advantages that the manufacturing cost and the package size can be greatly reduced.

 Although there are various cap substrate structures for Au-Si fusion bonding, the bump forming structure has advantages in commercialization by applying commercially available stabilized devices and techniques. Commonly used bump structures are Cu / Ni / Au and Au, and the structure applicable to MEMS devices is Cu / Ni / Au structure. However, Au-Si eutectic bonding with a cap substrate made of Cu / Ni / Au structure has resulted in a moisture-resistant bonding layer, which leads to reliability evaluation (HAST (High Accelerated Stress Test) and PCT (Pressure Cooker Test)). There is a problem that the performance of the MEMS device is affected and the amount of the positive / negative yield is lowered. The problem of reliability is a serious problem that needs to be solved directly related to product commercialization.

In order to solve the above-described problems, it is an object of the present invention to provide a reliable cap substrate bump structure in which a Cu material is replaced with a reliable material, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a bump structure including: a seed layer replacing a Cu material for bump plating; an Au layer eutectic bonding to a portion of the surface of the microstructure substrate; And an intermediate layer which is electrically connected between the Au layer and the Cu layer to replace the cap substrate with a predetermined interval.
Further, the bump structure according to the present invention includes: a seed layer made of Ni, which is a material replacing Cu for forming an intermediate layer on a cap substrate for sealingly mounting a microstructure substrate; An intermediate layer made of Ni, which is a material replacing Cu, which electrically connects the Au layer and the cap substrate to a part or more of the cap substrate; And an Au layer electrically connected to the intermediate layer and eutectic bonding to a portion of the surface of the microstructured substrate, wherein the intermediate layer has a eutectic temparature between the Au layer and the microstructured substrate, Has a higher melting point, and the Au layer is composed of one of Au, Au / Si, and Au / Ge materials.
A seal-mounted structure according to the present invention comprises: a microstructure substrate on which a microstructure is formed; A cap substrate for sealingly mounting the microstructure substrate; A seed layer and an intermediate layer for electrically connecting at least a part of the bottom surface of the cap substrate to the Au layer; And a Au layer electrically connected to the intermediate layer and eutectic bonded to a portion of the surface of the sensor substrate, wherein the intermediate layer has a melting point higher than an eutectic temperature of the Au layer and the microstructured substrate, The Au layer is made of one of Au, Au / Ge and Au / Si, and the microstructure substrate is made of Si.
In addition, the micro-device substrate includes a micro-device requiring wafer-level hermetic packaging.
In addition, there is no Cu component that may impair reliability in the interfaces and bumps of the cap substrate and the fine element substrate.

A method of manufacturing a bump structure according to an embodiment of the present invention includes: forming a seed layer replacing a Cu material on a cap substrate for sealingly mounting a microstructure substrate; Forming a pattern with a photosensitive material on at least a portion of the seed layer and replacing the Cu material with an intermediate layer; Forming an Au layer for eutectic bonding with the microstructure substrate; Removing the photoresist film and removing the seed material; And eutectic bonding the Au layer for eutectic bonding with the microstructure substrate.
According to another aspect of the present invention, there is provided a method of manufacturing a cap substrate bump structure, including: forming a Ni seed layer on the entire surface of a cap substrate for sealingly mounting a microstructured substrate; Forming a Ni intermediate layer in part on the seed layer, the Ni intermediate layer being electrically connected to the Au layer; Forming an Au layer on the intermediate layer for eutectic bonding with the microstructure substrate; Removing a seed layer in a region other than the bump formed region; Wherein the Au layer is made of gold (Au), Au / Ge, or Au / Si, and the intermediate layer is formed by bonding the Au layer and the microstructure substrate Ti, Cr, V, and Al as a plating layer having a melting point higher than the eutectic melting point of the eutectic mixture and having a good bonding strength with the seed layer and the Au layer, or two or more layers.
The eutectic bonding step may include pressing / heating the substrate at a preset pressure and temperature for close contact between the microstructured substrate and the Au layer.
Further, before forming the Au layer, the method further includes forming a silicon layer on the microstructured substrate.
In addition, when the undercut is seriously generated in the step of removing the seed layer in the region where the bump is formed, a step of protecting the bump region with the photoresist film is added to minimize the undercut and enable the over etching for the sufficient seed layer . ≪ / RTI >

The bump structure according to the present invention can be stably manufactured by the devices and techniques set up for commercialization in the past. Au-Si eutectic bonding was performed on the cap substrate and the microstructure substrate, Was formed without any problems. In addition, the product can be manufactured by obtaining a good result without yield reduction even in a reliability evaluation (HAST (High Accelerated Stress Test)).

1 is a cross-sectional view of a conventional microstructure substrate and a cap substrate structure.
2 is a cross-sectional view after eutectic bonding of the structure shown in FIG.
3 is a cross-sectional view after proceeding to a reliability evaluation (HAST (High Accelerated Stress Test)) on the structure shown in FIG.
4 is a cross-sectional view showing a structure in which a seed material is replaced with a material 20 capable of replacing Cu in a conventional bump structure.
5 is a cross-sectional view showing a structure in which a bump structure capable of replacing Cu is formed at a desired position on a seed material.
6 is a cross-sectional view showing a structure when an undercut is severely generated in a bump in a process of removing a seed material in a region where bumps are not formed.
7 is a sectional view showing a structure for preventing the undercut of the intermediate layer by adding a step of protecting the bump to the photoresist film 22 to solve the undercut problem as shown in Fig.
FIG. 8 is a cross-sectional view of a cap substrate prepared by applying a material substituting Cu for the seed layer and the intermediate layer in FIG. 1, and a structure immediately before sealing the microstructure substrate. FIG.
Fig. 9 is a cross-sectional view showing eutectic bonding of the structure shown in Fig. 8;

Prior to the description of the concrete contents of the present invention, for the sake of understanding, the outline of the solution of the problem to be solved by the present invention or the core of the technical idea is first given.

The cap substrate bump structure according to an embodiment of the present invention includes a seed layer composed of a material substituting Cu for forming an intermediate layer on a cap substrate for sealingly mounting a microstructure substrate; An intermediate layer composed of a material replacing Cu which electrically connects the Au layer and the cap substrate to at least a part of the cap substrate; And an Au layer electrically connected to the intermediate layer and eutectic bonding to a portion of the surface of the microstructure substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art, however, that these examples are provided to further illustrate the present invention, and the scope of the present invention is not limited thereto.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which: It is to be noted that components are denoted by the same reference numerals even though they are shown in different drawings, and components of different drawings can be cited when necessary in describing the drawings. In the following detailed description of the principles of operation of the preferred embodiments of the present invention, the description of well-known functions or constructions related to the present invention will be omitted, and it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention. , Detailed description thereof will be omitted.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprises " or "comprising" when used herein should be interpreted as excluding the presence or addition of one or more other elements, steps, operations, or elements in addition to the stated element, step, I never do that.

1 is a cross-sectional view showing a structure of a microstructure substrate and a cap substrate immediately before sealing mounting using a conventional bump structure structure. As shown, the microstructured substrate 12 is located below the structure. The microstructure substrate 12 is composed of a silicon (Si) or an SOI (Si on Insulator) wafer depending on the manufacturing method and the type of device. The cap substrate 11 is placed on the microstructure substrate 12 and the cap substrate 11 is covered and mounted on the microstructure substrate 12 as a cover. The cap substrate 11 may be preceded by a wiring process for electrical input / output. The bumps were fabricated by plating Cu (14), Ni (15) and Au (16) in the order of Cu / Ni / Au seeds. Through eutectic bonding, wafer- level hermetic packaging and two substrates And serves as an electrical connection.

FIG. 2 is a cross-sectional view showing a cross-sectional state of the microstructure substrate 12 and the cap substrate 11 after the eutectic bonding of the structure shown in FIG. 1 is completed. The eutectic bonding process includes: a first step in which the eutectic reaction is generated and enlarged in the Au layer 16 and the surface 13 of the microstructure substrate; Second, the liquid phase formed by the eutectic reaction flows to the Ni (15) and Cu (14) along the microstructured substrate surface (13) and the bump side; Third, a part of Cu is diffused into a liquid phase formed by a eutectic reaction; Fourth, the step of forming the Cu material 18 on the interface between the microstructure substrate surface 13 and the eutectic solid phase 17 in the process of phase transformation of the liquid phase formed by the eutectic reaction into the solid phase 17 can be categorized.

3 is a cross-sectional view showing the cross-sectional state of the microstructure substrate 12 and the cap substrate 11 after conducting a reliability evaluation (HAST (High Accelerated Stress Test)) on the structure shown in FIG. As shown, the Cu material 18 formed on the interface between the microstructure substrate surface 13 and the eutectic solid phase 17 is oxidized and removed by the high temperature moisture to form the microstructure substrate surface 13 and the eutectic solid phase 17 ) Is lowered. In addition, moisture penetrates into the microstructure due to penetration of moisture through the removed space of the Cu material (18), resulting in deterioration in the performance of the microstructure such as a MEMS do. In addition, there arises a problem that the resistance increases in terms of electrical connection.

FIG. 4 is a cross-sectional view showing a structure in which a bump structure capable of replacing Cu in a conventional bump structure vulnerable to moisture is replaced with a material 20 capable of replacing Cu, as a seed material. The seed material 20 is a material which is easy to form and bond to the cap substrate 11 and can be easily removed and has no problem of impairing reliability due to reaction with the eutectic liquid phase. Typically, there is Ni. In addition to Ni, there may be a variety of materials that can replace Cu.

5 is a cross-sectional view showing a structure in which a bump structure capable of replacing Cu is formed at a desired position on the seed material. The bumps are composed of an Au layer 16, an intermediate layer 21 for electrically connecting the Au layer 16 and the seed material 20. The intermediate layer can be formed as a single layer or a multilayer, and various materials capable of substituting for Cu can be used. Typically, Ni is used.

6 is a cross-sectional view showing a structure when an undercut is severely generated in a bump in a process of removing a seed material in a region where no bump is formed. In the case of a material in which the seed material is less easily removed than Cu, the undercut has a severe structure as the line width of the intermediate layer 21 is greatly reduced. The structure with severe undercut has serious drawbacks such as lowering the quality of the eutectic bonding, lowering the yield and the yield, increasing the size of the product as the line width of the bump increases in terms of design, and increasing the manufacturing cost.

7 is a cross-sectional view showing a structure for preventing the undercut of the intermediate layer by adding a step of protecting the bump to the photoresist film 22 to solve the undercut problem as shown in FIG.

FIG. 8 is a cross-sectional view of a cap substrate formed by applying a material substituting Cu for the seed layer and the intermediate layer in FIG. 1 and a structure immediately before sealing the microstructure substrate. Compared with Fig. 1, there is no difference other than the change of material, so it is possible to proceed to the same design and process.

9 is a cross-sectional view showing the cross-sectional state of the microstructure substrate 12 and the cap substrate 11 after the eutectic bonding of the structure shown in FIG. 8 is completed. The eutectic bonding process includes: a first step in which the eutectic reaction is generated and enlarged in the Au layer 16 and the surface 13 of the microstructure substrate; Second, the liquid phase formed by the eutectic reaction flows along the side surfaces of the fine structure substrate surface 13 and the intermediate layer 15; Third, the liquid phase formed by the eutectic reaction is phase-transformed into the solid phase 23. The phenomenon of diffusion into the Cu material liquid phase and formation on the interface between the microstructure substrate surface 13 and the eutectic solid phase 17 disappeared.

As a result of conducting a reliability evaluation (HAST (High Accelerated Stress Test)) on the structure shown in FIG. 9, it was confirmed that there was no change in the yield.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and specific embodiments and drawings. However, it should be understood that the present invention is not limited to the above- And various modifications and changes may be made thereto by those skilled in the art to which the present invention pertains.

Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (14)

A seed layer made of Ni which is a material replacing Cu for forming an intermediate layer on a cap substrate for sealingly mounting a microstructure substrate;
An intermediate layer made of Ni, which is a material replacing Cu, which electrically connects the Au layer and the cap substrate to a part or more of the cap substrate;
And an Au layer electrically connected to the intermediate layer and eutectic bonding to a portion of the surface of the microstructure substrate,
Wherein the intermediate layer has a melting point higher than the eutectic temperature of the Au layer and the microstructure substrate,
Wherein the Au layer comprises one of Au, Au / Si, and Au / Ge.
delete delete A microstructure substrate on which a microstructure is formed on a surface;
A cap substrate for sealingly mounting the microstructure substrate;
A seed layer and an intermediate layer for electrically connecting at least a part of the bottom surface of the cap substrate to the Au layer;
And an Au layer electrically connected to the intermediate layer and eutectic bonding to a portion of the surface of the microstructure substrate,
Wherein the intermediate layer has a melting point higher than the eutectic temperature of the Au layer and the microstructure substrate,
Wherein the Au layer is made of one of Au, Au / Ge, and Au / Si, and the microstructure substrate is made of Si.
delete delete 5. The method of claim 4,
Wherein the microstructured substrate comprises a micro-device requiring wafer-level hermetic packaging. ≪ RTI ID = 0.0 > 18. < / RTI >
5. The method of claim 4,
Wherein a Cu component that can impair reliability is not present in the interfaces and bumps of the cap substrate and the microstructure substrate.
Forming a Ni seed layer that can replace Cu on the entire surface of the cap substrate for sealingly mounting the microstructure substrate;
Forming a Ni intermediate layer in part on the seed layer, the Ni intermediate layer being electrically connected to the Au layer;
Forming an Au layer on the intermediate layer for eutectic bonding with the microstructure substrate;
Removing a seed layer in a region other than the region where the bump is formed;
Eutectic bonding the Au layer and the microstructure substrate,
The Au layer may be made of gold (Au), Au / Ge, or Au / Si,
The intermediate layer is a single layer or two or more layers of a plating material having a melting point higher than the eutectic temperature of the Au layer and the microstructure substrate and having a good bonding strength to the seed layer and the Au layer, ≪ / RTI > wherein the cap substrate comprises at least one selected material.
10. The method of claim 9,
Wherein the eutectic bonding comprises:
And pressing / heating the microstructure substrate at a preset pressure and temperature for close contact between the microstructured substrate and the Au layer.
10. The method of claim 9,
Before the step of forming the Au layer,
And forming a silicon layer on the microstructured substrate. ≪ RTI ID = 0.0 > 11. < / RTI >
delete delete 10. The method of claim 9,
And a step of protecting the bump region with the photoresist film when the undercut is severely generated in the step of removing the seed layer in the region where the bump is formed is further added so that the undercut is minimized and over etching of the sufficient seed layer is enabled felled ≪ / RTI >
KR1020130099353A 2013-08-21 2013-08-21 Cap bump structure for reliable wlb(wafer level bonding) and method of manufacture KR101708531B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100661350B1 (en) 2004-12-27 2006-12-27 삼성전자주식회사 Mems devices package and method for manufacturing thereof
KR100846569B1 (en) * 2006-06-14 2008-07-15 매그나칩 반도체 유한회사 Package of mems device and method for manufacturing the same
JP2012023226A (en) 2010-07-15 2012-02-02 Renesas Electronics Corp Method of manufacturing electronic component

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100661350B1 (en) 2004-12-27 2006-12-27 삼성전자주식회사 Mems devices package and method for manufacturing thereof
KR100846569B1 (en) * 2006-06-14 2008-07-15 매그나칩 반도체 유한회사 Package of mems device and method for manufacturing the same
JP2012023226A (en) 2010-07-15 2012-02-02 Renesas Electronics Corp Method of manufacturing electronic component

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