KR101707289B1 - 그래픽 병렬 처리 유닛에 대한 버퍼 관리 - Google Patents
그래픽 병렬 처리 유닛에 대한 버퍼 관리 Download PDFInfo
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- KR101707289B1 KR101707289B1 KR1020147023719A KR20147023719A KR101707289B1 KR 101707289 B1 KR101707289 B1 KR 101707289B1 KR 1020147023719 A KR1020147023719 A KR 1020147023719A KR 20147023719 A KR20147023719 A KR 20147023719A KR 101707289 B1 KR101707289 B1 KR 101707289B1
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G5/00—Devices in which the computing operation is performed by means of fluid-pressure elements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/10—Display system comprising arrangements, such as a coprocessor, specific for motion video images
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/121—Frame memory handling using a cache memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Computer Graphics (AREA)
- Mathematical Physics (AREA)
- Image Generation (AREA)
- Advance Control (AREA)
- Image Processing (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261591733P | 2012-01-27 | 2012-01-27 | |
| US61/591,733 | 2012-01-27 | ||
| US13/747,947 US9256915B2 (en) | 2012-01-27 | 2013-01-23 | Graphics processing unit buffer management |
| US13/747,947 | 2013-01-23 | ||
| PCT/US2013/022900 WO2013112692A1 (en) | 2012-01-27 | 2013-01-24 | Buffer management for graphics parallel processing unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20140125821A KR20140125821A (ko) | 2014-10-29 |
| KR101707289B1 true KR101707289B1 (ko) | 2017-02-27 |
Family
ID=48869818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020147023719A Active KR101707289B1 (ko) | 2012-01-27 | 2013-01-24 | 그래픽 병렬 처리 유닛에 대한 버퍼 관리 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9256915B2 (enExample) |
| EP (1) | EP2807646A1 (enExample) |
| JP (1) | JP6081492B2 (enExample) |
| KR (1) | KR101707289B1 (enExample) |
| CN (1) | CN104081449B (enExample) |
| BR (1) | BR112014018434B1 (enExample) |
| WO (1) | WO2013112692A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022022937A1 (en) | 2020-07-31 | 2022-02-03 | Morphotonics Holding B.V. | Assembly for replicating flexible stamps from a master |
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| US10134102B2 (en) * | 2013-06-10 | 2018-11-20 | Sony Interactive Entertainment Inc. | Graphics processing hardware for using compute shaders as front end for vertex shaders |
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| US10515430B2 (en) | 2015-11-03 | 2019-12-24 | International Business Machines Corporation | Allocating device buffer on GPGPU for an object with metadata using access boundary alignment |
| CN105447810B (zh) * | 2015-11-17 | 2018-08-24 | 上海兆芯集成电路有限公司 | 数据单元的关联性检查方法以及使用该方法的装置 |
| CN105446939B (zh) * | 2015-12-04 | 2019-02-26 | 上海兆芯集成电路有限公司 | 由装置端推核心入队列的装置 |
| US10025741B2 (en) * | 2016-01-13 | 2018-07-17 | Samsung Electronics Co., Ltd. | System-on-chip, mobile terminal, and method for operating the system-on-chip |
| US9799089B1 (en) * | 2016-05-23 | 2017-10-24 | Qualcomm Incorporated | Per-shader preamble for graphics processing |
| WO2017209876A1 (en) * | 2016-05-31 | 2017-12-07 | Brocade Communications Systems, Inc. | Buffer manager |
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| US20180122037A1 (en) * | 2016-10-31 | 2018-05-03 | Intel Corporation | Offloading fused kernel execution to a graphics processor |
| JP6817827B2 (ja) * | 2017-01-23 | 2021-01-20 | Necプラットフォームズ株式会社 | アクセラレータ処理管理装置、ホスト装置、アクセラレータ処理実行システム、方法およびプログラム |
| US10430919B2 (en) * | 2017-05-12 | 2019-10-01 | Google Llc | Determination of per line buffer unit memory allocation |
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| CN112104731B (zh) * | 2020-09-11 | 2022-05-20 | 北京奇艺世纪科技有限公司 | 请求处理方法、装置、电子设备和存储介质 |
| US11989554B2 (en) * | 2020-12-23 | 2024-05-21 | Intel Corporation | Processing pipeline with zero loop overhead |
| CN113457160B (zh) * | 2021-07-15 | 2024-02-09 | 腾讯科技(深圳)有限公司 | 数据处理方法、装置、电子设备及计算机可读存储介质 |
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| CN116048816B (zh) * | 2023-03-23 | 2023-08-22 | 摩尔线程智能科技(北京)有限责任公司 | 数据请求处理方法、装置、电子设备和存储介质 |
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| JP2007122537A (ja) | 2005-10-31 | 2007-05-17 | Sony Computer Entertainment Inc | 描画処理装置、並列処理装置および排他制御方法 |
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-
2013
- 2013-01-23 US US13/747,947 patent/US9256915B2/en active Active
- 2013-01-24 BR BR112014018434-8A patent/BR112014018434B1/pt active IP Right Grant
- 2013-01-24 KR KR1020147023719A patent/KR101707289B1/ko active Active
- 2013-01-24 EP EP13704848.4A patent/EP2807646A1/en not_active Ceased
- 2013-01-24 CN CN201380006620.XA patent/CN104081449B/zh active Active
- 2013-01-24 WO PCT/US2013/022900 patent/WO2013112692A1/en not_active Ceased
- 2013-01-24 JP JP2014554817A patent/JP6081492B2/ja active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040160446A1 (en) | 2003-02-18 | 2004-08-19 | Gosalia Anuj B. | Multithreaded kernel for graphics processing unit |
| JP2007122537A (ja) | 2005-10-31 | 2007-05-17 | Sony Computer Entertainment Inc | 描画処理装置、並列処理装置および排他制御方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022022937A1 (en) | 2020-07-31 | 2022-02-03 | Morphotonics Holding B.V. | Assembly for replicating flexible stamps from a master |
Also Published As
| Publication number | Publication date |
|---|---|
| BR112014018434B1 (pt) | 2021-07-27 |
| BR112014018434A8 (pt) | 2017-07-11 |
| WO2013112692A1 (en) | 2013-08-01 |
| US9256915B2 (en) | 2016-02-09 |
| JP6081492B2 (ja) | 2017-02-15 |
| KR20140125821A (ko) | 2014-10-29 |
| CN104081449B (zh) | 2016-11-09 |
| EP2807646A1 (en) | 2014-12-03 |
| BR112014018434A2 (pt) | 2017-06-20 |
| JP2015513715A (ja) | 2015-05-14 |
| CN104081449A (zh) | 2014-10-01 |
| US20130194286A1 (en) | 2013-08-01 |
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