JP6081492B2 - グラフィックス並列処理ユニットに関するバッファ管理 - Google Patents
グラフィックス並列処理ユニットに関するバッファ管理 Download PDFInfo
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- JP6081492B2 JP6081492B2 JP2014554817A JP2014554817A JP6081492B2 JP 6081492 B2 JP6081492 B2 JP 6081492B2 JP 2014554817 A JP2014554817 A JP 2014554817A JP 2014554817 A JP2014554817 A JP 2014554817A JP 6081492 B2 JP6081492 B2 JP 6081492B2
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G5/00—Devices in which the computing operation is performed by means of fluid-pressure elements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/10—Display system comprising arrangements, such as a coprocessor, specific for motion video images
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/121—Frame memory handling using a cache memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Computer Graphics (AREA)
- Mathematical Physics (AREA)
- Image Generation (AREA)
- Advance Control (AREA)
- Image Processing (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261591733P | 2012-01-27 | 2012-01-27 | |
| US61/591,733 | 2012-01-27 | ||
| US13/747,947 US9256915B2 (en) | 2012-01-27 | 2013-01-23 | Graphics processing unit buffer management |
| US13/747,947 | 2013-01-23 | ||
| PCT/US2013/022900 WO2013112692A1 (en) | 2012-01-27 | 2013-01-24 | Buffer management for graphics parallel processing unit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015513715A JP2015513715A (ja) | 2015-05-14 |
| JP2015513715A5 JP2015513715A5 (enExample) | 2016-05-26 |
| JP6081492B2 true JP6081492B2 (ja) | 2017-02-15 |
Family
ID=48869818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014554817A Active JP6081492B2 (ja) | 2012-01-27 | 2013-01-24 | グラフィックス並列処理ユニットに関するバッファ管理 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9256915B2 (enExample) |
| EP (1) | EP2807646A1 (enExample) |
| JP (1) | JP6081492B2 (enExample) |
| KR (1) | KR101707289B1 (enExample) |
| CN (1) | CN104081449B (enExample) |
| BR (1) | BR112014018434B1 (enExample) |
| WO (1) | WO2013112692A1 (enExample) |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10817043B2 (en) * | 2011-07-26 | 2020-10-27 | Nvidia Corporation | System and method for entering and exiting sleep mode in a graphics subsystem |
| US9304730B2 (en) | 2012-08-23 | 2016-04-05 | Microsoft Technology Licensing, Llc | Direct communication between GPU and FPGA components |
| CN103810124A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 用于数据传输的系统及方法 |
| US9977683B2 (en) * | 2012-12-14 | 2018-05-22 | Facebook, Inc. | De-coupling user interface software object input from output |
| US10176621B2 (en) * | 2013-06-10 | 2019-01-08 | Sony Interactive Entertainment Inc. | Using compute shaders as front end for vertex shaders |
| US10096079B2 (en) | 2013-06-10 | 2018-10-09 | Sony Interactive Entertainment Inc. | Fragment shaders perform vertex shader computations |
| US10102603B2 (en) | 2013-06-10 | 2018-10-16 | Sony Interactive Entertainment Inc. | Scheme for compressing vertex shader output parameters |
| US10134102B2 (en) * | 2013-06-10 | 2018-11-20 | Sony Interactive Entertainment Inc. | Graphics processing hardware for using compute shaders as front end for vertex shaders |
| US9659399B2 (en) * | 2013-08-23 | 2017-05-23 | Nvidia Corporation | System, method, and computer program product for passing attribute structures between shader stages in a graphics pipeline |
| WO2015074239A1 (en) * | 2013-11-22 | 2015-05-28 | Intel Corporation | Method and apparatus to improve performance of chained tasks on a graphics processing unit |
| US9589311B2 (en) * | 2013-12-18 | 2017-03-07 | Intel Corporation | Independent thread saturation of graphics processing units |
| US9679347B2 (en) * | 2014-02-18 | 2017-06-13 | Qualcomm Incorporated | Shader pipeline with shared data channels |
| US10055342B2 (en) * | 2014-03-19 | 2018-08-21 | Qualcomm Incorporated | Hardware-based atomic operations for supporting inter-task communication |
| US9710245B2 (en) * | 2014-04-04 | 2017-07-18 | Qualcomm Incorporated | Memory reference metadata for compiler optimization |
| KR102263326B1 (ko) | 2014-09-18 | 2021-06-09 | 삼성전자주식회사 | 그래픽 프로세싱 유닛 및 이를 이용한 그래픽 데이터 처리 방법 |
| GB2524346B (en) * | 2014-09-19 | 2016-12-21 | Imagination Tech Ltd | Separating Cores |
| US9412147B2 (en) | 2014-09-23 | 2016-08-09 | Apple Inc. | Display pipe line buffer sharing |
| US9659407B2 (en) * | 2015-01-26 | 2017-05-23 | MediaTek Singapore, Pte. Lte. | Preemptive flushing of spatial selective bins for deferred graphics processing |
| US9652817B2 (en) | 2015-03-12 | 2017-05-16 | Samsung Electronics Co., Ltd. | Automated compute kernel fusion, resizing, and interleave |
| CN104899039B (zh) | 2015-06-12 | 2018-12-25 | 百度在线网络技术(北京)有限公司 | 用于在终端设备上提供截屏服务的方法和装置 |
| US10515430B2 (en) | 2015-11-03 | 2019-12-24 | International Business Machines Corporation | Allocating device buffer on GPGPU for an object with metadata using access boundary alignment |
| CN105447810B (zh) * | 2015-11-17 | 2018-08-24 | 上海兆芯集成电路有限公司 | 数据单元的关联性检查方法以及使用该方法的装置 |
| CN105446939B (zh) * | 2015-12-04 | 2019-02-26 | 上海兆芯集成电路有限公司 | 由装置端推核心入队列的装置 |
| US10025741B2 (en) * | 2016-01-13 | 2018-07-17 | Samsung Electronics Co., Ltd. | System-on-chip, mobile terminal, and method for operating the system-on-chip |
| US9799089B1 (en) * | 2016-05-23 | 2017-10-24 | Qualcomm Incorporated | Per-shader preamble for graphics processing |
| WO2017209876A1 (en) * | 2016-05-31 | 2017-12-07 | Brocade Communications Systems, Inc. | Buffer manager |
| US10572399B2 (en) * | 2016-07-13 | 2020-02-25 | Qualcomm Incorporated | Memory request arbitration |
| US20180122037A1 (en) * | 2016-10-31 | 2018-05-03 | Intel Corporation | Offloading fused kernel execution to a graphics processor |
| JP6817827B2 (ja) * | 2017-01-23 | 2021-01-20 | Necプラットフォームズ株式会社 | アクセラレータ処理管理装置、ホスト装置、アクセラレータ処理実行システム、方法およびプログラム |
| US10430919B2 (en) * | 2017-05-12 | 2019-10-01 | Google Llc | Determination of per line buffer unit memory allocation |
| US11163546B2 (en) * | 2017-11-07 | 2021-11-02 | Intel Corporation | Method and apparatus for supporting programmatic control of a compiler for generating high-performance spatial hardware |
| US11068308B2 (en) * | 2018-03-14 | 2021-07-20 | Texas Instruments Incorporated | Thread scheduling for multithreaded data processing environments |
| US10810064B2 (en) * | 2018-04-27 | 2020-10-20 | Nasdaq Technology Ab | Publish-subscribe framework for application execution |
| US11397694B2 (en) | 2019-09-17 | 2022-07-26 | Micron Technology, Inc. | Memory chip connecting a system on a chip and an accelerator chip |
| US11163490B2 (en) * | 2019-09-17 | 2021-11-02 | Micron Technology, Inc. | Programmable engine for data movement |
| US11416422B2 (en) | 2019-09-17 | 2022-08-16 | Micron Technology, Inc. | Memory chip having an integrated data mover |
| CN111078395B (zh) * | 2019-11-12 | 2023-06-20 | 华中科技大学 | 一种基于张量的深度学习gpu内存管理优化方法及系统 |
| US11263064B2 (en) * | 2019-12-30 | 2022-03-01 | Qualcomm Incorporated | Methods and apparatus to facilitate improving processing of machine learning primitives |
| US11250538B2 (en) | 2020-03-09 | 2022-02-15 | Apple Inc. | Completion signaling techniques in distributed processor |
| US11416961B2 (en) | 2020-05-29 | 2022-08-16 | Samsung Electronics Co., Ltd. | Variable entry transitional ring storage for efficiently accessing graphics states |
| WO2022022937A1 (en) | 2020-07-31 | 2022-02-03 | Morphotonics Holding B.V. | Assembly for replicating flexible stamps from a master |
| CN112104731B (zh) * | 2020-09-11 | 2022-05-20 | 北京奇艺世纪科技有限公司 | 请求处理方法、装置、电子设备和存储介质 |
| US11989554B2 (en) * | 2020-12-23 | 2024-05-21 | Intel Corporation | Processing pipeline with zero loop overhead |
| CN113457160B (zh) * | 2021-07-15 | 2024-02-09 | 腾讯科技(深圳)有限公司 | 数据处理方法、装置、电子设备及计算机可读存储介质 |
| US20220391248A1 (en) * | 2022-08-12 | 2022-12-08 | Prashant Chaudhari | Monitoring Apparatus, Device, Method, and Computer Program and Corresponding System |
| US12361628B2 (en) * | 2022-12-08 | 2025-07-15 | Advanced Micro Devices, Inc. | Configurable multiple-die graphics processing unit |
| CN115599574B (zh) * | 2022-12-12 | 2023-03-24 | 北京象帝先计算技术有限公司 | 图形处理系统、电子组件、电子设备及信息处理方法 |
| CN116048816B (zh) * | 2023-03-23 | 2023-08-22 | 摩尔线程智能科技(北京)有限责任公司 | 数据请求处理方法、装置、电子设备和存储介质 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2500101B2 (ja) | 1992-12-18 | 1996-05-29 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 共用変数の値を更新する方法 |
| US7117481B1 (en) | 2002-11-06 | 2006-10-03 | Vmware, Inc. | Composite lock for computer systems with multiple domains |
| US7673304B2 (en) * | 2003-02-18 | 2010-03-02 | Microsoft Corporation | Multithreaded kernel for graphics processing unit |
| TWI322354B (en) * | 2005-10-18 | 2010-03-21 | Via Tech Inc | Method and system for deferred command issuing in a computer system |
| JP3853829B1 (ja) * | 2005-10-31 | 2006-12-06 | 株式会社ソニー・コンピュータエンタテインメント | 描画処理装置、並列処理装置および排他制御方法 |
| US7928990B2 (en) | 2006-09-27 | 2011-04-19 | Qualcomm Incorporated | Graphics processing unit with unified vertex cache and shader register file |
| US8087029B1 (en) | 2006-10-23 | 2011-12-27 | Nvidia Corporation | Thread-type-based load balancing in a multithreaded processor |
| US8135926B1 (en) | 2008-10-21 | 2012-03-13 | Nvidia Corporation | Cache-based control of atomic operations in conjunction with an external ALU block |
| US8392925B2 (en) | 2009-03-26 | 2013-03-05 | Apple Inc. | Synchronization mechanisms based on counters |
| JP2010287110A (ja) * | 2009-06-12 | 2010-12-24 | Nec Personal Products Co Ltd | 情報処理装置、情報処理方法、プログラム及び記録媒体 |
| DK2460072T3 (en) | 2009-07-28 | 2019-03-25 | Ericsson Telefon Ab L M | Device and method for handling incidents in a telecommunications network |
| US9245371B2 (en) | 2009-09-11 | 2016-01-26 | Nvidia Corporation | Global stores and atomic operations |
| US8817031B2 (en) * | 2009-10-02 | 2014-08-26 | Nvidia Corporation | Distributed stream output in a parallel processing unit |
| US8810592B2 (en) * | 2009-10-09 | 2014-08-19 | Nvidia Corporation | Vertex attribute buffer for inline immediate attributes and constants |
| KR20130141446A (ko) * | 2010-07-19 | 2013-12-26 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | 복수의 프로세싱 유닛들에서 온-칩 메모리를 사용하는 데이터 프로세싱 |
| US20120092351A1 (en) | 2010-10-19 | 2012-04-19 | Apple Inc. | Facilitating atomic switching of graphics-processing units |
| US9092267B2 (en) | 2011-06-20 | 2015-07-28 | Qualcomm Incorporated | Memory sharing in graphics processing unit |
-
2013
- 2013-01-23 US US13/747,947 patent/US9256915B2/en active Active
- 2013-01-24 BR BR112014018434-8A patent/BR112014018434B1/pt active IP Right Grant
- 2013-01-24 KR KR1020147023719A patent/KR101707289B1/ko active Active
- 2013-01-24 EP EP13704848.4A patent/EP2807646A1/en not_active Ceased
- 2013-01-24 CN CN201380006620.XA patent/CN104081449B/zh active Active
- 2013-01-24 WO PCT/US2013/022900 patent/WO2013112692A1/en not_active Ceased
- 2013-01-24 JP JP2014554817A patent/JP6081492B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| BR112014018434B1 (pt) | 2021-07-27 |
| BR112014018434A8 (pt) | 2017-07-11 |
| WO2013112692A1 (en) | 2013-08-01 |
| US9256915B2 (en) | 2016-02-09 |
| KR20140125821A (ko) | 2014-10-29 |
| CN104081449B (zh) | 2016-11-09 |
| KR101707289B1 (ko) | 2017-02-27 |
| EP2807646A1 (en) | 2014-12-03 |
| BR112014018434A2 (pt) | 2017-06-20 |
| JP2015513715A (ja) | 2015-05-14 |
| CN104081449A (zh) | 2014-10-01 |
| US20130194286A1 (en) | 2013-08-01 |
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