KR101699297B1 - Method for manufacturing solar cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a solar cell. A method of manufacturing a solar cell includes the steps of forming a first impurity film containing a first impurity on a first surface of a substrate, partially applying a first etching paste on the first impurity film, Etching the first impurity film and exposing a portion of the substrate present under the etched first impurity film to form a plurality of first impurity regions; Forming a second impurity film containing a second impurity on the second impurity film by partially applying a second etching paste on the second impurity film to etch the second impurity film in contact with the second etching paste, Forming a plurality of first impurity portions and a plurality of second impurity portions spaced apart from the first impurity portions of the plurality of first impurity regions, And forming a plurality of first electrodes and a plurality of second electrodes. As a result, a plurality of first impurity portions and a plurality of second impurity portions are formed by using the etching paste, so that the manufacturing process of the solar cell is easy and the process time is shortened.

Description

[0001] METHOD FOR MANUFACTURING SOLAR CELL [0002]

The present invention relates to a method of manufacturing a solar cell

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

Typical solar cells have a semiconductor portion that forms a p-n junction by different conductive types, such as p-type and n-type, and electrodes connected to semiconductor portions of different conductivity types, respectively.

When light is incident on such a solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes which are charged by the photovoltaic effect, The electrons move toward the semiconductor portion and the holes move toward the p-type semiconductor portion. The transferred electrons and holes are collected by the different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and the electrodes are connected by a wire to obtain electric power.

The technical problem to be solved by the present invention is to facilitate manufacture of a solar cell.

Another technical problem to be solved by the present invention is to shorten the manufacturing time of the solar cell.

According to an aspect of the present invention, there is provided a method of manufacturing a solar cell, comprising: forming a first impurity layer containing a first impurity on a first surface of a substrate; forming a first etching paste on the first impurity layer, Etching the first impurity film in contact with the first etching paste and exposing a part of the substrate existing under the etched first impurity film to form a plurality of first impurity portions; Forming a second impurity film containing a second impurity on the first impurity region and on the exposed portion of the substrate, partially applying a second etching paste on the second impurity film, Forming a plurality of second impurity regions spaced apart from the plurality of first impurity regions by etching the second impurity film having a plurality of first impurity regions, And a plurality of forming a first electrode and a plurality of second electrodes disposed on a plurality of second impurity part.

It is preferable that the first impurity has a p-type conductivity type and the second impurity has an n-type conductivity type.

The second etching paste may contain an alkali-based material.

The alkali-based material may contain potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), or ethylene diamine pyrocatechol (EDP).

The substrate may contain an n-type impurity.

The method may further include forming a first protective film on the first surface of the substrate before forming the first impurity film, wherein the first impurity film is formed on the first protective film Wherein the first impurity part forming step etches the first protective film located under the first impurity part etched by the first etching paste with the first etching paste to form the plurality of first And forming a plurality of first protective portions present under the impurity portion.

The method of manufacturing a solar cell according to the above feature may further include forming a second protective film on the second surface of the substrate facing the first surface of the substrate.

The first passivation layer and the second passivation layer may be made of intrinsic amorphous silicon.

The method of manufacturing a solar cell according to the above feature may further include forming a second protective film on the plurality of first impurities and on the exposed portion of the substrate before forming the second impurity film, The second impurity layer may be located on the second protective layer and the second impurity layer forming step may include forming the second protective layer located below the second impurity portion etched by the second etching paste into the second etching paste And forming a plurality of second protective portions under the plurality of second impurity portions by etching.

The second passivation layer may be made of intrinsic amorphous silicon.

The method for manufacturing a solar cell according to the above feature may further comprise cleaning the first surface of the substrate using a first solution after forming the plurality of first impurity portions and cleaning the first surface of the substrate after forming the plurality of second impurity portions , And cleaning the first surface of the substrate using a second solution.

The first solution and the second solution may be water.

Wherein the first and second electrode forming steps are performed by applying a metal paste on the plurality of first impurity regions and the plurality of second impurity regions by a screen printing method and then drying the metal paste, A plurality of first electrodes may be formed and the plurality of second electrodes may be formed on the plurality of second impurity regions.

The method of manufacturing a solar cell according to the above feature may further include forming an antireflection film on the second surface of the substrate facing the first surface of the substrate.

The first surface of the substrate may be a surface on which light is not incident, and the second surface of the substrate may be a surface on which light is incident.

It is preferable that the substrate is made of a crystalline semiconductor, and the first impurity portion and the second impurity portion are made of an amorphous semiconductor.

According to the features of the present invention, since the plurality of first impurity portions and the plurality of second impurity portions are formed by using the etching paste, the manufacturing process of the solar cell is easy and the process time is shortened.

1 is a partial perspective view of a solar cell according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the solar cell shown in FIG. 1 taken along line II-II.
3A to 3J are views sequentially illustrating a manufacturing process of a solar cell according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, a solar cell according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. FIG.

FIG. 1 is a partial perspective view of a solar cell according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II of the solar cell shown in FIG.

1 and 2, a solar cell 11 according to an embodiment of the present invention includes a substrate 110, an incident surface (hereinafter referred to as a front surface) that is a surface of the substrate 110 on which light is incident, (Hereinafter referred to as the 'surface') of the substrate 110, which is the surface opposite to the incident surface without incidence of light, is formed on the front protective portion 191, the anti-reflection portion 130, A plurality of emitter regions 121 located on the rear protective portion 192 and a plurality of emitter regions 121 located on the rear protective portion 192. The plurality of emitter regions 121, A plurality of first electrode 141 located on each of the plurality of emitter sections 121 and a plurality of second electrodes 141 disposed on the plurality of emitter sections 121 and spaced apart from the emitter section 121, And a plurality of second electrodes 142 positioned on the rear electric field 172, respectively.

The substrate 110 is a semiconductor substrate made of silicon of a first conductivity type, for example, n-type conductivity type. Here, the silicon is crystalline silicon such as monocrystalline silicon or polycrystalline silicon. Impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) are doped to the substrate 110 when the substrate 110 has an n-type conductivity type. Alternatively, however, the substrate 110 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon. When the substrate 110 has a p-type conductivity type, the substrate 110 is doped with an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In)

Such a substrate 110 has an uneven surface with an irregular surface. In FIG. 1, only the edge portion of the substrate 110 is shown as an uneven surface, and the front protective portion 191 and the anti-reflection portion 130, which are positioned thereon, are also shown with only the edge portion thereof as an uneven surface. However, the entire front surface of the substrate 110 substantially has an uneven surface, so that the front surface protective portion 191 and the anti-reflection portion 130, which are located on the front surface of the substrate 110, also have uneven surfaces.

In addition, the substrate 110 may have an uneven surface on the rear surface as well as on the front surface. In this case, the rear surface protection part 192, the plurality of emitter parts 121, the rear electric part 172, and the first and second electrodes 141 and 142 located on the rear surface of the substrate 110 are also provided with the irregular surface Lt; / RTI >

The front surface protection unit 191 located on the front surface of the substrate 110 changes a defect such as a dangling bond mainly present on the surface of the substrate 110 and its vicinity to a stable bond, A passivation function is performed to reduce the amount of charge lost on the surface of the substrate 110 and the vicinity thereof due to the defect.

In this embodiment, the front surface protection portion 191 is made of intrinsic amorphous silicon (a-Si) and may have a thickness of about 1 nm to 10 nm.

If the thickness of the front protective part 191 is about 1 nm or more, the front protective part 191 is more uniformly coated on the entire surface of the substrate 110, so that the passivation function can be performed more satisfactorily. The amount of light absorbed in the front protective portion 191 may be further reduced to further increase the amount of light incident into the substrate 110. [ The front surface protecting portion 191 can be omitted if necessary.

The antireflection part 130 located on the front surface protection part 191 reduces the reflectivity of light incident on the solar cell 11 and increases the selectivity of a specific wavelength area to increase the efficiency of the solar cell 11. The antireflective portion 130 is made of a silicon nitride film (SiNx), an amorphous silicon nitride film (a-SiNx), a silicon oxide film (SiOx) or the like, and may have a thickness of about 70 nm to 90 nm. The antireflection portion 130 may be omitted if necessary.

The rear surface protection portion 192 located on the rear surface of the substrate 110 includes a plurality of first rear surface protection portions 1921 and a plurality of second rear surface protection portions 1922 which are spaced apart from each other. The first rear surface protection portion 1921 and the second rear surface protection portion 1922 are alternately arranged on the substrate 110 and extend in a predetermined direction in parallel with each other.

Like the front surface protection part 191, the rear surface protection part 192 is made of intrinsic amorphous silicon and performs a passivation function, thereby reducing the disappearance of charges due to the unstable coupling to the rear surface of the substrate 110.

The first and second rear surface protection portions 1921 and 1922 of the rear surface protection portion 192 are formed so that the charges moved toward the rear surface of the substrate 110 pass through the first and second rear surface protection portions 1921 and 1922, To the emitter section (121) and the plurality of rear electric sections (172). For example, the thickness of each of the first and second back protection portions 1921, 1922 may be about 1 nm to 10 nm.

When the thickness of each of the first and second rear surface protection parts 1921 and 1922 is about 1 nm or more, the first and second rear surface protection parts 1921 and 1922 are more uniformly coated on the rear surface of the substrate 110, And if the thickness of each of the first and second rear surface protection portions 1921 and 1922 is about 10 nm or less, it is possible to facilitate the movement of the charge and to prevent the first and second rear surface protection portions 1921 and 1922 The amount of light absorbed by the substrate 110 can be further reduced and the amount of light incident on the substrate 110 can be further increased. Similarly to the front surface protection portion 191, the rear surface protection portion 192 may also be omitted if necessary.

A plurality of emitter portions 121 are present on the first rear surface protection portion 1921 of the rear surface protection portion 192 and extend along the first rear surface protection portion 1921.

Each emitter section 121 has a second conductivity type, for example, a p-type conductivity type opposite to the conductivity type of the substrate 110, and is formed of a semiconductor different from the substrate 110, for example, amorphous silicon It is an impurity part made up. Thus, the emitter layer 121 forms a heterojunction with the substrate 110 made of a crystalline semiconductor and also forms a p-n junction.

Hole pairs that are charges generated by the light incident on the substrate 110 due to the built-in potential difference due to the pn junction formed between the substrate 110 and the plurality of emitter portions 121, And electrons move to the n-type and the holes move to the p-type. Therefore, when the substrate 110 is n-type and the plurality of emitter portions 121 are p-type, the separated holes pass through the first rear surface protection portion 1921 of the rear surface protection portion 192 to form the emitter portions 121, And the separated electrons move toward the second rear surface protection portion 1921 of the rear surface protection portion 192. [

Each emitter section 121 forms a pn junction with the substrate 110. Thus, unlike the present embodiment, when the substrate 110 has a p-type conductivity type, the emitter section 121 is an n-type conductivity type I have. In this case, the separated electrons are moved toward the plurality of emitter portions 121 through the first rear surface protection portion 1921 of the rear surface protection portion 192 and the separated holes are guided to the second rear surface protection portion 192 of the rear surface protection portion 192, (1922).

When the plurality of emitter sections 121 have a p-type conductivity type, the emitter section 121 can be doped with an impurity of a trivalent element. Conversely, when the plurality of emitter sections 121 have an n-type conductivity type , The emitter portion 121 may be doped with an impurity of a pentavalent element.

Each emitter section 121 may have a thickness of about 5 nm to 15 nm.

When the thickness of the emitter section 121 is about 5 nm or more, the pn junction can be formed more satisfactorily. When the thickness of the emitter section 121 is about 15 nm or less, the amount of light absorbed in the emitter section 121 is further reduced, It is possible to increase the amount of light to be emitted.

The plurality of emitter sections 121 can perform a passivation function together with the first rear surface protection section 1921. In this case, the amount of charge that is extinguished at the rear surface of the substrate 110 due to the defect is reduced, 11 is improved.

A plurality of rear electric components 172 are present on the second rear surface protection portion 1922 of the rear surface protection portion 192 and extend along the second rear surface protection portion 1922. Accordingly, as shown in FIGS. 1 and 2, on the rear surface of the substrate 110, the rear electric section 172 and the emitter section 121 are alternately located.

The plurality of rear electric field portions 172 are impurity portions of the same conductivity type as the substrate 110 and doped at a higher concentration than the substrate 110. For example, the plurality of backside electrical sections 172 may be n + impurity regions.

In this embodiment, the plurality of rear electric sections 172 are made of an amorphous semiconductor, such as amorphous silicon (a-Si), and form a hetero junction with the substrate 110.

This rear electric field 172 prevents the hole movement toward the rear electric field 172, which is the direction of movement of the electrons, due to the potential barrier due to the difference in impurity concentration between the substrate 110 and the rear electric field 172, (E. G., Electrons) to the electrical system 172. The < / RTI > Thus, the amount of charge, e. G., Electrons, that has passed through the second rear surface protection portion 1922 is reduced by recombining with the holes in the rear electric < / RTI & To the rear electric section 17, thereby increasing the amount of electron movement to the rear electric section 172. [

Each backside electrical conductor 172 may have a thickness of about 10 nm to 25 nm. If the thickness of the rear electric field 172 is about 10 nm or more, the electric potential barrier that prevents the movement of the holes can be formed more favorably, thereby further reducing the charge loss. If the thickness is about 25 nm or less, It is possible to further reduce the amount of light absorbed and to further increase the amount of light re-incident into the substrate 110.

The plurality of rear electric fields 172 can perform the passivation function together with the second rear surface protection portion 1922. In this case, the amount of electric charges disappearing from the rear surface of the substrate 110 due to the defects is reduced, (11) is improved. This rear electric section 172 can be omitted if necessary.

In the present embodiment, due to the rear protective portion 192 of the intrinsic semiconductor material (intrinsic a-Si) located below the plurality of emitter portions 121 and the plurality of rear electric sections 172 and having no or little impurities, When a plurality of emitter portions 121 and a plurality of rear electric fields 172 are formed on a substrate 110 made of a crystalline semiconductor material rather than a plurality of emitter portions 121 and a plurality of rear electric fields 172, The crystallization phenomenon is reduced. This improves the characteristics of the plurality of emitter portions 121 and the plurality of rear electric sections 172 located on the intrinsic amorphous silicon.

The width W1 of the emitter section 121 is larger than the width W1 of the rear electric section 172. The width W1 of the emitter section 121 is different from the width W1 of the rear electric section 172. [ The width of the first rear surface protection portion 1921 existing under the emitter portion 121 is greater than the width of the second rear surface protection portion 1922 existing under the rear surface electric portion 172. [ This increases the amount of electron-hole pairs generated, increases the pn junction region, reduces the current loss at the pn junction, and is advantageous for the collection of holes having lower mobility than electrons.

Alternatively, however, the width W2 of the rear electric section 172 may be greater than the width W1 of the emitter section 121. [ In this case, the surface area of the substrate 110 covered with the rear electric section 172 increases, and the rear electric field effect due to the rear electric section 172 increases.

The plurality of first electrodes 141 located on the plurality of emitter sections 121 extend long along the plurality of emitter sections 121 and are physically and electrically connected to the plurality of emitter sections 121.

Each first electrode 141 collects charges, for example, holes, which move toward the corresponding emitter section 121.

A plurality of second electrodes 142 positioned over the plurality of backside electrical components 172 extend elongate along the plurality of backside electrical components 172 and are electrically and physically connected to the plurality of backside electrical components 172 have.

Each second electrode 142 collects an electric charge, e. G., Electrons, that has migrated toward the rear electric field 172.

The first and second electrodes 141 and 142 may be formed of a metal such as aluminum (Al) or silver (Ag), but may be formed of a metal such as nickel (Ni), copper (Cu), tin ), Indium (In), titanium (Ti), gold (Au), and combinations thereof, or other conductive metal materials.

Since the plurality of first and second electrodes 141 and 142 are made of a metal material, the plurality of first and second electrodes 141 and 142 are electrically connected to the plurality of emitter portions 121 and the plurality of rear electrical parts 172 to the substrate 110 side.

The solar cell 11 according to the present embodiment having such a structure has a structure in which a plurality of first electrodes 141 and a plurality of second electrodes 142 are positioned on the rear surface of a substrate 110 on which light is not incident, 110 and a plurality of emitter portions 121 are made of different kinds of semiconductors. The operation of the solar cell is as follows.

When the solar cell 11 is irradiated with light and sequentially passes through the antireflection portion 130 and the front surface protection portion 191 and then is incident on the substrate 110, an electron-hole pair is generated in the substrate 110 by light energy do.

At this time, the reflection loss of light incident on the substrate 110 is reduced by the anti-reflection unit 130, and the amount of light incident on the substrate 110 is further increased.

These electron-hole pairs are separated from each other by the pn junction of the substrate 110 and the emitter section 121, and the holes move to the emitter section 121 having the p-type conductivity type, and electrons move to the n- And is collected by the first and second electrodes 141 and 142 by being transferred to the first electrode 141 and the second electrode 142, respectively. When the first electrode 141 and the second electrode 142 are connected to each other by a conductor, a current flows and the external power is utilized.

At this time, since the protective portions 192 and 191 are located on the front surface of the substrate 110 as well as the rear surface of the substrate 110, the amount of charge loss due to defects existing on the front surface and the rear surface of the substrate 110 and in the vicinity thereof is reduced The efficiency of the solar cell 11 is improved.

In addition, since the electric field portion 172 containing the impurity of the same conductivity type as the substrate 110 is located at the rear surface of the substrate 110, the hole movement to the rear surface of the substrate 110 is hindered. Thus, the recombination of electrons and holes at the back surface and the vicinity of the substrate 110 and the disappearance thereof are reduced, and the efficiency of the solar cell 11 is improved.

Since the solar cell 11 according to the present embodiment is a solar cell using the heterojunction between the substrate 110 and the plurality of emitter portions 121, the band gap energy between the substrate 110 and the emitter portion can be reduced, Eg) is obtained. As a result, the efficiency of the solar cell 11 is higher than that of the solar cell using the homogeneous junction.

Next, a method of manufacturing the solar cell 11 according to one embodiment of the present invention will be described with reference to FIGS. 3A to 3J. FIG.

3A to 3J are views sequentially illustrating a manufacturing process of a solar cell according to an embodiment of the present invention.

3A, first, an etch stopping layer 60 made of a silicon oxide (SiOx) or the like is stacked on the rear surface of a substrate 110 made of n-type polycrystalline silicon.

3B, the surface of the substrate 110 on which the etch stopping layer 60 is not formed is etched and cleaned using the etch stopping layer 60 as a mask. Then, the etch stopping layer 60 is removed do. Therefore, a saw damage portion of the surface of the substrate 110, which is generated in a slicing process for obtaining a substrate for a solar cell in a silicon ingot, is removed, and an uneven surface is formed on the surface of the exposed substrate 110 .

In an alternative embodiment, the surface of the substrate 110 to be etched or the entire surface of the substrate 110 may be exposed to an etchant or the like without forming a separate etch stopping layer 60 to form an uneven surface on the surface of the desired substrate 110 .

Then, as shown in FIG. 3C, the surface of the substrate 110, which is an uneven surface, and the rear surface of the substrate 110 are patterned by using a vapor deposition method such as plasma enhanced chemical vapor deposition (PECVD) Thereby forming a front protective portion 191 and a first rear protective film 921. At this time, the front surface protection layer 191 and the first rear surface protection layer 921 made of the same material are formed on the front surface and the rear surface of the substrate 110 by changing the surface position of the substrate 110 exposed to the deposition material, The order of forming the first rear surface protective film 921 and the first rear surface protective film 921 can be changed.

Next, as shown in FIG. 3D, the first passivation layer 920 is formed of amorphous silicon using a silane gas (SiH 4), hydrogen (H ₂ ), a dopant of a trivalent element or the like on the first rear passivation film 921 using PECVD or the like, An amorphous silicon layer containing elemental impurities is formed to form an emitter film 21 which is an impurity film.

Next, as shown in FIG. 3E, an etching paste 61 is partially applied on the emitter film 21 by screen printing or the like, and then heat-treated. At this time, the etching paste 61 has a property of etching the emitter film 21 containing the impurity of the trivalent element and the first rear surface protective film 921 which is the intrinsic amorphous silicon film located below the emitter film 21.

The portion of the emitter film 21 to which the etching paste 61 is applied and the portion of the first rear surface protective film 921 below the etching film are sequentially etched by the etching paste 61 and the etching paste 61 is applied The portion of the emitter film 21 and the portion of the first rear surface protection film 921 below the emitter film 21 are not etched.

At this time, since the amount to be etched is determined depending on the heat treatment time of the etching paste 61, the heat treatment temperature, or the coating thickness of the etching paste, the heat treatment time, the heat treatment temperature, To protect the substrate 110 present on the substrate 100 from the etching paste 62.

Therefore, when the predetermined heat treatment time has elapsed, a cleaning operation of the substrate 110 is performed using water or the like to remove the residue of the etching paste 61 present on the substrate 110. As a result, as shown in FIG. 3F, a plurality of first rear surface protection portions 1921 and a plurality of emitter portions 121 disposed thereon are completed.

Next, as shown in FIG. 3G, a second rear surface protective film 922 made of intrinsic amorphous silicon is formed by PECVD or the like, and a silane gas (SiH ₄ ), hydrogen (H ₂ ) (for example, n ⁺ -a-Si), which is made of amorphous silicon and contains impurities of the pentavalent element at a higher concentration than the substrate 110, is formed using a dopant or the like, (72).

Then, as shown in FIG. 3H, the etching paste 62 is partially applied on the rear field film 72 by screen printing or the like, and then heat-treated. At this time, the etching paste 62 has a property of etching the rear field film 72 containing the impurities of the pentavalent element and the second rear protective film 922 located below the rear electric field film 72.

At this time, the etching paste 62 is different from the etching paste 61 and is made of an alkali such as a KOH (potassium hydroxide) etching paste, a TMAH (tetramethyl ammonium hydroxide) etching paste, or an EDP (ethylene diamine pyrocatechol) ) Based etching paste.

Generally, when silicon (Si) is etched using an alkaline (OH-) etchant, the reaction formula between silicon (Si) and etchant is as follows.

1) Si + 2OH-? Si (OH) ₂ ²⁺ + 4e-

_{2) 4H 2 O + 4e- →} 4OH- + 2H 2

3) Si (OH) ₂ ² + 4e- + 4H ₂ O -> Si (OH) ₆ ^2- + 2H ₂

That is, 1) as if one is Si (OH) ₂ ²⁺ created by the scheme in conjunction with the 4OH- generated by 2) times scheme 3) times in Scheme, Si is the Si (OH) ₆ ^2- Silicon (Si) is etched in the form of water.

However, the electrons (e-) produced in the reaction formula (1) are contained in the silicon film doped with the p-type impurity when a p-type impurity such as boron meets a film doped at a high concentration (about 10 ²⁰ cm ^-3 or more) (2)) reaction to prevent the formation of 4OH-, resulting in (3) no reaction and eventually the silicon (Si) is not etched. Therefore, the etching paste 62 is not etched in the film containing the p-type impurity.

The portion of the rear surface electric field film 72 to which the etching paste 62 is applied and the portion of the second rear surface protective film 922 below the rear surface electric film 72 are sequentially etched by the etching paste 62, The portion of the rear surface electric field film 72 which is not provided, the portion of the second rear surface protective film 922 which is below the portion, and the plurality of emitter portions 121 containing the p-type impurity are not etched by the etching paste 62.

Therefore, the rear electric field layer 72 of the portion to which the etching paste 62 is applied and the second rear surface protective layer 922 thereunder are sequentially etched. At this time, the emitter portion 121 is provided with the p- When the etching paste 62 comes into contact with the emitter section 121, no further etching operation is performed because impurities are contained.

Therefore, when the predetermined heat treatment time has elapsed, the cleaning operation of the substrate 110 is performed using water or the like to remove the residue of the etching paste 62 present on the substrate 110, A plurality of rear electric sections 172 spaced apart from the plurality of emitter sections 121 and a second rear surface protection section 1922 located under the plurality of emitter sections 121 are formed on the rear surface of the substrate 110, 1 rear protection portion 1921 and a plurality of second rear protection portions 1922 are completed. At this time, the substrate 110 existing under the second rear protective film 922 is protected from the etching paste 62 by adjusting the heat treatment time of the etching paste 62, the heat treatment temperature, or the application amount of the paste.

The etching paste 61 is applied to correspond to the positions where the plurality of emitter portions 121 are formed and the etching paste 62 is formed on the rear surface of the substrate 110 such that a plurality of rear electric fields 172 are formed In the same manner as in the first embodiment.

As compared with the method of forming a plurality of emitter portions and a plurality of rear surface electric field portions on the rear surface of the substrate 110 through the use of a photoresist, a light exposure, a development process, and an etching process, A plurality of emitter portions and a plurality of rear surface electric field portions are formed by using an etching paste for etching a desired portion. As a result, the process of forming the plurality of emitter portions and the plurality of rear electric field portions becomes very simple, and the process time of the plurality of emitter portions and the plurality of rear electric field portions is greatly shortened, thereby reducing the process time and manufacturing cost of the solar cell do.

Further, a plurality of etching pads 61, 62 selectively etching only one of a film having a p-type conductivity type (for example, an emitter portion) and an n-type conductive type (for example, Both the emitter section 121 and the plurality of rear electric sections 172 are formed using the etching paste, so that the processing time and manufacturing cost of the solar cell 11 are reduced.

Next, as shown in FIG. 3J, a metal paste containing a metal material such as aluminum (Al) or silver (Ag) is formed on a plurality of emitter portions 121 and a plurality of rear electric field portions 172 by a screen printing method And then dried. A plurality of first electrodes 141 located on the plurality of emitter sections 121 and extending along the plurality of emitter sections 121 and a plurality of rear electric sections 172 located on the plurality of rear electric sections 172, A plurality of second electrodes 142 are formed.

Then, the antireflective portion 130 is formed on the front protective portion 191 to complete the solar cell 11 (FIGS. 1 and 2). In this case, the radiation prevention part 130 may be formed by a process performed at a low temperature to protect the components formed on the rear surface of the substrate 110, for example, a sputtering method. However, the radiation prevention part 130 may be formed by various film deposition methods such as PECVD .

In the present embodiment, the substrate 110 is an n-type and the plurality of emitter portions 121 are p-type. However, as described above, the substrate 110 is p-type and the plurality of emitter portions 121 n-type. In this case, the plurality of rear electric sections 172 become p-type impurity regions which are the same as the substrate 110.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

21: Emitter film 61, 62: Etching paste
72: rear surface electric field film 110: substrate
121: Emitter part 130: Antireflection part
141, 142: Electrode 172:
191: front protection part 192: rear protection part
921, 922: Rear protective film 1921, 1922: Rear protective film

Claims (16)

Forming a first protective film on the first surface of the substrate,
Forming a first impurity film containing a first impurity on the first protective film,
A first etching paste is partially applied on the first impurity film to sequentially etch the first impurity film in contact with the first etching paste and the first protective film under the first impurity film to form a plurality of Forming a plurality of first impurity portions located over the first protective portion and the plurality of first protective portions,
Forming a second protective film on the first face of the substrate on which the plurality of first impurity portions and the plurality of first impurity portions are not located,
Forming a second impurity film containing a second impurity on the second protective film,
A second etching paste is partially applied on the second impurity film to sequentially etch the second impurity film in contact with the second etching paste and the second protective film under the second impurity film to form a plurality of Forming a plurality of second impurity portions located on the second protective portion and the plurality of second protective portions, and
Forming a plurality of first electrodes and a plurality of second electrodes respectively disposed on the plurality of first impurity portions and the plurality of second impurity portions,
Lt; / RTI >
Wherein the plurality of first impurity portions are located apart from the plurality of second impurity portions,
The plurality of first protective portions being spaced apart from the plurality of second protective portions,
Wherein the first etching paste and the second etching paste contain different materials. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
Wherein the first impurity has a p-type conductivity type and the second impurity has an n-type conductivity type. Claim 3 has been abandoned due to the setting registration fee. 3. The method of claim 2,
Wherein the second etching paste contains an alkali-based material. Claim 4 has been abandoned due to the setting registration fee. 4. The method of claim 3,
Wherein the alkali-based material contains potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), or ethylene diamine pyrocatechol (EDP). Claim 5 has been abandoned due to the setting registration fee. 3. The method of claim 2,
Wherein the substrate contains an n-type impurity. Claim 6 has been abandoned due to the setting registration fee. The method of claim 1,
And forming a third protective film on the second surface of the substrate facing the first surface of the substrate. Claim 7 has been abandoned due to the setting registration fee. The method of claim 6,
Wherein the first to third protective films are made of the same material. Claim 8 has been abandoned due to the setting registration fee. 8. The method of claim 7,
Wherein the first to third protective films are made of intrinsic amorphous silicon. Claim 9 has been abandoned due to the setting registration fee. The method of claim 1,
The widths of the first impurity portion and the second impurity portion being different from each other,
The width of the first protective portion is equal to the width of the first impurity portion,
And the width of the second protective portion is equal to the width of the second impurity portion. Claim 10 has been abandoned due to the setting registration fee. The method of claim 9,
Wherein a width of the first impurity portion is larger than a width of the second impurity portion. Claim 11 has been abandoned due to the set registration fee. The method of claim 1,
Cleaning the first surface of the substrate with a first solution after forming the plurality of first impurity portions and the plurality of first protective portions,
Cleaning the first surface of the substrate using a second solution after forming the plurality of second impurity portions and the plurality of second protective portions,
Further comprising the steps of: Claim 12 is abandoned in setting registration fee. 12. The method of claim 11,
Wherein the first solution and the second solution are water. Claim 13 has been abandoned due to the set registration fee. The method of claim 1,
Wherein the first and second electrode forming steps are performed by applying a metal paste onto the plurality of first impurity regions and the plurality of second impurity regions by a screen printing method, Wherein the plurality of first electrodes are formed and the plurality of second electrodes are formed on the plurality of second impurity regions. Claim 14 has been abandoned due to the setting registration fee. The method of claim 1,
And forming an antireflection film on the second surface of the substrate facing the first surface of the substrate. Claim 15 is abandoned in the setting registration fee payment. The method of claim 14,
Wherein the first surface of the substrate is a surface on which light is not incident and the second surface of the substrate is a surface on which light is incident. Claim 16 has been abandoned due to the setting registration fee. 16. The method according to any one of claims 1 to 15,
Wherein the substrate is made of a crystalline semiconductor, and the first impurity region and the second impurity region are made of an amorphous semiconductor.

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