KR101696412B1 - Semiconductive chip device having an air gap and method for manufacturing the same - Google Patents

Semiconductive chip device having an air gap and method for manufacturing the same Download PDF

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Publication number
KR101696412B1
KR101696412B1 KR1020150033229A KR20150033229A KR101696412B1 KR 101696412 B1 KR101696412 B1 KR 101696412B1 KR 1020150033229 A KR1020150033229 A KR 1020150033229A KR 20150033229 A KR20150033229 A KR 20150033229A KR 101696412 B1 KR101696412 B1 KR 101696412B1
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KR
South Korea
Prior art keywords
substrate
electrode
discharge
cavity
protective cover
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KR1020150033229A
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Korean (ko)
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KR20150105934A (en
Inventor
박규환
유준서
오수민
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주식회사 아모텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Adjustable Resistors (AREA)
  • Thermistors And Varistors (AREA)

Abstract

The present invention relates to a chip device having a cavity and a method of manufacturing the same, and more particularly, to a chip device having an internal electrode portion including a first electrode portion and a second electrode portion, A void portion formed in a space portion between the first electrode portion and the second electrode portion; A discharger formed on the gap portion; And a protective cover portion covering the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a chip device having a cavity,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip element having a cavity and a manufacturing method thereof, and more particularly, to a chip element which improves the reliability of a chip element by forming a void in the chip element and a method of manufacturing the same.

Recently, as a technique for increasing the degree of integration of a chip element or a ceramic element, a metal wiring is formed in each layer of a multi-layered structure, or a method of narrowing the interval between the metal wiring and the metal wiring on the same layer is adopted.

The problem of dealing with parasitic resistance and parasitic capacitance existing between metal wirings adjacent to each other or between metal wirings adjacent to each other on the same layer becomes most important as the distance between metal wirings becomes narrow.

That is, in the case of a highly integrated chip device or a ceramic device, the parasitic resistance and the parasitic capacitance components present in the multilayered metal interconnect structure deteriorate the electrical characteristics of the device due to delay induced by RC (Resistance Capacitance) Furthermore, there is a problem that the power consumption and the signal leakage amount of the chip device or the ceramic device can be increased.

Therefore, in recent years, there have been many attempts to reduce the parasitic capacitance between wirings by using a low-k material and an air gap in a multi-layer metal wiring process in which ultra-high-integration chip devices or ceramic devices are used. Methods for forming such voids include a method of forming a metal and an interlayer insulating layer as described in Korean Patent Laid-Open No. 10-2010-0078778 and then removing all of the interlayer insulating layer by wet etching, and a method of forming a void by forming a void between the interlayer insulating layers by maximizing the overhang by controlling the deposition parameters of the plasma enhanced chemical vapor deposition method.

However, when the interlayer insulating layer is entirely removed by the wet etching or ashing method in the conventional method of forming voids, a highly integrated chip element or a ceramic element is not structurally stable in the following process, There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which can improve the reliability of a chip component by filling a gap- And a method of manufacturing the same.

According to an aspect of the present invention, there is provided a chip device having a cavity, the chip device including: a first electrode unit and a second electrode unit; A void portion formed in a space portion between the first electrode portion and the second electrode portion; A discharger formed on the gap portion; And a protective cover portion covering the substrate.

The first electrode portion and the second electrode portion may be horizontally spaced from each other on the substrate to form the space portion.

In addition, the void portion may be formed by filling a void-forming material comprising any one of a polymer material and a carbon material in the space portion, and then firing the void-forming material.

One end of the discharge unit may be in contact with the first electrode unit and the other end may be in contact with the second electrode unit.

In addition, the protective cover portion may cover the discharge portion, the gap portion, the internal electrode portion, and the upper portion of the substrate.

In addition, the substrate may be formed of any one of a ceramic substrate and a metal substrate.

In addition, the discharge unit may be formed of a discharge material including at least one of a conductive metal and a metal compound.

At this time, the conductive metal includes at least one of silver (Ag), palladium (Pd), nickel (Ni), copper (Cu), and platinum (Pt), and the metal compound includes silicon carbide (SiC), barium titanate ), Zinc oxide (ZnO), and tin oxide (SnO).

The protective cover may be made of glass or epoxy glass.

According to an aspect of the present invention, there is provided a method of manufacturing a chip device having a cavity, the method comprising: a) forming a first electrode portion and a second electrode portion on a substrate; b) filling voids in the space between the first electrode portion and the second electrode portion;

c) forming a discharge portion on the space portion filled with the void-forming material; And d) laminating a protective cover portion on the substrate.

The first electrode portion and the second electrode portion may be horizontally spaced from each other on the substrate to form the space portion.

Further, after the step d), the step of firing the void-forming material filled in the space part may further include forming a void part.

According to the present invention, a chip element having a cavity and a method of manufacturing the same are provided with a cavity forming material filling and firing between the internal electrode and the discharge portion to sublimate at a certain temperature or higher, thereby minimizing deformation due to heat of the chip element There is an effect that can be done.

Further, the present invention has the effect of stabilizing the reliability and electrical characteristics of the chip element by dispersing stress by forming a gap between the internal electrode and the discharge portion.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for explaining a chip element having a cavity according to an embodiment of the present invention; FIG.
2 is a view for explaining a procedure for manufacturing a chip element having a cavity according to an embodiment of the present invention;
3 to 7 are perspective views illustrating a process of manufacturing a chip device having a cavity according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

Hereinafter, with reference to FIG. 1, a structure of a chip element having a cavity according to an embodiment of the present invention will be described.

1, a chip device 100 having a gap according to the present invention includes a substrate 110, an internal electrode unit 120, a gap unit 130, a discharge unit 140, and a protective cover unit (not shown) 150).

Here, the chip device 100 according to the present invention is implemented in an ESD (Electro-Static Discharge) protection device for protecting a semiconductor circuit in a common region of adjacent pads, and can be applied to various semiconductor package technologies.

The substrate 110 may be formed of any one of a ceramic substrate produced by different manufacturing techniques such as DBC, DPC, LTCC, and HTCC, and a metal substrate such as a PCB or an FPCB. That is, the substrate 110 may correspond to all kinds of substrates having the flat surface on which the internal electrode unit 120 can be printed.

The internal electrode portion 120 is formed on the substrate 110. The internal electrode unit 120 includes a first electrode unit 120a and a second electrode unit 120b that are horizontally spaced apart from each other on the substrate 110. [ At this time, a space portion 121 is formed between the first electrode portion 120a and the second electrode portion 120b.

The cavity portion 130 is formed in the space portion 121 between the first electrode portion 120a and the second electrode portion 120b. The void-forming material for forming the void portion 130 may be composed of a polymer material for low temperature, a carbon material for high temperature, a polymer material, and a mixture of carbon materials, which is sublimated at a certain temperature or higher. That is, the void-forming material refers to a material which can be kept at a room temperature or below a certain temperature and can be sublimated into a gas at a certain temperature or higher. Accordingly, the void portion 130 is formed by filling a void-forming material in the void portion 121 and then firing the void-forming material. The process of forming the void portion 130 will be described in detail with reference to FIGS. 3 to 7 .

The discharge part 140 is formed on the gap part 130 and is in contact with the internal electrode part 120. That is, one end of the discharge unit 140 is in contact with the first electrode unit 121 and the other end is in contact with the second electrode unit 122. At this time, the discharge unit 140 may be formed of a discharge material having overvoltage and overcurrent protection functions such as ESD discharge and surge absorption. At this time, the discharge material may include at least one of a conductive metal and a metal compound. Here, the conductive metal includes at least one of silver (Ag), palladium (Pd), nickel (Ni), copper (Cu), and platinum (Pt), and the metal compound includes silicon carbide (SiC), barium titanate BaTiO3, zinc oxide (ZnO), and tin oxide (SnO).

 The protective cover portion 150 covers the substrate 110. That is, the protective cover unit 150 has a size and shape corresponding to the substrate to cover the entire substrate 110 having the discharge unit 140, the cavity unit 130, and the internal electrode unit 120, The material may be formed of any one of glass and epoxy glass, but is not limited thereto.

Hereinafter, a method of manufacturing a chip element having a cavity according to an embodiment of the present invention will be described with reference to FIGS. 2 to 7. FIG.

Referring to FIG. 2, in the method of manufacturing a chip element having a cavity according to the present invention, a step S100 of printing the internal electrode unit 120 on the substrate 100 is performed.

Next, a step S200 of filling the gap forming material a between the internal electrode portions 120 is performed.

Next, a step S300 of forming the discharge part 140 is performed.

Next, a step S400 of laminating the protective cover portion 150 on the substrate 110 is performed.

Finally, a step S500 of forming the void 120 by firing the void-forming material (a) is sequentially performed, and each step will be described in more detail with reference to FIG. 3 to FIG.

In operation S100, the first electrode unit 120a and the second electrode unit 120b are formed on the substrate 110 as shown in FIG. At this time, the first electrode part 120a and the second electrode part 120b are horizontally spaced apart from each other on the substrate 110 to form the space part 121. [

In step S200, as shown in FIG. 4, the void forming material a is filled in the space 121 between the first electrode part 120a and the second electrode part 120b. At this time, the void-forming material (a) may be composed of a material that sublimates at a certain temperature or higher in one of a polymer material for low temperature, a carbon material for high temperature, a polymer material, and a mixture of carbon materials.

As shown in FIG. 5, the discharging unit 140 is formed on the space 121 filled with the void forming material (a). At this time, the discharge unit 140 may be formed of a discharge material having an overvoltage and overcurrent protection function such as ESD discharge and surge absorption.

In operation S400, the protective cover unit 150 is stacked on the substrate 110 as shown in FIG. At this time, the material of the protective cover part 150 may be any one of glass and epoxy glass.

Finally, in step S500, the porous material (a) is baked as shown in FIG. The substrate including the internal electrode part 120, the discharge part 140, and the protective cover part 150 is heated at a temperature at which the void forming material a sublimates at step S500. Thereafter, the void forming material (a) in the space portion 121 is sublimated and removed, whereby a chip element having a sectional structure as shown in Fig. 1 is produced.

As described above, according to the present invention, there is provided a chip element having a cavity and a method of manufacturing the same, wherein the cavity forming material that sublimates at a temperature higher than a predetermined temperature is filled between the internal electrode and the discharge material, And at the same time, the stress can be dispersed, so that the reliability and characteristics of the chip element can be stabilized.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but many variations and modifications may be made without departing from the scope of the present invention. It will be understood that the invention may be practiced.

100: chip device 110: internal electrode part
130: air gap part 140: discharge part
150: protective cover part

Claims (12)

An internal electrode unit including a first electrode unit and a second electrode unit, the internal electrode unit being formed on the substrate;
A void portion formed in a space portion between the first electrode portion and the second electrode portion;
A discharging part formed on the gap part, one end thereof being in contact with the first electrode part and the other end being in contact with the second electrode part to absorb ESD (Electrostatic Discharge) discharge or surge voltage; And
And a protective cover portion covering the substrate,
Wherein the discharge unit includes at least one of a conductive metal and a metal compound, and is formed of a discharge material having an overvoltage and an overcurrent protection function. The method according to claim 1,
Wherein the first electrode portion and the second electrode portion are horizontally spaced apart from each other on the substrate to form the space portion. The method according to claim 1,
Wherein the cavity portion is formed by filling a cavity-forming material comprising one of a polymer material and a carbon material in the space portion, and then firing the cavity-forming material. delete The method according to claim 1,
Wherein the protective cover portion covers the discharge portion, the gap portion, the internal electrode portion, and the upper portion of the substrate. The method according to claim 1,
Wherein the substrate comprises a ceramic substrate and a metal substrate. delete The method according to claim 1,
Wherein the conductive metal comprises at least one of silver (Ag), palladium (Pd), nickel (Ni), copper (Cu), and platinum (Pt), and the metal compound is selected from the group consisting of silicon carbide (SiC), barium titanate ), Zinc oxide (ZnO), and tin oxide (SnO). The method according to claim 1,
Wherein a material of the protective cover portion is formed of one of glass and epoxy glass. delete delete delete
KR1020150033229A 2014-03-10 2015-03-10 Semiconductive chip device having an air gap and method for manufacturing the same KR101696412B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020140027857 2014-03-10
KR20140027857 2014-03-10

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KR20150105934A KR20150105934A (en) 2015-09-18
KR101696412B1 true KR101696412B1 (en) 2017-01-16

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217293A (en) * 2000-11-27 2002-08-02 Chartered Semiconductor Manufacturing Inc Manufacturing method of conductive wire structure having gap between conductive wires
JP2011039530A (en) 2010-09-08 2011-02-24 Toppan Printing Co Ltd Microcapsule type electrophoresis display panel and method of manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3597885B2 (en) * 1994-06-06 2004-12-08 テキサス インスツルメンツ インコーポレイテツド Semiconductor device
JPH11312733A (en) * 1998-04-28 1999-11-09 Nkk Corp Manufacturing method of integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217293A (en) * 2000-11-27 2002-08-02 Chartered Semiconductor Manufacturing Inc Manufacturing method of conductive wire structure having gap between conductive wires
JP2011039530A (en) 2010-09-08 2011-02-24 Toppan Printing Co Ltd Microcapsule type electrophoresis display panel and method of manufacturing the same

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