KR101688381B1 - Light emitting diode driving circuit reducing sub harmonic oscillation of driving current - Google Patents

Abstract

The LED driving circuit includes a driving transistor, an LED block, a load resistance, an average current holding control section, a sub harmonic oscillation control section, an OR circuit, an inactive section control section, and an SR latch. The LED block drives the LED as the driving current corresponding to the input voltage and outputs the driving current to the drain of the driving transistor. The load resistance includes one terminal connected to the source of the driving transistor and the other terminal to which the ground voltage is applied. The average current holding control section generates a first reset signal for maintaining the average value of the driving current based on the load voltage and the reference voltage of the source of the driving transistor. The sub harmonic oscillation control section generates a second reset signal that keeps the load voltage smaller than the sum of the previous average value of the load voltage and the offset voltage. The OR operator performs an OR operation on the first reset signal and the second reset signal to generate a third reset signal. The inactivation period control unit activates the set signal after the output signal is inactivated and a certain time passes. The SR latch receives the set signal as a set port, receives the third reset signal as a reset port, and provides an output signal to the gate of the driving transistor through the output port.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode (LED) driving circuit for reducing sub-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode (LED) driving circuit, and more particularly, to a light emitting diode driving circuit for reducing sub harmonic oscillation of a driving current.

The illuminance of an LED spotlighted as an illumination and display device is determined by the average current flowing through the LED. The LED driving circuit controls the current flowing through the LED, and can be largely divided into two types according to the driving method. The first method is a linear regulating method that controls the current flowing through the LED to be constant. The second method is a switching regulating method which controls the current flowing through the LED by repeating on / off switching during the operation period. ) Method. Among them, a drive circuit of a switching control system with good efficiency is widely used.

The switching control method can be classified into (1) Buck, Boost and Buck-boost according to the difference between the input voltage and the LED load voltage, (2) the peak current control mode mode or an average current mode. Because the LED load voltage is generally lower than the input voltage, the LED driver circuit usually has a Buck structure, and the average current control mode is mainly used to more precisely control the illuminance of the LED.

The conventional average current control mode may cause a sub harmonic oscillation problem. Under ideal conditions, the ripple of the drive current should remain at one value for the duration of the operation, but sub-harmonic oscillation is defined as the division of the current ripple into two values according to the starting point of the drive current. The sub harmonic oscillation of the driving current changes the peak value of the driving current according to the operation period. When the variation is large, the LED driving circuit operates in the discrete current mode without operating in the continuous current mode It has a problem that can be made. A method for reducing sub harmonic oscillation is needed for more precise and stable drive current control.

It is an object of the present invention to provide an LED driving circuit for reducing sub harmonic oscillation of an LED driving current.

In order to accomplish one object of the present invention, an LED driving circuit includes a driving transistor, an LED block, a load resistance, an average current holding controller, a sub harmonic oscillation controller, an OR circuit, an inactive section controller, and an SR latch . The LED block drives a light emitting diode (LED) as a driving current corresponding to an input voltage, and outputs the driving current to the drain of the driving transistor. The load resistor includes one end connected to the source of the driving transistor and the other end to which a ground voltage is applied. The average current holding control section generates a first reset signal for maintaining an average value of the driving current based on the load voltage and the reference voltage of the source of the driving transistor. The sub harmonic oscillation control unit generates a second reset signal that keeps the load voltage smaller than the sum of the previous average value of the load voltage and the offset voltage. The OR operator performs an OR operation on the first reset signal and the second reset signal to generate a third reset signal. The deactivation period control unit deactivates the output signal and activates a set signal after a predetermined time has elapsed. The SR latch receives the set signal as a set port, receives the third reset signal as a reset port, and provides the output signal to the gate of the driving transistor through an output port.

In one embodiment, the drive current increases linearly with time when the output signal is activated, and the drive current may decrease linearly with time when the output signal is inactive.

In one embodiment, the sub harmonic oscillation control unit may operate when the enable signal is activated.

In one embodiment, when the enable signal is inactive, the first reset signal may be activated in a pulse form whenever the load voltage has a peak value.

In one embodiment, when the enable signal is activated, the first reset signal and the second reset signal may be alternately activated in a pulse form whenever the load voltage has a peak value.

In one embodiment, when the enable signal is activated and the load voltage alternately has a first peak value and a second peak value that is smaller than the first peak value, the load voltage has the first peak value The first reset signal may be activated in a pulse form when the second reset signal is activated in a pulse form and the load voltage has the second peak value.

In one embodiment, the difference between the first peak value and the second peak value may be twice the offset voltage.

In one embodiment, the LED block may include the light emitting diode, the capacitor, the diode, and the inductor. The light emitting diode may have a first terminal coupled to the input voltage through a first node and a second terminal coupled to a third node. The capacitor may have a first end coupled to the first node and a second end coupled to the third node. The diode may have a first end coupled to the first node and a second end coupled to the second node. The inductor may have a first end coupled to the second node and a second end coupled to the third node.

In one embodiment, the sub harmonic oscillation control unit may include a first switch, a second switch, a third switch, a first capacitor, a second capacitor, an adder, and a comparator. The first switch may electrically connect the first terminal receiving the load voltage and the second terminal connected to the first node in response to the first control signal. The second switch may electrically connect the first end connected to the first node and the second end connected to the second node in response to a second control signal. The third switch may electrically connect a first terminal coupled to the first node and a second terminal coupled to the second node in response to a third control signal. The first capacitor may have a first terminal connected to the first node and a second terminal receiving a ground voltage. The second capacitor may have a first terminal coupled to the second node and a second terminal receiving the ground voltage. The adder may add the voltage of the second node and the offset voltage to generate a threshold voltage. The comparator may activate the second reset signal when the load voltage exceeds the threshold voltage.

In one embodiment, the first control signal and the second control signal may have complementary values.

In one embodiment, the third control signal is activated during the initialization interval, and the third control signal may be deactivated after the initialization interval.

In one embodiment, the voltage across the second capacitor may be a previous average value of the load voltage.

In one embodiment, the comparator may output the second reset signal when the enable signal is activated.

In one embodiment, the average current holding control unit may include a reference voltage generator, a first comparator, a second comparator, a third comparator, and an integrator. The reference voltage generator may generate a peak voltage based on the third reset signal and the up / down signal. The first comparator may compare the reference voltage and the load voltage to generate a first count signal. The integrator may integrate the first count signal to generate an integration signal. The second comparator may output a result of comparing the integrated signal with a reference value as the up / down signal. The third comparator may activate the first reset signal in a pulse form when the load voltage is greater than the peak voltage.

In one embodiment, the second comparator activates the up / down signal when the integrated signal is greater than the reference value, and the second comparator activates the up / down signal when the integrated signal is smaller than the reference value. Can be deactivated.

In one embodiment, the reference voltage generator increases the peak voltage when the third reset signal is activated and the up / down signal is activated, and the reference voltage generator generates the third reset signal, / Down < / RTI > signal is deactivated.

The LED driving circuit according to the embodiments of the present invention can reduce the ripple change of the driving current due to the sub harmonic oscillation to generate a more precise and stable driving current.

1 is a block diagram showing an LED driving circuit according to an embodiment of the present invention.
2 is a block diagram showing an LED block included in the LED driving circuit of FIG.
3 is a block diagram showing a sub harmonic oscillation control unit included in the LED driving circuit of FIG.
4 is a block diagram showing an inactivation period control part included in the LED driving circuit of FIG.
5 is a block diagram showing an average current holding control unit included in the LED driving circuit of FIG.
6 is a timing chart showing the operation of the signals of the LED driving circuit of Fig.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Similar reference numerals have been used for the components in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having", etc., are intended to specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, But do not preclude the presence or addition of other features, numbers, steps, operations, elements, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram showing an LED driving circuit according to an embodiment of the present invention.

1, the LED driving circuit 100 includes a driving transistor 170, an LED block 160, a load resistor RL, an average current holding control section 120, a sub harmonic oscillation control section 110, 130, an inactivation period control unit 140, and an SR latch 150. [

The LED block 160 drives the light emitting diode (LED) as the driving current ILED corresponding to the input voltage VIN and outputs the driving current ILED to the drain of the driving transistor 170. The LED block 160 will be described later with reference to Fig.

The load resistor RL includes one end connected to the source of the driving transistor 170 and the other end to which the ground voltage GND is applied. The average current holding control section 120 generates a first reset signal RST1 that holds the average value of the driving current ILED based on the load voltage VL of the source of the driving transistor 170 and the reference voltage VREF do. The average current holding control unit 120 will be described later with reference to Fig.

The sub harmonic oscillation control section 110 generates a second reset signal RST2 that keeps the load voltage VL smaller than the value obtained by adding the offset voltage VOS to the previous average value of the load voltage VL. The OR operator 130 performs a logical sum operation on the first reset signal RST1 and the second reset signal RST2 to generate a third reset signal RST3. The inactivation period control unit 140 activates the set signal SET after the output signal QSIG is inactivated and a predetermined time elapses. The SR latch receives the set signal SET as a set port SP and receives the third reset signal RST3 as a reset port RP to output the output signal QSIG through the output port QP to the driving transistor TR. (170). The sub harmonic oscillation control unit 110 will be described later with reference to FIG. 3, and the inactivity period control unit 140 will be described later with reference to FIG.

In one embodiment, when the output signal QSIG is activated, the drive transistor 170 is turned on and the drive current ILED generated through the LED block 160 increases linearly with time do. In one embodiment, when the output signal QSIG is inactive, the driving transistor 170 is turned off and the driving current ILED generated through the LED block 160 is linearly reduced in proportion to time do.

In one embodiment, the sub harmonic oscillation control unit 110 may operate when the enable signal EN is activated.

2 is a block diagram showing an LED block included in the LED driving circuit of FIG.

Referring to FIG. 2, the LED block 160 may include a light emitting diode (LED), a capacitor C1, a diode DIODE, and an inductor L. Referring to FIG.

The input voltage VIN is applied through the first node N1. One end of the light emitting diode (LED) is connected to the first node (N1), and the other end of the light emitting diode (LED) is connected to the third node (N3). One end of the capacitor C1 is connected to the first node N1 and the other end of the capacitor C1 is connected to the third node N3. One end of the diode DIODE is connected to the first node N1 and the other end of the diode DIODE is connected to the second node N2. One end of the inductor L is connected to the second node N2 and the other end of the inductor L is connected to the third node N3.

When the driving transistor 170 is turned on, the driving current ILED linearly increases in proportion to time, and when the driving transistor 170 is turned off, the driving current ILED is linearly proportional to the time . ≪ / RTI >

3 is a block diagram showing a sub harmonic oscillation control unit included in the LED driving circuit of FIG.

3, the sub harmonic oscillation control unit 110 includes a first switch SW1, a second switch SW2, a third switch SW3, a first capacitor CS, a second capacitor CH, (111) and a comparator (112).

The first switch SW1 may electrically connect the first terminal receiving the load voltage VL and the second terminal connected to the first node N4 in response to the first control signal CS1. The second switch SW2 may electrically connect the first end connected to the first node N4 and the second end connected to the second node N5 in response to the second control signal CS2. The third switch SW3 may electrically connect the first end connected to the first node N4 and the second end connected to the second node N5 in response to the third control signal SW3. The first capacitor CS may have a first terminal connected to the first node N4 and a second terminal receiving the ground voltage GND. The second capacitor CH may have a first terminal connected to the second node N5 and a second terminal receiving the ground voltage GND. The adder 111 can generate the limit voltage VSHP by adding the voltage VSH and the offset voltage VOS of the second node N5. The comparator 112 can activate the second reset signal RST2 when the load voltage VL exceeds the limit voltage VSHP.

In one embodiment, the first control signal CS1 and the second control signal CS2 may have a complementary value. In one embodiment, the third control signal SW3 is activated during the initialization period, and the third control signal SW3 may be inactive after the initialization period.

The first control signal CS1 and the third control signal SW3 are activated and the load voltage VL is applied to both ends of the first capacitor CS and the second capacitor CH during the initialization period.

When the initialization period ends at t = 0 and the first control signal CS1 is activated and the second control signal CS2 is deactivated at t = T0, both ends of the first capacitor CS are loaded with a load at t = T0 The voltage VL is applied. When the first control signal CS1 is deactivated and the second control signal CS2 is activated at t = T1, both ends of the first capacitor CS and both ends of the second capacitor CH are loaded with a load at t = T0 The first average value of the voltage VL and the load voltage VL at t = T1 is stored. When the first control signal CS1 is activated and the second control signal CS2 is deactivated at t = T2, the load voltage VL at t = T2 is applied to both ends of the first capacitor CS. both ends of the first capacitor CS and both ends of the second capacitor CH are connected to the first average value and the second average value at both ends of the first capacitor CS when the first control signal CS1 is deactivated and the second control signal CS2 is activated at t = The second average value of the load voltage VL at t = T2 is stored. As a result, the voltage across the second capacitor CH may be the previous average value of the load voltage VL.

The comparator 112 can activate the second reset signal RST in a pulse form when the enable signal EN is activated and the load voltage VL exceeds the threshold voltage VSHP.

4 is a block diagram showing an inactivation period control part included in the LED driving circuit of FIG.

4, the inactivation period control unit 140 includes an inverter 141, a current source 142, a fourth switch SW4, a fifth switch SW5, a second capacitor C2, and a comparator 143 can do. The inactivity period control unit 140 may be implemented in a structure different from that of FIG.

The inverter 141 receives the output signal QSIG and generates an inverted output signal IQSIG. The power source voltage VDD is applied to one terminal of the current source 142 and the other terminal of the current source 142 is connected to one terminal of the fourth switch SW4 and the other terminal of the fourth switch SW4 is connected to the terminal of the sixth Node N6, and the fourth switch SW4 connects one terminal to the other terminal in response to the inverted output signal IQSIG. The ground voltage GND is applied to one terminal of the fifth switch SW5 and the other terminal of the fifth switch SW5 is connected to the sixth node N6 and the fifth switch SW5 receives the output signal QSIG ) To connect one end and the other end. The ground voltage GND is applied to one terminal of the second capacitor C2 and the other terminal of the second capacitor C2 is connected to the sixth node N6. The positive input terminal of the comparator 143 is connected to the sixth node N6 and the bias voltage VBIAS is applied to the input terminal of the comparator 143. The comparator 143 outputs the set signal SET.

When the output signal QSIG is activated, both terminals of the fourth switch SW4 are electrically disconnected and both terminals of the fifth switch SW5 are electrically connected so that the voltage across the second capacitor C2 is 0V Is initialized. Thereafter, when the output signal QSIG is inactivated, both ends of the fourth switch SW4 are electrically connected and both ends of the fifth switch SW5 are electrically disconnected and the bias current Charge is accumulated in the second capacitor C2 by the IBIAS and the voltage of the sixth node N6 connected to the other end of the second capacitor C2 increases in proportion to the time. The comparator 143 can activate the set signal SET in a pulse form when the voltage of the sixth node N6 becomes larger than the bias voltage VBIAS. In one embodiment, the predefined time may be determined by the ratio of the bias voltage (VBIAS) and the bias current (IBIAS).

5 is a block diagram showing an average current holding control unit included in the LED driving circuit of FIG.

5, the average current holding control unit 120 may include a reference voltage generator REFGEN, a first comparator CMP1, a second comparator CMP2, a third comparator CMP3, and an integrator INT have. The average current maintenance controller 120 may be implemented in a structure different from that of FIG.

The reference voltage generator REFGEN may generate the peak voltage VPEAK based on the third reset signal RST3 and the up / down signal UDS. The first comparator CMP1 may generate a value obtained by subtracting the load voltage VL from the reference voltage VREF as the first count signal COUT1. The integrator INT may integrate the first count signal COUT1 to produce the integral signal IOUT. The second comparator CMP2 may output the result of the comparison of the integral signal IOUT with the reference value as the up / down signal UDS. The third comparator CMP3 may activate the first reset signal RST1 in a pulse form when the load voltage VL is larger than the peak voltage VPEAK. In one embodiment, the reference value may be 0V.

In one embodiment, the second comparator CMP2 activates the up / down signal UDS when the integration signal IOUT is greater than the reference value and the second comparator CMP2 activates the up / The up / down signal UDS can be deactivated.

In one embodiment, the reference voltage generator REFGEN increases the peak voltage VPEAK when the third reset signal RST3 is activated and the up / down signal UDS is activated, and the reference voltage generator REFGEN It is possible to reduce the peak voltage VPEAK when the third reset signal RST3 is activated and the up / down signal UDS is inactivated.

6 is a timing chart showing the operation of the signals of the LED driving circuit of Fig.

6, when the enable signal EN is inactivated from the first time point 211 to the third time point 213, the load voltage VL has a first peak value at the first time point 211 , And the load voltage (VL) has a second peak value at the third time point (213). In other words, a sub harmonic oscillation phenomenon occurs in the drive current ILED indicated by the load voltage VL. In this case, the first reset signal RST1 may be activated in a pulse form whenever the load voltage VL has a peak value (211, 213).

The limit voltage VSHP is stabilized from the third time point 213 to the seventh time point 217 and the limit voltage VSHP after the seventh time point 217 is stabilized.

When the enable signal EN is activated, the first reset signal RST1 and the second reset signal RST2 alternate each time the load voltage VL has a peak value (217, 219, 221, 223) It can be activated in pulse form. More specifically, when the enable signal EN is activated and the load voltage VL is higher than the third peak value at the seventh time point 217 and the eleventh time point 221 and the third peak value and the ninth time point 219 and the thirteenth time point 223 The second reset signal RST2 is activated in the form of a pulse at the seventh time point 217 and the eleventh time point 221 and the ninth time point 219 and the thirteenth time point 223 are activated in a pulse form, The first reset signal RST1 may be activated in a pulse form.

The third peak value at the seventh time point 217 and the third peak value at the ninth time point 219 and the thirteenth time point 221 at the seventh time point 217 223) is set to twice the offset voltage (VOS). It can be seen that the sub harmonic oscillation of the load voltage VL and the drive current ILED is reduced before the third time 213.

The LED driving circuit according to embodiments of the present invention can be applied to a lighting device or a display device that uses an LED electrically. Specifically, the LED driving circuit can be applied to a lighting apparatus such as a lamp using an LED and an automobile head lamp, and can be applied to a display apparatus included in a monitor, a notebook, a TV, and a smart phone.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It will be understood that the invention may be modified and varied without departing from the scope of the invention.

Claims (16)

A driving transistor;
An LED block driving a light emitting diode (LED) as a driving current corresponding to an input voltage and outputting the driving current to a drain of the driving transistor;
A load resistor including one end connected to a source of the driving transistor and the other end to which a ground voltage is applied;
An average current holding control unit for generating a first reset signal for maintaining an average value of the driving current based on a load voltage and a reference voltage of the source of the driving transistor;
A sub harmonic oscillation control unit for generating a second reset signal for maintaining the load voltage smaller than a sum of the previous average value and the offset voltage of the load voltage;
An OR operator for performing a logical sum operation on the first reset signal and the second reset signal to generate a third reset signal;
An inactivation period control unit for activating a set signal after the output signal is inactivated and a predetermined time elapses; And
And an SR latch that receives the set signal as a set port, receives the third reset signal as a reset port, and provides the output signal to the gate of the driving transistor through an output port,
Wherein the sub harmonic oscillation control unit comprises:
A first switch electrically connecting a first terminal receiving the load voltage and a second terminal connected to the first node in response to a first control signal;
A second switch electrically connecting the first end connected to the first node and the second end connected to the second node in response to a second control signal;
A third switch electrically connecting a first end connected to the first node and a second end connected to the second node in response to a third control signal;
A first capacitor having a first terminal coupled to the first node and a second terminal receiving a ground voltage;
A second capacitor having a first terminal coupled to the second node and a second terminal receiving the ground voltage;
An adder for adding a voltage of the second node and the offset voltage to generate a threshold voltage; And
And a comparator for activating said second reset signal when said load voltage exceeds said threshold voltage. The method according to claim 1,
Wherein when the output signal is activated, the drive current linearly increases in proportion to time,
Wherein the drive current is linearly decreased in proportion to time when the output signal is inactivated. The method according to claim 1,
And the sub harmonic oscillation control unit operates when the enable signal is activated. The method of claim 3,
Wherein the first reset signal is activated in a pulse form whenever the load voltage has a peak value when the enable signal is inactivated. The method of claim 3,
Wherein when the enable signal is activated, the first reset signal and the second reset signal are alternately activated in a pulse form whenever the load voltage has a peak value. The method of claim 3,
When the enable signal is activated and the load voltage has a first peak value and a second peak value alternately smaller than the first peak value, when the load voltage has the first peak value, Is activated in a pulse form and the first reset signal is activated in a pulse form when the load voltage has the second peak value. The method according to claim 6,
Wherein the difference between the first peak value and the second peak value is twice the offset voltage. The LED module according to claim 1, wherein the LED block
The light emitting diode having a first terminal receiving the input voltage through a first node and a second terminal coupled to a third node;
A capacitor having a first end coupled to the first node and a second end coupled to the third node;
A diode having a first terminal coupled to the first node and a second terminal coupled to the second node; And
An inductor having a first terminal coupled to the second node and a second terminal coupled to the third node. delete The method according to claim 1,
Wherein the first control signal and the second control signal have complementary values. The method according to claim 1,
During the initialization period, the third control signal is activated,
And the third control signal is inactivated after the initialization period. The method according to claim 1,
Wherein a voltage across the second capacitor is a previous average value of the load voltage. The method according to claim 1,
And the comparator outputs the second reset signal when the enable signal is activated. The apparatus of claim 1, wherein the average current maintenance controller
A reference voltage generator for generating a peak voltage based on the third reset signal and the up / down signal;
A first comparator for comparing the reference voltage with the load voltage to generate a first count signal;
An integrator for integrating the first count signal to generate an integrated signal;
A second comparator that outputs a result of comparing the integrated signal with a reference value as the up / down signal; And
And a third comparator for activating the first reset signal in a pulse form when the load voltage is greater than the peak voltage. 15. The method of claim 14,
And the second comparator activates the up / down signal when the integrated signal is greater than the reference value,
And the second comparator deactivates the up / down signal when the integrated signal is smaller than the reference value. 16. The method of claim 15,
The reference voltage generator increases the peak voltage when the third reset signal is activated and the up / down signal is activated,
The reference voltage generator decreasing the peak voltage when the third reset signal is activated and the up / down signal is inactive.

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