KR101687104B1 - Method and apparatus of V-Sync Delay Calculation - Google Patents
Method and apparatus of V-Sync Delay Calculation Download PDFInfo
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- KR101687104B1 KR101687104B1 KR1020150078501A KR20150078501A KR101687104B1 KR 101687104 B1 KR101687104 B1 KR 101687104B1 KR 1020150078501 A KR1020150078501 A KR 1020150078501A KR 20150078501 A KR20150078501 A KR 20150078501A KR 101687104 B1 KR101687104 B1 KR 101687104B1
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- South Korea
- Prior art keywords
- vertical synchronization
- synchronization delay
- display
- vertical
- frame locking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
- H04N5/10—Separation of line synchronising signal from frame synchronising signal or vice versa
Abstract
A method for calculating a vertical synchronization delay is provided. A method of calculating a vertical synchronization delay according to an exemplary embodiment of the present invention includes calculating a vertical synchronization delay for an input signal having a frequency different from each other, the method comprising: setting a layout and storing a set value; Calculating a vertical synchronization delay based on the capture area information of the input signal and an input signal of a display pipeline to perform frame locking, comparing the frequencies with each other, And increasing the vertical synchronization delay in accordance with the set vertical synchronization delay flag.
Description
The present invention relates to a method and apparatus for calculating a vertical synchronization delay, and more particularly to a vertical synchronization delay calculation method and apparatus for implementing frame locking in a PBP mode.
Generally, in the case of a currently used scaler, if the vertical synchronization (V-Sync) of the signal output to the display does not match the vertical synchronization of the input signal, Overlapping frame tearing or a frame drop phenomenon in which an image flows from the top to the bottom of the screen occurs.
In order to correct this, the task of adjusting the vertical synchronization of the output signal to the vertical synchronization of the input signal is called frame locking. At this time, if the input frame rate is slower than the output frame rate for frame locking of the input signal and the output signal, a part of the input frame is repeatedly inserted to prevent frame tearing (frame repeat) .
In addition, when the input frame rate is faster than the output frame rate, a part of the input frame is skipped (frame skip, frame drop) to synchronize the input signal and the output signal, Solves the problem of image due to inconsistency.
The display period is adjusted to the capture period using the frame omission or the frame repeat insertion. The same image buffer is used for the output and the input. The frame buffer memory Some delay is required before reading data from the output before completing the data writing. The delay at this time is referred to as a vertical synchronization delay (V-sync delay).
Meanwhile, the scaler supports various multi-layout such as picture-in-picture (PIP), picture-on-picture (POP) and picture-by-picture When a signal having a different frequency (for example, one frequency is 50 Hz and the other frequency is 60 Hz) is input, when the conventional vertical synchronization delay calculation method is used, There is a problem that frame tearing occurs at the top of the screen.
According to an aspect of the present invention, there is provided a method of calculating a vertical synchronization delay that can easily implement frame locking even when a signal having a different frequency is input in a PBP mode .
According to an aspect of the present invention, there is provided a method of calculating a vertical synchronization delay for an input signal having a different frequency. The vertical synchronization delay calculation method includes the steps of: setting a layout and storing a set value; setting a vertical synchronization delay flag by comparing vertical frequencies of input signals; Calculating a vertical synchronization delay according to an input signal of a display pipeline to be performed, determining whether the vertical synchronization delay flag is set, and increasing the vertical synchronization delay according to the set vertical synchronization delay flag .
In one embodiment, the step of calculating the vertical synchronization delay may calculate a larger value of the difference between the write start time and the read start time and the difference between the write end time and the read end time as the vertical synchronization delay value .
In one embodiment, increasing the vertical synchronization delay comprises: calculating the read end time (DisplayEnd) according to DisplayEnd = DisplayBottom + DisplayTop when the vertical synchronization delay flag is set, wherein DisplayBottom is a display pipeline (Display Pipeline Image Height), and DisplayTop may be a display Pipeline Image Top (Pipeline Image Top) to be output to the display pipeline.
In one embodiment, when the vertical synchronization delay flag is unset, the vertical synchronization delay may not be increased.
According to an aspect of the present invention, there is provided an apparatus for calculating a vertical synchronization delay for an input signal having a frequency different from each other connected to a display. The vertical synchronization delay calculation apparatus includes a buffer for storing a signal to be output to the display, a vertical synchronization delay flag setting stage for setting a vertical synchronization delay flag by comparing vertical frequencies of input signals according to a layout set by the user, And a frame locking operation unit for calculating a vertical synchronization delay according to the capture area information of the input signal and an input signal of a display pipeline for performing frame locking and increasing the vertical synchronization delay according to the set vertical synchronization delay flag.
In one embodiment, the frame locking operation unit may calculate a larger value of the difference between the write start time and the read start time and the difference between the write end time and the read end time as the vertical synchronization delay value.
In one embodiment, the frame locking operation unit calculates the read end time (DisplayEnd) according to DisplayEnd = DisplayBottom + DisplayTop when the vertical synchronization delay flag is set, where DisplayBottom is a value of the image to be output to the display pipeline The display length is a vertical length (Display Pipeline Image Height), and the DisplayTop can disable the vertical synchronization delay flag, which is the top of the image to be output to the display pipeline (Display Pipeline Image Top).
In one embodiment, the frame locking calculation unit may not increase the vertical synchronization delay when the vertical synchronization delay flag is unset.
The vertical synchronization delay calculation method according to an embodiment of the present invention can prevent frame tearing by selectively implementing frame locking even when signals having different frequencies are input in the PBP mode.
1 is a flowchart of a method of calculating a vertical synchronization delay according to an embodiment of the present invention.
2 is a diagram illustrating an image area for explaining a method of calculating a vertical synchronization delay according to an embodiment of the present invention.
3 is a diagram illustrating a display area for explaining a method of calculating a vertical synchronization delay according to an embodiment of the present invention.
4 is a simplified block diagram of a vertical synchronization delay calculation apparatus according to an embodiment of the present invention.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.
2 is a diagram illustrating an image area for explaining a method of calculating a vertical synchronization delay according to an exemplary embodiment of the present invention. FIG. 4 is a diagram illustrating a display area for explaining a method of calculating a vertical synchronization delay according to an embodiment of the present invention; Hereinafter, a method of calculating a vertical synchronization delay according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.
As shown in FIG. 1, the vertical synchronization
More specifically, the user first sets the screen layout to PBP (step S110), and stores the current user setting in the memory (step S120). At this time, when the user sets the layout to PBP, the display pipe line 0 & 1 of the scaler is used at the same time, and the capture size is variable in the main window. On the other hand, the initial data of the input signal and the display pipeline (display pipe line 0 & 1) are set to simultaneously display the two images.
Next, the vertical frequencies of the two input signals are compared (step S130).
It is determined whether or not the vertical frequencies of the two input signals coincide with each other according to the comparison result of step 130 (step S140).
If it is determined in step S140 that the vertical frequencies of the two input signals are different, the vertical synchronization delay flag of the PBP mode is set (step S141).
If it is determined in step S140 that the vertical frequencies of the two input signals are the same, the vertical synchronization delay flag of the PBP mode is cleared (step S142).
Next, a vertical synchronization delay is calculated as a frame locking value according to the capture area information of the input signal and the input signal of the display pipeline to perform frame locking (step S150).
At this time, since the capture size of the main window is variable in the PBP mode, the setting of the write end time is not sufficient by only the vertical data start information (VDataEnableStart) of the display. Therefore, the vertical synchronization delay value is adjusted depending on whether the vertical synchronization delay flag is set or not. Here, the formula for calculating the frame lock value will be described in detail below.
The Captured Image Region shown in FIG. 2 has values of CAPL, CAPT, CAPW, and CAPH, and is used to determine an input capture area of the currently input image. The display pipeline region 0 & 1 shown in FIG. 3 has values of PIPE0L, PIPE0T, PIPE0W, PIPE0H, PIPE1L, PIPE1T, PIPE1W and PIPE1H. And determines the area to be output through the display pipeline. In this case, the CAPL (Image Capture Left Pixel) may be a number of pixels to wait for capturing each line of the input image after the horizontal synchronization (Hsync), and CAPT (Image Capture Top Line) It may be the number of lines to wait to capture an image.
Also, CAPW (Image Capture Width) represents the number of pixels captured per line after CAPL and CAPH (Image Capture Height) represents the total number of lines captured after CAPT of each image line from vertical sync (VSync).
PIPE0 & 1L (Display Pipeline 0 & 1 Image Left Edge) represents the left edge of the pipeline at full display resolution, and PIPE0 & 1T (Display Pipeline 0 & 1 Image Top) represents the top edge of the pipeline at full display resolution .
Also, PIPE0 & 1W (Display Pipeline 0 & 1 Image Height) represents the horizontal length of the image to be output in relation to the entire display resolution, and PIPE0 & 1H (Display Pipeline 0 & 1 Image Height) represents the vertical length of the image to be outputted in relation to the entire display resolution.
In order to calculate the frame lock value, the capture area information and input signal information of the display pipeline to be subjected to frame locking are required.
First, a frame locking input vertical synchronization (InputVFreq) is calculated using an input signal of a display pipeline.
Next, it is checked whether the output of the display is within a certain range according to the calculated input vertical frequency (InputVFreq). At this time, the output range of the display may be 127.5 to 148.5 MHz.
Next, an input horizontal period (InputHPer) is calculated according to Equation (1) using the input vertical synchronization, the display clock (DCLK), and the display pipeline vertical VTotal.
Equation 1
InputHPer = DCLK / (1 / InputVFreq * VTotal)
Next, the display vertical frequency (DisplayVFreq) is set equal to the input vertical frequency. Then, the horizontal period (DisplayHPer) of the display pipeline is calculated according to the following equation (2) using the display clock, the vertical period of the display, and the display vertical frequency.
Equation 2
DisplayHPer = ((DCLK / PanelVPeriod) * 100) / DisplayVFreq
Next, it is determined whether or not the horizontal period (DisplayHPer) of the display pipeline is within the horizontal period range of the display to be used. If the display period is larger or smaller than the display value, it is set to the maximum or minimum value of the display horizontal period range.
Thereafter, the vertical line VLine is calculated using the horizontal period DisplayHPer, the display vertical frequency DisplayVFreq, and the display clock DCLK of the display pipeline, and the calculated vertical line VLine is used to calculate And calculates a vertical period (DisplayVPer). At this time, the calculated vertical line (VLine) must be within the vertical period (PanelVPer) range of the display to be used for frame locking.
Next, the writing start time (InputStart) (writing start time) of the frame buffer memory is determined according to the following Equation 3 using the image capturing top line (InputTop), input horizontal period (InputHPer), and display horizontal period (DisplayHPer) do. At this time, the image capturing top line (InputTop) means a capturing start line of an image to be displayed.
Equation 3
InputStart = (InputTop + InputHPer) / DisplayHPer
In addition, the writing end time (Input End) of the frame buffer memory is determined according to Equation (4) using an image capture bottom line (InputBottom), an input horizontal period (InputHPer), and a display horizontal period (DisplayHPer) . At this time, the image capture bottom line (InputBottom) means the total number of lines of the captured image.
Equation 4
InputEnd = (InputBottom + InputHPer) / DisplayHper
In addition, an input vertical period (InputVPer) is determined according to Equation (5) using input vertical frequency (InputVFreq), display horizontal period (DisplayHPer) and display clock (DCLK) information.
Equation 5
InputVPer = DCLK / (1 / (InputVFreq * DisplayHPer))
On the other hand, the display start time (DisplayStart) of the frame buffer memory is calculated according to Equation (6) using the memory top line (DisplayTop) of the image to be displayed and the vertical data start of the display to be used .
Equation 6
DisplayStart = DisplayTop + Panel VDataEnableStart
The frame buffer memory read end time (Display End) is determined according to Equation (7) using the memory bottom line of the image to be displayed and the vertical start of the display to be used do.
Equation 7
DisplayEnd = DisplayBottom + Panel VDataEnableStart.
The vertical synchronization delay (V-Sync) is calculated according to the following equation (8) by the difference between the write start time (InputStart) and the read start time (DisplayStart) calculated as described above or the difference between the write end time (InputEnd) Delay.
Equation 8
V-Sync Delay = Max ((InputStart - DisplayStart), (InputEnd - DisplayEnd))
Here, the V-Sync Delay is determined by the difference between the write start start (InputStart) and the read start start (DisplayStart) and the difference between the write end time (InputEnd) and the read end time (DisplayEnd) At this time, it can not be 0 or less, and the read end time of the next frame buffer memory must not exceed the display end time of the next image start line.
Next, it is determined whether or not the vertical synchronization delay flag is set (step S160). If the vertical synchronization delay flag is set, that is, if the vertical frequencies of the two signals are different, the vertical synchronization delay is increased (step S161). More specifically, in order to increase the vertical synchronization delay, the read end time (DisplayEnd) is increased by using the memory top line (DisplayTop) of the image to be displayed as shown in the following equation (9).
Equation 9
DisplayEnd = DisplayBottom + DisplayTop
If it is determined in step S160 that the vertical synchronization delay is not set, that is, if the vertical frequencies of the two signals are the same, the frame locking value derived in step S150 is used without increasing the vertical synchronization delay.
Hereinafter, a vertical synchronization delay calculation apparatus according to an embodiment of the present invention will be described in detail with reference to FIG. 4 is a block diagram of a vertical synchronization delay calculation apparatus (hereinafter referred to as a scaler) according to an embodiment of the present invention. The
The
The frame locking
The vertical synchronization delay
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
500: Vertical synchronization delay calculation device (scaler)
510: buffer 520: frame locking operation unit
530: Vertical synchronization delay flag setting stage
Claims (8)
Storing a layout setting value in a buffer,
Comparing vertical frequencies of input signals stored in the buffer with each other to set a vertical synchronization delay flag at a vertical synchronization delay flag setting stage,
Calculating a vertical synchronization delay in a frame locking operation unit according to capture area information of the input signal and an input signal of a display pipeline to perform frame locking;
Determining whether the vertical synchronization delay flag is set in the frame locking calculation unit, and
And increasing the vertical synchronization delay by the frame locking operation unit according to the set vertical synchronization delay flag.
Wherein the step of calculating the vertical synchronization delay comprises:
Wherein a difference between the write start time and the read start time and a difference between the write end time and the read end time are calculated as the vertical synchronization delay value.
The step of increasing the vertical synchronization delay may include calculating the read end time DisplayEnd according to DisplayEnd = DisplayBottom + DisplayTop when the vertical synchronization delay flag is set, wherein DisplayBottom is a length of the image to be output to the display pipeline Wherein the Display Pipeline Image Height is a Display Pipeline Image Height and the DisplayTop is a Display Pipeline Image Top.
And does not increase the vertical synchronization delay when the vertical synchronization delay flag is unset.
A buffer for storing a signal for output to the display,
A vertical synchronous delay flag setting stage for setting a vertical synchronous delay flag by comparing vertical frequencies of input signals according to a layout set by a user, and
And a frame locking operation unit for calculating a vertical synchronization delay in accordance with the capture area information of the input signal and an input signal of a display pipeline to perform frame locking and to increase the vertical synchronization delay according to the set vertical synchronization delay flag, Vertical synchronization delay calculation device.
Wherein the frame locking calculation unit calculates a difference between the write start time and the read start time and a larger value of the difference between the write end time and the read end time as the vertical synchronization delay value.
The frame locking operation unit calculates the read end time DisplayEnd according to DisplayEnd = DisplayBottom + DisplayTop when the vertical synchronization delay flag is set, wherein DisplayBottom is a display length of the display pipeline Image Height), and DisplayTop unset the vertical synchronization delay flag, which is the top of the image to be output to the display pipeline (Display Pipeline Image Top).
Wherein the frame locking calculation unit does not increase the vertical synchronization delay when the vertical synchronization delay flag is unset.
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| KR1020150078501A KR101687104B1 (en) | 2015-06-03 | 2015-06-03 | Method and apparatus of V-Sync Delay Calculation |
| PCT/KR2016/005897 WO2016195409A1 (en) | 2015-06-03 | 2016-06-03 | Vertical synchronization delay calculating method and apparatus |
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| KR20070047729A (en) | 2006-11-27 | 2007-05-07 | 엠텍비젼 주식회사 | Method for outputting deferred vertical synchronous signal and image signal processor performing the method |
| KR101861723B1 (en) * | 2011-12-20 | 2018-05-30 | 삼성전자주식회사 | Devices and method of adjusting synchronization signal preventing tearing and flicker |
| KR102036034B1 (en) * | 2012-10-22 | 2019-10-24 | 주식회사 오리온 | Apparatus and Method for Buffering Signal Delay between Display Device in Multi-Display Environment |
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