JP2012169727A - Image signal processor and image signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a judder in the movement of an image from becoming conspicuous, that is generated by frame synchronization processing and gives discomfort to a user when performing the multi-screen displaying of multiple images on the same display.SOLUTION: A frame synchronization part includes: a synchronization timing detection part for detecting scenes suitable for repeat and skip; and an address control part for controlling writing and reading addresses with respect to a frame memory, based on timing which is reported from the synchronization timing detection part. Thus, the frame synchronization part adjusts the timing to repeat or skip a frame to be read from the frame memory. Besides, the frame synchronization part includes an interpolation frame generation part for generating the interpolation frames of an intermediate phase, based on multiple temporally continuous frames. The peripheral frames of the repeat or skip are replaced with the interpolation frames thereby to allow frame intervals to be temporally substantially equal.

Description

  The present invention relates to a video signal processing apparatus and method for smoothing the motion of a video when a plurality of videos are displayed on a multi-screen on the same display.

  In recent years, in a DTV (digital television) or the like, multi-screen display that simultaneously displays a plurality of videos on the same display is becoming common. The large screen and high definition of the display also help, and the user can enjoy simultaneous display such as multi-channel simultaneous display and playback of content provided through broadcasting and recording equipment or an external network.

  When a plurality of video sources are displayed on a multi-screen, only one synchronization signal is used to display the screen. Therefore, in DTV, video is displayed in synchronization with one of the vertical synchronization signals of the plurality of video sources. There is a need. As the video source to be selected at this time, the video having the largest screen size and the video that the user wants to watch most (hereinafter referred to as the main video) is selected. It is necessary to display another video (hereinafter referred to as sub-video) on the basis of the vertical synchronization signal (hereinafter referred to as V-sync) of the main video. In a PC or the like, there are cases where all videos are displayed based on V synchronization generated by free-running (Patent Documents 1 and 2).

  At this time, since the V synchronization of the main video and the sub video has different frequencies, a process called frame synchronization (hereinafter referred to as frame synchronization) is performed in order to display the sub video in synchronization with the main video. It is common. In frame synchronization, the sub-picture is synchronized by reading out the sub-picture frame in accordance with V synchronization of the main picture. As a result, the sub-picture frames are thinned out (skip processing) or displayed repeatedly (repeat processing) at regular intervals. For example, when V synchronization of the main video is 59.94 Hz and V synchronization of the sub video is 60.00 Hz, the sub video skips one frame every about 1000 frames (about 16.7 seconds).

  However, since this frame synchronization process is performed by skipping or repeating frames at a fixed period, frame reproduction of the displayed video is discontinuous in time. For example, in a scene in which the camera pans or tilts for a certain period of time, there is a problem in that the motion of the video is unstable (judder), giving the user a sense of incongruity and impairing viewing quality.

JP-A-2005-341132 JP 2007-271848 A

  Therefore, the present invention has an object to reduce the judder caused by the frame synchronization process and to display a smooth and high-quality image when a plurality of images are displayed simultaneously or in a multi-screen display.

  In order to solve the above problems, a video signal processing apparatus according to the present invention is a video signal processing apparatus that generates a display screen for simultaneously displaying a plurality of videos on a screen, and inputs a plurality of video signals of the videos. Display synchronization signal that is a synchronization signal for displaying the display screen on the basis of a video input unit and a free-run vertical synchronization signal or a vertical synchronization signal in one of the plurality of video signals. A display synchronization generation unit that generates a plurality of video signals input from the video input unit, a frame synchronization unit that outputs in synchronization with the display synchronization signal, and a plurality of video signals output from the frame synchronization unit. A multi-screen composition unit that synthesizes and generates the display screen, and the frame synchronization unit is the same as the display synchronization signal among the plurality of video signals. A synchronization timing detection unit that determines an appropriate period for eliminating the synchronization shift is provided for a video signal in which a shift occurs, and a synchronization shift occurs with the display synchronization signal during the period determined by the synchronization timing detection unit. For the video signal, the frame at the same time is repeatedly output or the frame is thinned and output to eliminate the synchronization shift.

  The video signal processing apparatus of the present invention is a video signal processing apparatus that generates a display screen for simultaneously displaying a plurality of videos on a screen, and a video input unit that inputs a plurality of video signals of the video, Display synchronization that generates a display synchronization signal, which is a synchronization signal for displaying the display screen, based on a free-running vertical synchronization signal or a vertical synchronization signal in one of the plurality of video signals. A generating unit; a frame synchronization unit that outputs the plurality of video signals input from the video input unit in synchronization with the display synchronization signal; and a combination of the plurality of video signals output from the frame synchronization unit. A multi-screen synthesis unit that generates a video screen, wherein the frame synchronization unit is a video signal that is out of synchronization with the display synchronization signal among the plurality of video signals On the other hand, an interpolation frame generation unit that generates an intermediate-phase interpolation frame from a plurality of temporally continuous frames, and a period for eliminating the synchronization shift with respect to the video signal in which the synchronization shift from the display synchronization signal occurs In this case, the synchronization shift is eliminated by replacing the video signal with the intermediate frame generated by the interpolation frame generation unit.

  According to the present invention, when a plurality of videos are displayed on a multi-screen, judder due to frame synchronization processing is reduced, and a smooth and high-quality video display is possible.

Configuration diagram of video signal processing apparatus according to an embodiment Configuration diagram of frame synchronization unit in embodiment 1 Explanatory drawing of address control in conventional frame synchronization Explanatory drawing of address control in the embodiment Configuration diagram of frame synchronization unit in embodiment 2 Explanatory drawing of frame replacement in the second embodiment Flowchart of frame synchronization processing in the first embodiment Flowchart representing elimination of synchronization error in the second embodiment

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  As shown in FIG. 1, the video signal processing apparatus according to the embodiment includes a video input unit 100, a display synchronization generation unit 200, a frame synchronization unit 300, a frame memory 400, a multi-screen synthesis unit 500, and a video display unit 600. The

  A plurality of video signals are input from the video input unit 100 and output to the display synchronization generation unit 200 and the frame synchronization unit 300.

  The display synchronization generation unit 200 generates display V synchronization that is a display synchronization signal for displaying the input video signal. As the display V synchronization signal, vertical signal synchronization (Vsync synchronization, hereinafter referred to as V synchronization) can be used from one of the input video signals. Further, a variable clock is generated by a clock generator (not shown), and a clock that is gradually changed until a predetermined display synchronization signal frequency (for example, 60 Hz) is reached is used as a display V synchronization signal. Can be used. A synchronization signal generated by gradually changing the clock in this way is called free-run V synchronization.

  The frame synchronization unit 300 temporarily stores a plurality of video signals input from the video input unit 100 in the frame memory 400, and stores them in the frame memory 400 in synchronization with the display V synchronization generated by the display synchronization generation unit 200. The plurality of video signals thus read out are read out. The frame synchronization unit 300 outputs the read video signal to the multi-screen composition unit 500.

  The multi-screen composition unit 500 arranges a plurality of video signals output from the frame synchronization unit 300 on the display screen, and outputs the synthesized video to the video display unit 600.

  The video display unit 600 displays the video output from the multi-screen composition unit 500.

  Next, the frame synchronization unit 300 will be described in detail.

(Embodiment 1)
FIG. 2 is a configuration diagram of the frame synchronization unit 300 according to the first embodiment.

  The frame synchronization unit 300 includes a synchronization timing detection unit 310 and an address control unit 320. The synchronization timing detection unit 310 includes a motion detection unit 311 that detects the amount of motion of a video, and a scene change detection unit 312 that detects video switching.

  The frame synchronization unit 300 performs, for each input video signal stored in the frame memory 400, a process of repeatedly reading the frame (repeat process) and a process of skipping the video signal (skip process). The input video signal is read out. The timing for reading the input video signal is a part for synchronizing the video with the display synchronization signal, and is performed in a scene suitable for repeat processing and skip processing.

  The synchronization timing detection unit 310 detects a scene suitable for repeat processing and skip processing.

  The address control unit 320 controls an address for writing to and reading from the frame memory 400 based on the timing notified from the synchronization timing detection unit 310.

  Next, the operation of the above-described configuration will be described later with a specific example.

  Before that, the operation of the conventional frame sync will be described with reference to FIG. FIG. 3 is an explanatory diagram showing conventional control of write and read addresses to the frame memory.

  A conventional address control unit (not shown) receives V synchronization of an input video signal and a display synchronization signal for screen display. The input video signal is written to the frame memory according to the write address. At this time, the write address is counted up in synchronization with the input V synchronization, and the write address is reset to 0 when the number of frames that can be buffered is exceeded.

  On the other hand, the video signal to be displayed is read from the frame memory according to the read address. At this time, the read address is obtained as (write address at the timing of the display synchronization signal) − (predetermined phase difference). In the case of FIG. 3, the phase difference is set to 1.

  In this way, by controlling the write address and the read address, the input video signal is displayed in synchronization with the display synchronization signal for screen display.

  By performing the conventional address control, if the frequency of the input V synchronization and the display synchronization signal is the same, it is possible to output in synchronization, but there is a difference in the frequency between the input V synchronization and the display synchronization signal. If there is, there is a skip in which the input video signal is skipped, or a repeat in which the input video signal is repeatedly displayed.

  For example, FIG. 3A shows a case where the frequency of the display synchronization signal is slower than the input V synchronization. In FIG. 3A, the frame “1” is designated by the read address for the display synchronization signal generated during the writing of the write address “2”. Subsequently, a display synchronization signal is generated during writing at the write address “3” and further at the write address “4”. Therefore, the frame “3” in which the phase difference of the write address “4” is 1 is designated as the read address. Thus, a frame skip occurs in which the frame “2” of the input video signal is skipped and read out.

  FIG. 3B shows a case where the frequency of the display synchronization signal is faster than the input V synchronization. In FIG. 3B, the display synchronization signal is generated twice while the write address “3” is being written. For this reason, the frame “2” is designated as the read address corresponding to the two display synchronization signals. In this manner, frame repeat is generated in which the “2” frame of the input video signal is repeatedly read out.

  As described above, in the conventional address control, the same frame, called judder, is repeatedly generated or skipped by skipping a frame at regular intervals. For this reason, the user may feel uncomfortable depending on the displayed scene.

  Judder is not easily perceived by the user in a scene where the image is stationary, a scene where the motion is extremely intense, or a scene where blackout or whiteout occurs when the scene changes (scene change).

  Therefore, in this embodiment, paying attention to this, it is made difficult to perceive by the user by generating judder by repeat processing for repeatedly playing frames in these scenes or skip processing for skipping frames. It is characterized by that.

  The motion detection unit 311 and the scene change detection unit 312 detect a still scene in which a video is still, a scene with extremely intense motion, or a scene change.

  The distinction between a still scene and a scene with extremely intense movement is specified as follows. With respect to the temporally continuous frames of the input video, each frame is divided into several small areas, and the sum of luminance differences between the preceding and following frames of the corresponding divided small areas is obtained. It can be determined as a still scene as this sum is closer to 0, a scene with extremely intense movement as the sum is larger, or a scene change. Establishing a predetermined threshold for determining a still scene and a predetermined threshold for determining an extremely intense scene or scene change, and the total difference in luminance between frames and the respective thresholds are related in magnitude Thus, it is determined that the scene is a still scene, an extremely intense scene, or a scene change. In the detection of a scene change, a portion where the difference between the average luminance of the entire frame of the input video and the average luminance of several frames before the frame of the input video is large may be determined as a scene change.

  The synchronization timing detection unit 310 has an address control unit as a suitable timing for repeat processing and skip processing in a still scene, a scene with intense motion, and a scene in which a scene change occurs detected by the motion detection unit 311 and the scene change detection unit 312. 320 is notified.

  FIG. 4 is an explanatory diagram showing the writing to the frame memory 400 and the control of the reading address in the address control unit 320. Although the case of the skip process is illustrated in FIG. 4, the same process can be applied to the repeat process.

  In FIG. 4, the phase difference is set to 4. It is assumed that the size of the frame memory is 8 frames, that is, addresses “0” to “7” are prepared.

  The write address generated by the address control unit 320 is counted up by the input V synchronization.

  On the other hand, as shown in FIG. 4A, the read address is reset so as to have a predetermined phase difference from the write address at the start of display, and is counted up by display V synchronization. After writing with a write address of “4”, a frame of “0” having a phase difference of 4 is read by the display synchronization signal.

  While the display synchronization signal is delayed from the input V synchronization while proceeding from the state shown in FIG. 4A to the state shown in FIG. 4B, the delay is accumulated without adjusting the phase difference in the middle. It shows the state. In FIG. 4B, a display synchronization signal is generated when the video signal input at the write address “4” is being written. Up to this point, since the readout is performed without frame skipping, the phase difference is accumulated, and the phase difference is “6” instead of the phase difference “4”. Here, if the read address phase difference “6” remains, the frame “0” is read out. However, if it is notified from the sync timing detection unit 310 that the scene is suitable for frame skipping, frame skip processing is performed so as to eliminate the phase difference.

  Now, since the phase difference with the write address is “6”, which is larger than the predetermined phase difference “4”, it is determined that the frame skip is possible, and the frame skip is performed until the predetermined phase difference is caught up. In FIG. 4B, while the preferred scene notification is made, a process of reducing the phase difference by one is performed. That is, the address “0”, which is the phase difference “5” obtained by reducing the phase difference by one in accordance with the display synchronization signal generated while the video signal input at the write address “5” is being written, is read. Set as. Subsequently, according to the display synchronization signal generated in the period of the write address “6”, an address “2” that is a phase difference “4” obtained by further reducing the phase difference by one is set as a read address. As described above, since the phase difference is reduced, the designated phase difference becomes “4”. Therefore, the subsequent read address setting is read with the phase difference “4” without being made smaller than the phase difference “4”. Proceed with address setting. Since the display synchronization signal is later than the input V synchronization, the phase difference “4” is increased thereafter. Although FIG. 4B shows an example in which the phase difference is reduced by one, the phase difference may be reduced at a time. In other words, the phase difference is reduced from “6” to the phase difference “4”, and when writing is performed at the write address “5”, the read address “1” may be set. . Further, the size of contraction may be a constant value of 2 or more.

  As shown in FIG. 4C, when the phase difference from the write address is larger than a predetermined value (the frame memory is for 8 frames, the phase difference is “7”). Even if a suitable scene is not detected, frame skip is performed to prevent frame memory overflow (overtaking).

  FIG. 7 is a flowchart of frame synchronization processing in the first embodiment.

  The video signal processing method according to the first embodiment has the following processing flow.

  First, a plurality of video signals are input (S710).

  Subsequently, a display synchronization signal for simultaneously displaying a plurality of input images is generated. This selects any one of the V synchronizations of the plurality of video signals and sets it as a display synchronization signal (S720).

  Next, a period for eliminating the synchronization deviation is determined for a video signal that is out of synchronization with the display synchronization signal among the plurality of video signals. First, it is determined whether or not the video signal in which the synchronization shift occurs is a still scene or whether the motion amount of the frame of the video signal is a predetermined size or more. If it is a still scene or if the amount of motion is large (Yes in S730), the synchronization error is eliminated (S750).

  If it is not a still scene and the amount of motion is not large (No in S730), it is determined whether or not the video signal is a scene where the video scene changes with respect to the video signal in which synchronization loss occurs. If the video scene changes (Yes in S740), the synchronization error is eliminated (S750).

  If none of the above determinations in S730 and S740 is applicable (No), the synchronization error is not eliminated.

  To eliminate the synchronization error, when the display synchronization signal is delayed (the interval between the display synchronization signals is long) with respect to the V synchronization of the video signal causing the synchronization error, the frames at the same time are repeatedly displayed. When the display synchronization signal is advanced (when the interval of the display synchronization signal is short), the frame is thinned and displayed.

(Embodiment 2)
FIG. 5 is a configuration diagram of the frame synchronization unit 301 according to the second embodiment of the present invention.

  The frame synchronizer 301 includes an address controller 320 and an interpolation frame generator 360. The interpolation frame generation unit 360 includes a motion vector detection unit 361 and a motion compensated image generation unit 362.

  The interpolation frame generation unit 360 generates an intermediate phase interpolation frame from a plurality of temporally continuous frames. The motion vector detection unit 361 detects a motion vector from a plurality of temporally continuous frames. The motion compensated image generation unit 362 generates an interpolation image by motion compensation from the detected motion vector.

  Next, the operation of the above-described configuration will be described with a specific example. Here, the operation of the address control unit 320 is as described in the first embodiment.

  The second embodiment is characterized in that the frame before and after frame repeat or frame skip is replaced with an interpolated frame corresponding to a time such that the frame intervals are substantially equal in time. The interpolation frame generation unit 360 generates this interpolation frame.

  FIG. 6 is an explanatory diagram showing frame replacement in the interpolated frame generation unit 360. In FIG. 6, the case where the frame phase difference is 1 and the period of the display synchronization signal is slightly early is shown (the case of repeat is illustrated, but the same applies to skip).

  .., 7 are written as write addresses of the input video signal. The display synchronization signal is generated twice during the period in which the input video signal is written in the frame “3”. When the read address is set with the phase difference “1”, the read addresses are 0, 1, 2, 2, 3, 4,... And the frame “2” is read repeatedly. The interpolation frame generation unit 360 generates an interpolation frame so that the frames between 1, 2, 2, 3, and 4 are temporally equal. Five frames are generated from the first frame to the fourth frame. These five interpolated frames are generated as 1, 1.8, 2.5, 3.2, 4 and 4 frames, with 1 frame and 4 frames on both sides being left as they are, and the interval between them being almost equal. The decimal represents the temporal phase centroid. Indicates that an interpolation frame is generated. That is, if the frame is 1.8, the frame 1 and the frame 2 are linearly interpolated with a motion compensation ratio of 1: 4. If the frame is 2.5, the frame 2 and the frame 3 are linearly interpolated at 1: 1.

  In linear interpolation, a motion vector detection unit 361 detects a motion vector between two frames, and a motion compensation image generation unit 362 generates a motion compensated image obtained by interpolating the detected motion vector at the previous ratio.

  The motion vector detection unit 361 divides an input video frame to be detected into several frames, and each motion vector of the divided small area is a frame before and after the input video (in the past and the future in time). Is estimated by referring to. A portion corresponding to each of the divided small regions is searched from within a reference frame that is a frame before and after the input video. At this time, for example, there is a method for obtaining a portion where the sum of luminance differences is minimum.

  The motion compensated image generation unit 362 generates a frame corresponding to the middle (predetermined phase) from two consecutive frames of the input video. For example, each pixel of the intermediate frame is generated as an intermediate frame by mixing the pixels of two frames before and after the motion vector of the pixel at a ratio according to the phase.

  In this way, the frame specified by the read address is not output as an output video as it is, but the interpolated frame is generated by the interpolated frame generation unit 360, so that a repeated frame by frame repeat is displayed. However, since the temporal continuity of frames is improved, judder is reduced for the user.

  FIG. 8 is a flowchart showing the elimination of the synchronization error in the second embodiment.

  When it is determined that there is a possibility that the input video signal may be out of sync, determine the period to eliminate the out of sync and determine the frame equivalent to the interpolation time so that the time is equal during that period (S810).

  Subsequently, the video frame is interpolated into the input video signal corresponding to the time before and after the determined interpolation time to generate an interpolation frame (S820).

  In the second embodiment, the generation of the interpolated frame when the frame repeat occurs has been described. However, when the frame skip occurs, the interpolated frame is generated in the same manner, so that the time of the frame is increased. Continuity can be improved.

  As described above, according to the present invention, judder due to frame synchronization processing is reduced, and a smooth and high-quality video display can be achieved. Therefore, the present invention is useful for a video signal processing apparatus and method for displaying a plurality of videos on a multi-screen.

DESCRIPTION OF SYMBOLS 100 Video input part 200 Display synchronous production | generation part 300 Frame synchronization part 301 Frame synchronization part 310 Synchronization timing detection part 311 Motion detection part 312 Scene change detection part 320 Address control part 360 Interpolation frame generation part 361 Motion vector detection part 362 Motion compensation image generation Unit 400 frame memory 500 multi-screen composition unit 600 video display unit

Claims (7)

A video signal processing apparatus for generating a display screen for simultaneously displaying a plurality of videos on a screen,
A video input unit for inputting a plurality of video signals of the video;
Display synchronization generation for generating a display synchronization signal, which is a synchronization signal for displaying the display screen, based on a free-running vertical synchronization signal or a vertical synchronization signal in one of the plurality of video signals. And
A plurality of the video signals input from the video input unit, a frame synchronization unit that outputs in synchronization with the display synchronization signal;
A multi-screen synthesis unit that synthesizes a plurality of video signals output from the frame synchronization unit and generates the display screen;
The frame synchronization unit includes a synchronization timing detection unit that determines an appropriate period for eliminating the synchronization shift with respect to a video signal in which a synchronization shift occurs with the display synchronization signal among the plurality of video signals.
In the period determined by the synchro timing detection unit, the video signal that is out of synchronization with the display synchronization signal is output by repeating a frame at the same time or by thinning out and outputting the frame. A video signal processing apparatus characterized by eliminating the deviation. The synchronization timing detection unit
A motion detector that detects the amount of motion of the video included in the video signal;
A scene change detection unit for detecting a change of a scene of a video including the video signal;
Detecting a scene where it can be determined that there is no video motion amount, a scene where the video motion amount is greater than or equal to a predetermined amount, or a change in the video scene, and determining that it is an appropriate period to eliminate the synchronization gap The video signal processing apparatus according to claim 1. A video signal processing apparatus for generating a display screen for simultaneously displaying a plurality of videos on a screen,
A video input unit for inputting a plurality of video signals of the video;
Display synchronization generation for generating a display synchronization signal, which is a synchronization signal for displaying the display screen, based on a free-running vertical synchronization signal or a vertical synchronization signal in one of the plurality of video signals. And
A plurality of the video signals input from the video input unit, a frame synchronization unit that outputs in synchronization with the display synchronization signal;
A multi-screen synthesis unit that synthesizes a plurality of video signals output from the frame synchronization unit and generates the display screen;
The frame synchronization unit generates an interpolation frame of an intermediate phase from a plurality of temporally continuous frames for a video signal that is out of synchronization with the display synchronization signal among the plurality of video signals. A generator,
For a video signal in which a synchronization error occurs with respect to the display synchronization signal, the synchronization error is eliminated by replacing the video signal with an intermediate frame generated by the interpolation frame generation unit in a period for eliminating the synchronization error. A video signal processing apparatus. The interpolation frame generation unit
A motion vector detector that detects a motion vector from a plurality of temporally continuous frames;
A motion compensation image generation unit that generates an interpolation image by motion compensation from the motion vector detected by the motion vector detection unit;
4. The video signal processing apparatus according to claim 3, wherein the interpolated image is generated as an interpolated frame of the intermediate phase. A video signal processing method for generating a display screen for simultaneously displaying a plurality of videos on a screen,
A video input step of inputting a plurality of video signals of the video;
Display synchronization generation for generating a display synchronization signal, which is a synchronization signal for displaying the display screen, based on a free-running vertical synchronization signal or a vertical synchronization signal in one of the plurality of video signals. Steps,
A frame synchronization step for outputting the plurality of input video signals in synchronization with the display synchronization signal;
A multi-screen synthesis step of generating a plurality of video signals output by the frame synchronization step to generate the display screen,
The frame synchronization step includes a synchronization timing detection step of determining an appropriate period for eliminating the synchronization shift with respect to the video signal in which a synchronization shift occurs with the display synchronization signal among the plurality of video signals,
In the period determined in the sync timing detection step, for the video signal that is out of synchronization with the display synchronization signal, the video signal having the same time is repeatedly output or the frame is thinned and output. A video signal processing method characterized by eliminating the deviation. The synchronization timing detection step includes
A motion detection step of detecting a motion amount of a video included in the video signal;
A scene change detection step for detecting a change of a scene of a video including the video signal,
Detecting a scene where it can be determined that there is no video motion amount, a scene where the video motion amount is greater than or equal to a predetermined amount, or a change in the video scene, and determining that it is an appropriate period to eliminate the synchronization gap The video signal processing method according to claim 5. A video signal processing method for generating a display screen for simultaneously displaying a plurality of videos on a screen,
A video input step of inputting a plurality of video signals of the video;
Display synchronization generation for generating a display synchronization signal, which is a synchronization signal for displaying the display screen, based on a free-running vertical synchronization signal or a vertical synchronization signal in one of the plurality of video signals. Steps,
A frame synchronization step for outputting the plurality of input video signals in synchronization with the display synchronization signal;
A multi-screen synthesis step of generating a plurality of video signals output by the frame synchronization step to generate the display screen,
The frame synchronization step generates an interpolated frame of an intermediate phase from a plurality of temporally continuous frames for a video signal that is out of synchronization with the display synchronization signal among the plurality of video signals. With a generation step,
For a video signal in which a synchronization error occurs with respect to the display synchronization signal, the synchronization error is eliminated by replacing the video signal with an intermediate frame generated by the interpolation frame generation unit in a period for eliminating the synchronization error. And a video signal processing method.

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