KR20070047729A - Method for outputting deferred vertical synchronous signal and image signal processor performing the method - Google Patents

Abstract

A vertical synchronization signal delay output method and an image signal processor performing the method are disclosed. In the vertical synchronization signal delay output method according to an embodiment of the present invention, when a capture command is input and a vertical synchronization signal for a k-th frame is input from an encoder, a delay control command for a k + 1 th frame is sent to the image sensor. When the encoding process for the k-th frame is completed, the return control command is transmitted to the image sensor. By the present invention, a complete encoding process of image data can be performed.

Encoding, image, JPEG, image sensor

Description

Method for outputting deferred vertical synchronous signal and image signal processor performing the method}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified diagram of a configuration of a general imaging device.

2 is a diagram illustrating a general JPEG encoding process.

FIG. 3 is a diagram illustrating a signal form for outputting encoded data by a conventional image signal processor (ISP). FIG.

4 is a diagram schematically showing a configuration of an imaging device according to an embodiment of the present invention.

5 is a view briefly showing a configuration of a data output unit according to an exemplary embodiment of the present invention.

6 and 7 illustrate output signal waveforms of each component according to a preferred embodiment of the present invention.

The present invention relates to data encoding, and more particularly to the output of a vertical synchronization signal for the delivery of encoded data.

In recent years, small and thin image pickup devices have been mounted in small and thin portable terminals such as mobile phones and PDAs (Personal Digital Assistants), whereby the portable terminals can function as image pickup devices, thereby enabling not only audio information but also images to be remotely located. Information can also be transmitted. The imaging device is provided not only in a mobile phone or a PDA but also in a portable terminal such as an MP3 player so as to hold external images as electronic data in various devices.

Generally, solid-state imaging devices, such as a charge coupled device (CCD) type image sensor and a complementary metal-0xide semiconductor (CMOS) type image sensor, are used for such an imaging device.

FIG. 1 is a diagram schematically illustrating a configuration of a general image capturing apparatus, FIG. 2 is a diagram illustrating a general JPEG encoding process, and FIG. 3 is a conventional image signal processor (ISP) for outputting encoded data. It is a figure which shows the signal form.

As illustrated in FIG. 1, an image pickup device that converts an external image into electrical data and displays the same on the display unit 150 includes an image sensor 110, an image signal processor 120 (ISP), and a backend chip ( 130, a back-end chip, a baseband chip 140, and a display unit 150. In addition, the imaging apparatus may further include a memory for storing the converted electrical data, an AD converter for converting an analog signal into a digital signal, and the like.

The image sensor 110 is a sensor having a Bayer pattern, and outputs an electric signal corresponding to the amount of light input through the lens for each unit pixel.

The image signal processor 120 converts an electrical signal (raw data) input from the image sensor 110 into a YUV value, and inputs the converted YUV value to the back end chip 130. The YUV method focuses on the fact that the human eye is more sensitive to brightness than color, and the color is divided into Y component, which is luminance, and U and V, which are chroma. Since the Y component is sensitive to error, we code more bits than the color components U and V. A typical Y: U: V ratio is 4: 2: 2.

The image signal processor 120 sequentially stores the converted YUV values in the FIFO so that the back end chip 130 may receive the corresponding information.

The back end chip 130 converts the input YUV value into JPEG or BMP by using a predetermined encoding method and stores the same in the memory or decodes the displayed YUV value on the display unit 150. The back end chip 130 may also perform functions such as enlargement, reduction, and rotation of an image. Of course, as shown in FIG. 1, the baseband chip 140 may receive decoded data from the backend chip 130 and display the decoded data on the display unit 150.

The baseband chip 140 performs a function of controlling the overall operation of the imaging device. For example, when an imaging command is input from a user through a key input unit (not shown), the baseband chip 140 transmits an image generation command to the backend chip 130 to the external image to which the backend chip 130 is input. It is also possible to generate corresponding encoded data.

The display unit 150 displays decoded data provided by the control of the back end chip 130 or the baseband chip 140.

2 illustrates a general JPEG encoding process performed by the back end chip 130. Since the JPEG encoding process 200 is obvious to those skilled in the art, it will be briefly described.

As shown in FIG. 2, the input YUV values are divided into blocks of 8 × 8 pixel size, and a DCT (Discrete Cosine Transform) is performed on each block (210). The pixel value of each pixel input in the form of an 8-bit integer between -128 and 127 is converted into a value between -1024 and 1023 by the DCT.

Subsequently, the quantizer quantizes the DCT coefficient of each block with weights according to the effect on time (220). This table of weights is called a quantization table. The quantization table values take small values near DC, and large values at high frequencies, resulting in small loss of data near DC with a large amount of information, and high compression at high frequencies.

The final compressed data is then generated 230 by an entropy encoder, which is a lossless coder.

The data encoded through the above-described process is loaded into the memory. The back end chip 130 decodes the data loaded in the memory and displays the same on the display unit 150.

A signal waveform of a process of sequentially inputting data loaded in a memory for processing such as decoding is shown in FIG. 3. In general, the back end chip 130 is implemented to receive data in YUV / BAYER format, and uses the P_CLK, V_sync, H_REF, and DATA signals as an interface for receiving such data.

As shown in FIG. 3, the conventional back-end chip 130 is configured to receive a vertical sync signal V_sync2 and / or image data for a subsequent frame while performing an encoding process for one frame. There was a lot of problems that can occur when encoding data.

That is, in this case, the back end chip 130 may perform not only the encoding process for the frame currently being processed but also the encoding process for the next frame, thereby preventing accurate data encoding from being completed.

In addition, when the encoding unit of the back end chip 130 transmits the encoded data to the decoding unit or stores the encoded data in the memory, after receiving the new vertical sync signal V_sync2, the encoded data for the current frame may not be input normally. .

Accordingly, an object of the present invention is to provide a vertical synchronization signal delay output method capable of improving processing efficiency of a backend chip and an image signal processor performing the method.

Another object of the present invention is to transmit data encoded by an encoder to a receiving end (e.g., back-end chip, baseband chip, etc.) to output a vertical synchronization signal at an optimal time point (i.e., recognize input of a new frame). To provide a vertical synchronization signal delay output method and an image signal processor performing the method.

It is still another object of the present invention to provide a vertical synchronization signal delay output method in which an input of processed data for a current frame is not interrupted by an input of a vertical synchronization signal representing an input of a new frame when receiving encoded data at a receiving end, and It is to provide an image signal processor that performs the method.

It is still another object of the present invention to provide a vertical synchronization signal delay output method having an advantageous effect in terms of hardware design and control by using a general interface structure when an image signal processor provides encoded data to a backend chip, and an image for performing the method. It provides a signal processor.

It is still another object of the present invention to provide a vertical synchronization signal delay output method and an image signal processor performing the method, by which an image signal processor can determine whether to encode an input frame according to an encoding speed and thus perform a smooth encoding operation. .

Other objects of the present invention will become more apparent through the preferred embodiments described below.

According to an aspect of the present invention to achieve the above object, there is provided an image signal processor and / or an imaging device including the image signal processor.

According to a preferred embodiment of the present invention, an imaging device comprising: an image sensor for outputting an electrical signal corresponding to an external image; A sub-ISP (Image Signal Processor) for performing preprocessing corresponding to at least one of filtering and interpolation of the electrical signal; An encoding unit encoding the preprocessed electrical signal to generate encoded image data; And a data output unit configured to output the encoded image data to a receiver, wherein the receiver is a backend chip or a baseband chip, wherein the sub-ISP is followed by a k (natural number) frame to be processed immediately after the input of the capture command. output a delay control command for extending the output period of the vertical synchronization signal corresponding to the k + 1th frame to the image sensor, and the image sensor outputs the output period of the vertical synchronization signal in response to the delay control command An imaging device is provided.

An end point of the output period of the vertical synchronization signal output from the image sensor is output the same as or subsequent to the time point when the encoding of the k-th frame is completed by the encoding unit, and the end point is a falling edge or a rising edge. It is characterized in that (rising edge).

When the data output unit detects that the encoding process of the k-th frame is completed and notifies the sub-ISP, the sub-ISP outputs a return control command to the image sensor, and the return control command corresponds to the k + 2th frame. The length of the output section of the vertical synchronization signal is reset to a default value, and the gain value is adjusted to the default value.

The encoded image data output for the k-th frame is characterized by being from 'START MARKER' to 'STOP MARKER'.

The data output unit may include a register for delaying and outputting the encoded image data input from the encoding unit by a predetermined clock.

The data output unit may include an H_sync generator configured to generate and output the valid data enable signal in a high or low state according to a valid data enable control command; A transmission delay unit for outputting valid data input from the encoding unit and invalid data or pre-generated dummy data according to a data output control command; And a transmission controller configured to generate and output the valid data enable control command and the data output control command.

The valid data enable signal may be interpreted as a write enable signal at the receiving end.

According to another aspect of the present invention for achieving the above object, there is provided a vertical synchronization signal delay output method performed in an image signal processor and / or a recording medium on which a program for performing the method is recorded.

According to one preferred embodiment of the present invention, a vertical synchronization signal delay output method performed in an image signal processor of an image pickup device having an image sensor, the method comprising: receiving a capture command; Receiving a vertical synchronization signal for a k (natural number) -th frame from the encoding unit; transmitting a delay control command for a k + 1th frame to the image sensor; And when the encoding process for the k-th frame is completed, transmitting a return control command to the image sensor, wherein the delay control command causes the image sensor to output a vertical sync signal corresponding to the k + 1 th frame. The output period may be extended and output, and the image sensor may adjust the length of the output period of the vertical synchronization signal for the k + 2th frame and the gain value by the return control command.

An end point of the output period of the vertical synchronization signal output from the image sensor is output the same as or after the completion of the encoding of the k-th frame, and the end point is a falling edge or a rising edge. Can be.

Whether encoding of the k-th frame is completed may be determined using header information and tail information of the encoded data.

Hereinafter, a vertical synchronization signal delay output method and an image signal processor performing the method will be described in detail with reference to the accompanying drawings. In the following description of the present invention with reference to the accompanying drawings, the same or corresponding components will be given the same reference numerals and redundant description thereof will be omitted.

4 is a view schematically showing a configuration of an imaging device according to an exemplary embodiment of the present invention, FIG. 5 is a view schematically showing a configuration of a data output unit according to an embodiment of the present invention, and FIGS. 6 and 7 A diagram illustrating an output signal waveform of each component according to a preferred embodiment of the present invention.

As shown in FIG. 4, the imaging apparatus according to the present invention includes an image sensor 110, an image signal processor 400, and a back end chip 405. In addition, it will be apparent that the imaging apparatus may further include a display unit 150, a memory, a baseband chip 140, a key input unit, and the like, and thus description thereof will be omitted.

The image sensor 110 includes a V_sync controller 440. The V_sync controller 440 controls the length of the vertical sync signal (V_sync) section of the frame correspondingly when a sensor control command is input from the sub image signal processor (ISP) 410.

For example, as shown in FIG. 6, if a delay control command is input from the sub-ISP 410 while outputting raw data for the k (natural number) frame, the k + 1 th frame is input immediately after. Controls the delay output of the V_sync signal. That is, when the sub ISP 410 or the like according to the present invention detects a rising edge of the V_sync signal and detects whether an electrical signal for a new frame is input, it delays the time when the rising edge is generated. The delay time of the rising edge may be predetermined, and may be, for example, any time of processing data of 8 to 24 line size.

Subsequently, when the return control command is input from the sub-ISP 410, the interval of the V_sync signal output thereafter is reduced to the default length, and the gain value is readjusted to a predetermined value. The return control command may be input from the sub ISP 410 when the processing of the frame corresponding to the input capture command (eg, the picture taking command) is completed. The reason for adjusting the gain value to a predetermined value is as follows. Increasing the output interval of the V_sync signal increases the exposure time, which is the sensor integration time, so that the brightness becomes brighter so that the gain can be adjusted to maintain a relatively low brightness. will be. This is because an abnormal increase in the gain value may adversely affect a subsequent input image.

The image signal processor 400 includes a sub ISP 410, a JPEG encoder 420, and a data output unit 430. Of course, the image signal processor 400 may further include a clock generator for internal operation.

The sub ISP 410 not only functions as an image signal processor according to the related art, but also additional functions (for example, sensor control command output, capture command output, capture completion information input, etc.) described herein. Do more.

In detail, the sub ISP 410 may perform a preprocessing process for processing the JPEG encoder 420. The sub-ISP 410 may receive raw data in the form of an electric signal from each image sensor 110 for each frame, process the raw data, and transmit the raw data to the JPEG encoder 420.

The preprocessing may include color space transformation, filtering, downsampling, and the like.

Color Space Transformation converts the RGB color model to a YUV (or YIQ) color model because it can reduce the amount of information without being aware of the difference in picture quality. .

Filtering is a process of smoothing an image with a low pass filter to increase the compression ratio.

Color subsampling is the process of downsampling the chrominance signal components by using all the Y values and using only some of the other values.

In addition, the sub-ISP 410 is a vertical output from the image sensor 110 for a frame immediately after the capture command (for example, a photographing command) is input from the back end chip 405 or the baseband chip 140. In order to extend the output section length of the synchronization signal (V_sync signal), a sensor control command (ie, a delay control command) is output to the V_sync controller 440 of the image sensor 110, and a capture command is sent to the JPEG encoder 420. Output It will be apparent to those skilled in the art that the vertical sync signal means that the input of each frame will be initiated.

By the delay control command, the V_sync controller 440 extends and outputs the length of the output section of the V_sync signal to be immediately output. In addition, by the capture command, the JPEG encoder 420 processes image data of a corresponding frame. The processing of the JPEG encoder 420 by the capture command is the same as the processing operation by the conventional photography command. Therefore, the process of outputting the capture command to the JPEG encoder 420 may be omitted.

Subsequently, when the data output unit 430 recognizes that the JPEG encoded data including 'STOP MARKER' is input from the JPEG encoder 420 and the encoding processing for the corresponding frame is completed, the data output unit 430 captures the capture completion information to the sub ISP 410. Outputs

Subsequently, the sub-ISP 410 outputs a return control command to the V_sync controller 440 to perform output section length control and gain value adjustment of the V_sync signal.

The JPEG encoder 420 compresses raw data preprocessed by the sub ISP 410 in the same manner as described above to generate JPEG encoded data.

The JPEG encoder 420 is an input memory for temporarily storing the processed raw data input from the sub-ISP 410 in order to be divided into predetermined block units (for example, 8 x 8) for encoding processing. It may include. In addition, the JPEG encoder 420 may further include an output memory for temporarily storing the JPEG encoded data before outputting the encoded data to the data output unit 430. The output memory can be, for example, a FIFO. That is, the image signal processor 400 according to the present invention may further perform encoding of image data, unlike the conventional image signal processor 120.

The data output unit 430 receives the JPEG encoded data generated by the JPEG encoder 420 (for example, the back end chip 405, the baseband chip 140, the camera control processor (CCP), etc.). Collectively referred to as back-end chip 405). The data output unit 430 may include a register for delaying and outputting data input from the JPEG encoder 420 for a predetermined time (for example, 2 to 3 clocks).

The data output unit 430 monitors whether the encoded data input from the JPEG encoder 420 includes 'STOP MARKER' and transmits the capture completion information to the sub ISP 410 when the data output unit 430 includes the 'STOP MARKER'. .

When the backend chip 405 receives, for example, a command for capturing a picture from the baseband chip 140 that performs overall operation control of the portable terminal, the backend chip 405 transmits a capture command to the sub ISP 410 and transmits an image signal. The JPEG encoded data received from the processor 400 is received and stored in a memory, decoded, displayed on the display unit 150, or the baseband chip 140 may be read and processed. An I2C bus may be used to deliver capture commands to sub ISP 410.

5 illustrates a detailed configuration of the data output unit 430.

Referring to FIG. 5, the data output unit 430 includes an AND gate 510, an H_sync generator 530, a transmission delay unit 540, and a transmission control unit 550. The data output unit 430 according to the present invention does not have a separate V_sync generator, which is sufficient to output the V_sync input from the preceding component (for example, the JPEG encoder 420) as it is. Because.

 The AND gate 510 outputs the clock signal P_CLK to the back end chip 405 only when signals are input to all inputs. In other words, the clock signal is input from a clock generator (not shown) included in the image signal processor 400, the clock control signal is input from the transmission control unit 550, and the clock control signal indicates the clock signal output. The signal is output to the back end chip 405. The clock control signal may be in the form of a high signal or a low signal, and may be recognized as a P_CLK enable or P_CLK disable signal, respectively. Of course, the reverse is also possible. In this case, a section in which the clock signal P_CLK is output to the backend chip 405 may be matched with a section in which the transmission delay unit 540 outputs valid data among JPEG encoded data. It will be apparent to those skilled in the art that the transmission control unit 550 may control the output signal of the AND gate 510 because the transmission controller 550 may identify whether the encoded data to be currently output is valid data or invalid data. If the clock signal is set to be always output to the backend chip 405, the AND gate 510 shown may be omitted.

The H_sync generator 530 is in a high state under the control of the transmission control unit 550 (that is, until the valid data enable signal H_REF output command is input and the output termination command of the H_REF signal is input). A valid data enable signal H_REF is generated and output. The high period of the valid data enable signal (which may be a low period according to a design method) coincides with a period in which the valid data is output among the JPEG encoded data for one frame in the transmission delay unit 540. It will be apparent to those skilled in the art that the transmission controller 550 may control the output signal of the H_sync generator 530 because the transmission controller 550 may identify whether the encoded data to be currently output is valid data or invalid data.

The transmission delay unit 540 sequentially outputs data input from the JPEG encoder 420 to the back end chip 405. The transmission delay unit 540 may include, for example, a register for delaying and outputting data input from the JPEG encoder 420 at a predetermined time (for example, 2 to 3 clocks). The section in which the transmission delay unit 540 outputs valid data may coincide with the section in which the H_REF signal is output in a high state.

Whether the JPEG encoded data temporarily stored in the transmission delay unit 540 is valid data may be determined by the transmission control unit 550, and the data to be currently output is not valid data (for example, ff, 0x00). Including data), the transmission controller 550 may control the AND gate 510 such that the clock signal is not output to the back end chip 405, and control the H_sync generator 530 to output the H_REF signal in a low state. Can be.

The invalid data (ie, invalid data) in the present specification means invalid data (ie, data that does not actually constitute an image) mentioned in the JPEG standard or the like, and may be represented as ff as an example. . However, it is apparent to those skilled in the art that 'ffd8' in FIG. 7 will be recognized as 'SOI' as 'START MARKER' and 'ffd9' will be recognized as 'EOI' as 'STOP MARKER'.

In the section in which the invalid data is output, the prestored dummy data (that is, data only for the purpose of matching the format) may be output. A multiplexer (MUX) may be provided in front of the transmission delay unit 540 to output dummy data. JPEG encoded data and dummy data are output through the multiplexer, and the transmission delay unit 540 may receive and output the received data. In this case, when the transmission controller 550 determines that the input JPEG encoded data is invalid data, the transmission controller 550 may input a dummy data output command to the multiplexer. The multiplexer may allow dummy data set in advance to be registered to the transmission delay unit 540 to be output to the back end chip 405.

The transmission control unit 550 receives a 'sequence from the header and the tail of the JPEG encoded data which the transmission delay unit 540 sequentially receives from the JPEG encoder 530 for valid data output and stores the data before the output. You can capture START MARKER 'and' STOP MARKER 'to recognize information about the beginning and end of JPEG encoding. That is, through this, the JPEG encoder 420 may recognize whether all one frame is encoded and / or output.

6 and 7 illustrate waveforms of signals output by each component. 6 illustrates a signal waveform when the image sensor 110 extends the length of the output section of the V_sync signal by a delay control command, and FIG. 7 illustrates a signal waveform output from the data output unit 430. .

As shown in FIG. 6, the image sensor 110 outputs a V_sync signal according to a preset period, and also outputs a corresponding electrical signal (raw data). That is, in a normal preview state (that is, a state in which an electrical signal input from the image sensor 110 is encoded and decoded and displayed on the display unit 150 regardless of the photographing state) before the photographing, an output such as 610 is obtained. The state will be maintained. However, if a capture command is input by the user while the k-th frame is being processed, a sensor control command (i.e., a delay control command) is input from the sub ISP 410 while the k-th frame is processed and immediately output. The length of the output section of the V_sync signal is extended. In the present specification, it is assumed that a new edge is input by a rising edge by the V_sync signal. Therefore, when the 610 and 620 are compared, it can be seen that the rising edge detection time is extended compared to the prior art. When shooting of the k-th frame is completed, the preview state resumes from the k + 1 th frame.

As the length of the output section of the V_sync signal is extended by the above-described process, as shown in FIG. 7, it may be at or after the processing of the frame is completed at the time when the rising edge of the V_sync signal is detected.

The data output unit 430 according to the present invention may solve the problem that normal data transmission and reception are interrupted by the V_sync signal for the k + 1th frame while processing the kth frame through the above-described process.

In this case, the data output unit 430 may maintain the H_REF signal high only when the encoded data to be output is valid data, and may also output the clock signal to the back end chip 405 only in a corresponding section. In this manner, unnecessary operation of the back end chip 405 may be minimized by turning off the clock signal P_CLK to be output to the back end chip 405 while invalid encoding data or dummy data is output. As a result, power consumption of the back end chip 405 may be minimized.

The conventional back end chip 405 is implemented to receive data in YUV / BAYER format, and has used P_CLK, V_sync, H_REF, and DATA signals as interfaces for receiving such data.

In consideration of this, the image signal processor 400 of the present invention is implemented to use the same interface as in the prior art.

Thus, it is apparent that the present invention can be port matched even when the back end chip 405 is implemented by a conventional back end chip design method.

For example, if the operation of the general back-end chip 405 is initialized from the interrupt of the rising edge of the V_sync signal, the present invention also applies the conventional interface structure in the same way, so that the existing V_sync signal is outputted. Likewise, by inputting the corresponding signal to the back end chip 405, interfacing between the chips is possible.

Similarly, a typical backend chip 405 should generate a V_sync rising interrupt, and also enable write enable of the valid data enable signal H_REF in memory when receiving data from the image signal processor 400. Considering the use as a signal, the power consumption of the back end chip 405 can be reduced by using the signal output method according to the present invention.

Until now, the image signal processor 400 has been described based only on the case of using the JPEG encoding scheme, but other encoding schemes such as BMP encoding scheme, MPEG (MPEG 1/2/4, MPEG-4 AVC) encoding scheme, TV out scheme, etc. Obviously, the same data transmission scheme can be used even if it supports it.

As described above, the vertical synchronization signal delay output method and the image signal processor implementing the method have an effect of improving processing efficiency of the backend chip.

In addition, the present invention transmits the data encoded by the encoder to the receiving end (e.g., back-end chip, baseband chip, etc.), outputting a vertical synchronization signal at the optimum time (i.e., recognize the input of a new frame) It also has the effect of making it possible.

In addition, the present invention has the effect that the input of the processed data for the current frame is not interrupted by the input of the vertical synchronization signal indicating the input of a new frame when receiving the encoded data at the receiving end.

In addition, the present invention may have an advantageous effect in terms of hardware design and control by using a general interface structure in providing the encoded data to the back-end chip to the image signal processor.

In addition, the present invention has the effect that the image signal processor can determine whether to encode the input frame according to the encoding speed can perform a smooth encoding operation.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (10)

In the imaging device, An image sensor for outputting an electrical signal corresponding to an external image; A sub-ISP (Image Signal Processor) for performing preprocessing corresponding to at least one of filtering and interpolation of the electrical signal; An encoding unit encoding the preprocessed electrical signal to generate encoded image data; And A data output unit configured to output the encoded image data to a receiver, wherein the receiver is a backend chip or a baseband chip, The sub-ISP outputs a delay control command to the image sensor to extend an output period of a vertical sync signal corresponding to a k + 1th frame following a k (natural number) th frame to be processed immediately after the capture command. And the image sensor extends and outputs the output section of the vertical synchronization signal in response to a delay control command. The method of claim 1, An end point of the output period of the vertical synchronization signal output from the image sensor is output the same as or subsequent to the time point when the encoding of the k-th frame is completed by the encoding unit, And the endpoint is a falling edge or a rising edge. The method of claim 1, If the data output unit detects that the encoding process of the k-th frame is completed and notifies the sub ISP, the sub ISP outputs a return control command to the image sensor. And the return control command resets the length of the output section of the vertical synchronization signal corresponding to the k + 2th frame to the default value and readjusts the gain value to the default value. The method of claim 1, The encoded image data output for the k-th frame is from 'START MARKER' to 'STOP MARKER'. The method of claim 1, And the data output unit comprises a register for delaying and outputting the encoded image data input from the encoding unit by a predetermined clock. The method of claim 1, The data output unit, An H_sync generator for generating and outputting the valid data enable signal in a high or low state according to a valid data enable control command; A transmission delay unit for outputting valid data input from the encoding unit and invalid data or pre-generated dummy data according to a data output control command; And And a transmission controller configured to generate and output the valid data enable control command and the data output control command. The method of claim 6, And the valid data enable signal is interpreted as a write enable signal at the receiving end. In the vertical synchronization signal delay output method performed in the image signal processor of the image pickup device having an image sensor, Receiving a capture command; Receiving a vertical synchronization signal for a k (natural number) th frame from the encoder; transmitting a delay control command for a k + 1th frame to the image sensor; And When the encoding process for the k-th frame is completed, transmitting a return control command to the image sensor, The image sensor extends the output period of the vertical synchronization signal corresponding to the k + 1th frame by the delay control command and outputs the vertical synchronization signal for the k + 2th frame by the return control command. And adjusting the length of the output section of the output section and the gain value. The method of claim 8, The end point of the output period of the vertical synchronization signal output from the image sensor is output the same as or after the completion of the encoding of the k-th frame, And the endpoint is a falling edge or a rising edge. The method of claim 8 The encoding of the k-th frame is completed or not is determined using the header (Header) information and the tail (Tail) information of the encoded data, characterized in that the vertical synchronization signal delay output method.

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