KR100685300B1 - Method for transferring encoded data and image pickup device performing the method - Google Patents

Abstract

A method for transmitting encoded data and an image pickup device for performing the method are provided to have profitable effect in a hardware design and control aspect by using a general interface structure when an image signal processor provides the encoded data to a back-end chip. A JPEG(Joint Photographic Experts Group) encoder(420) encodes image data corresponding to an electric signal inputted from an image sensor(110), and generates the encoded image data. A data output unit(430) temporarily stores the image data encoded by the JPEG encoder(420), and transmits the encoded data to a receiving terminal. If a following frame input notification signal notifying the input start of an electric signal for the n+1th frame is received from the image sensor(110) or the JPEG encoder(420) while encoded image data of the nth frame processed by the JPEG encoder(420) are transmitted, the data output unit(430) provides a skip command for skipping the process of the n+1th frame to the JPEG encoder(420). The JPEG encoder(420) skips the encoding of the image data for the n+1th frame inputted from the image sensor(110) by the skip command.

Description

Method for transferring encoded data and image pickup device performing the method

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified diagram of a configuration of a general imaging device.

2 is a diagram illustrating a general JPEG encoding process.

FIG. 3 is a diagram illustrating a signal form for outputting encoded data by a conventional image signal processor (ISP). FIG.

4 is a diagram schematically showing a configuration of an imaging device according to an embodiment of the present invention.

5 is a view briefly showing a configuration of a data output unit according to an exemplary embodiment of the present invention.

FIG. 6 illustrates signal waveform shapes for encoded data output of an image signal processor in accordance with one preferred embodiment of the present invention. FIG.

TECHNICAL FIELD The present invention relates to data encoding, and more particularly, to data encoding performed in an imaging device.

In recent years, small and thin image pickup devices have been mounted in small and thin portable terminals such as mobile phones and PDAs (Personal Digital Assistants), whereby the portable terminals can function as image pickup devices, thereby enabling not only audio information but also images to be remotely located. Information can also be transmitted. The imaging device is provided not only in a mobile phone or a PDA but also in a portable terminal such as an MP3 player so as to hold external images as electronic data in various devices.

Generally, solid-state imaging devices, such as a charge coupled device (CCD) type image sensor and a complementary metal-0xide semiconductor (CMOS) type image sensor, are used for such an imaging device.

FIG. 1 is a diagram schematically illustrating a configuration of a general image capturing apparatus, FIG. 2 is a diagram illustrating a general JPEG encoding process, and FIG. 3 is a conventional image signal processor (ISP) for outputting encoded data. It is a figure which shows the signal form.

As illustrated in FIG. 1, an image pickup device that converts an external image into electrical data and displays the same on the display unit 150 includes an image sensor 110, an image signal processor 120 (ISP), and a backend chip ( 130, a back-end chip, a baseband chip 140, and a display unit 150. In addition, the imaging apparatus may further include a memory for storing the converted electrical data, an AD converter for converting an analog signal into a digital signal, and the like.

The image sensor 110 is a sensor having a Bayer pattern, and outputs an electric signal corresponding to the amount of light input through the lens for each unit pixel.

The image signal processor 120 converts the electrical signal input from the image sensor 110 into a YUV value, and inputs the converted YUV value to the back end chip 130. The YUV method focuses on the fact that the human eye is more sensitive to brightness than color, and the color is divided into Y component, which is luminance, and U and V, which are chroma. Since the Y component is sensitive to error, we code more bits than the color components U and V. A typical Y: U: V ratio is 4: 2: 2.

The image signal processor 120 sequentially stores the converted YUV values in the FIFO so that the back end chip 130 may receive the corresponding information.

The back end chip 130 converts the input YUV value into JPEG or BMP by using a predetermined encoding method and stores the same in the memory or decodes the displayed YUV value on the display unit 150. The back end chip 130 may also perform functions such as enlargement, reduction, and rotation of an image. Of course, as shown in FIG. 1, the baseband chip 140 may receive decoded data from the backend chip 130 and display the decoded data on the display unit 150.

The baseband chip 140 performs a function of controlling the overall operation of the imaging device. For example, when an imaging command is input from a user through a key input unit (not shown), the baseband chip 140 transmits an image generation command to the backend chip 130 to the external image to which the backend chip 130 is input. It is also possible to generate corresponding encoded data.

The display unit 150 displays decoded data provided by the control of the back end chip 130 or the baseband chip 140.

2 illustrates a general JPEG encoding process performed by the back end chip 130. Since the JPEG encoding process 200 is obvious to those skilled in the art, it will be briefly described.

As shown in FIG. 2, the input YUV values are divided into blocks of 8 × 8 pixel size, and a DCT (Discrete Cosine Transform) is performed on each block (210). The pixel value of each pixel input in the form of an 8-bit integer between -128 and 127 is converted into a value between -1024 and 1023 by the DCT.

Subsequently, the quantizer quantizes the DCT coefficient of each block with weights according to the effect on time (220). This table of weights is called a quantization table. The quantization table values take small values near DC, and large values at high frequencies, resulting in small loss of data near DC with a large amount of information, and high compression at high frequencies.

The final compressed data is then generated 230 by an entropy encoder, which is a lossless coder.

The data encoded through the above-described process is loaded into the memory. The back end chip 130 decodes the data loaded in the memory and displays the same on the display unit 150.

A signal waveform of a process of sequentially inputting data loaded in a memory for processing such as decoding is shown in FIG. 3. In general, the back end chip 130 is implemented to receive data in YUV / BAYER format, and uses the P_CLK, V_sync, H_REF, and DATA signals as an interface for receiving such data.

As shown in FIG. 3, the conventional backend chip 130 outputs the clock signal P_CLK in the entire process in transferring the encoded data to a subsequent component (eg, a decoding unit). Since ON is maintained in the ON state, the backend chip 130 must perform an operation for interfacing with each other even while invalid data (0x00) is input.

Therefore, the conventional imaging device has a problem that unnecessary power consumption is caused by the unnecessary operation of the back end chip 130.

In addition, as shown in FIG. 3, the conventional image signal processor 120 backends a new vertical sync signal V_sync2 indicating the input of data for the next frame even though the encoding process for the frame currently being processed is not completed. The chip 130 may be output.

In this case, the back-end chip 130 may not only process the frame currently being processed but also process the next frame, thereby preventing accurate data input and / or processing from being completed.

Accordingly, an object of the present invention is to provide an encoded data transfer method capable of improving processing efficiency and preventing power consumption of a backend chip and an imaging apparatus that performs the method.

Another object of the present invention is to provide an encoded data transfer method having an advantageous effect in terms of hardware design and control by using a general interface structure in providing an image data processor to a back-end chip, and an imaging apparatus for performing the method. To provide.

It is still another object of the present invention to provide an encoded data transfer method and an imaging apparatus that perform the method, by which an image signal processor can determine whether to encode an input frame according to an encoding speed, thereby performing a smooth encoding operation.

Other objects of the present invention will become more apparent through the preferred embodiments described below.

According to an aspect of the present invention to achieve the above object, there is provided an image signal processor and / or an imaging device including the image signal processor.

According to a preferred embodiment of the present invention, an image signal processor of an imaging device, comprising: an encoding unit for generating encoded image data by encoding image data corresponding to an electrical signal input from an image sensor by a predetermined encoding method; And a data output unit configured to temporarily store image data encoded by the encoding unit, and transmit the stored encoded image data to a receiving end, wherein the receiving end is a backend chip or a baseband chip. When the input start information of a subsequent frame is received from the image sensor or the encoding unit during the processing of the preceding frame by the encoding unit, a skip command for skipping the processing of the subsequent frame is performed by the image sensor or the encoding. There is provided an image signal processor characterized by negative input.

The predetermined encoding scheme may be at least one of a JPEG encoding scheme, a BMP encoding scheme, an MPEG encoding scheme, and a TV out scheme.

The image signal processor may further include a clock generator.

The data output unit may output a clock signal to the receiving end only in a section in which valid data is transmitted. Invalid data may be data including 0x00.

The data output unit may further output a V_sync signal and a valid data enable signal to the receiver.

The data output unit may include: an AND gate for stopping output of the clock signal input from a clock generator when a clock disable signal is input; A V_sync generator for generating and outputting the vertical sync signal in a high or low state according to a vertical sync signal control command; An H_sync generator for generating and outputting the valid data enable signal in a high or low state according to a valid data enable control command; A transmission delay unit which temporarily stores the encoded data and outputs the stored encoded data according to a data output control command; And a transmission controller configured to generate and output the clock disable signal, the vertical synchronization signal control command, the valid data enable control command, and the data output control command. Here, when the encoded data is stored in the transmission delay unit, the transmission controller may control the clock signal and the valid data enable signal to be output only in an output section of valid data among the encoded data.

The valid data enable signal may be interpreted as a write enable signal at the receiving end.

The transmission control unit may determine whether encoding of the preceding frame is completed by using header information and tail information of the encoded image data stored in the transmission delay unit.

When the input start information of the subsequent frame is received during the processing of the preceding frame, the transmission control unit may control to maintain the current state when the vertical synchronization signal output by the V_sync generator is low.

In another preferred embodiment of the present invention, there is provided an image signal processor of an imaging device, comprising: a clock generator; An encoding unit for encoding the image data corresponding to the electrical signal input from the image sensor by using a predetermined encoding method to generate encoded image data; An AND gate for stopping output of the clock signal input from a clock generator when a clock disable signal is input; A V_sync generator for generating and outputting the vertical sync signal in a high or low state according to a vertical sync signal control command; An H_sync generator for generating and outputting the valid data enable signal in a high or low state according to a valid data enable control command; A transmission delay unit which temporarily stores the encoded data and outputs the stored encoded data according to a data output control command; And a transmission controller configured to generate and output the clock disable signal, the vertical synchronization signal control command, the valid data enable control command, and the data output control command. The clock signal, the vertical synchronizing signal, the valid data enable signal, and the encoded data may be output to a receiving end, wherein the receiving end is a backend chip or a baseband chip according to a predetermined condition. When the input start information of a subsequent frame is received from the image sensor or the encoding unit during the processing of the preceding frame by the encoding unit, a skip command for skipping the processing of the subsequent frame is performed by the image sensor or the encoding. Characterized in that the input.

According to still another preferred embodiment of the present invention, in an imaging device including an image sensor, an image signal processor, a back end chip, and a baseband chip, the image signal processor may include image data corresponding to an electrical signal input from an image sensor. An encoding unit for encoding the data by using a predetermined encoding method to generate encoded image data; And a data output unit configured to temporarily store image data encoded by the encoding unit, and to transmit the stored encoded image data to a receiving end, wherein the receiving end is a backend chip or a baseband chip. . The data output unit may skip a processing of the following frame when the input start information of the following frame is received from the image sensor or the encoding unit during the processing of the preceding frame by the encoding unit. The image sensor may be input to the encoding unit.

According to another aspect of the present invention for achieving the above object, there is provided an image signal processing method performed in an image signal processor and / or a recording medium on which a program for performing the method is recorded.

According to a preferred embodiment of the present invention, in an image signal processing method performed in an image signal processor of an imaging apparatus, an image encoded by encoding image data corresponding to an electrical signal input from an image sensor by a predetermined encoding method is encoded. Generating data; Storing the encoded image data; And outputting the stored encoded image data to a receiving end, wherein the receiving end is a back end chip or a baseband chip, and when input start information of a subsequent frame is input from the image sensor during processing of a preceding frame, The image signal processing method is provided, characterized in that the processing of the following frame is skipped.

The predetermined encoding scheme may be at least one of a JPEG encoding scheme, a BMP encoding scheme, an MPEG encoding scheme, and a TV out scheme.

A clock signal and a valid data enable signal may be output to the receiving end only in an output period of valid data among the stored encoded data. Invalid data may be data including 0x00.

The valid data enable signal may be interpreted as a write enable signal at the receiving end.

Whether encoding of the preceding frame is completed may be determined using header information and tail information of the stored encoded image data.

Hereinafter, an encoded data transfer method and an imaging apparatus for performing the method according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention with reference to the accompanying drawings, the same or corresponding components will be given the same reference numerals and redundant description thereof will be omitted. In addition, in the following description of the embodiments of the present invention, only the processing operations of the image signal processor, which is the core of the present invention, will be described. However, the scope of the present invention is not limited thereto.

4 is a view schematically showing the configuration of an imaging device according to an exemplary embodiment of the present invention, and FIG. 5 is a view briefly showing the configuration of a data output unit 430 according to an embodiment of the present invention. Is a diagram illustrating a signal waveform shape for outputting encoded data of the image signal processor 120 according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the imaging apparatus according to the present invention includes an image sensor 110, an image signal processor 400, and a back end chip 405. In addition, it will be apparent that the imaging apparatus may further include a display unit 150, a memory, a baseband chip 140, a key input unit, and the like, and thus description thereof will be omitted.

The image signal processor 400 includes a preprocessor 410, a JPEG encoder 420, and a data output unit 430. Of course, the image signal processor 400 may further include a clock generator for internal operation.

The preprocessor 410 performs a preprocessing process for the processing of the JPEG encoder 420. The preprocessor 410 may receive raw data from each image line 110 for each frame and process the raw data for each frame, and then transfer the raw data to the JPEG encoder 420.

The preprocessing may include color space transformation, filtering, downsampling, and the like.

Color Space Transformation converts the RGB color model to a YUV (or YIQ) color model because it can reduce the amount of information without being aware of the difference in picture quality. .

Filtering is a process of smoothing an image with a low pass filter to increase the compression ratio.

Downsampling (Color SubSampling) is the process of downsampling the chrominance signal components by using all the Y values and using only some of the other values.

The JPEG encoder 420 compresses the preprocessed raw data in the same manner as described above to generate JPEG encoded data. The JPEG encoder 420 may include a memory for temporarily storing the processed raw data input from the preprocessor 410 in order to be divided into a predetermined block unit (for example, 8 × 8) for encoding processing. It may include. That is, the image signal processor 400 according to the present invention may further perform encoding of image data, unlike the conventional image signal processor 120.

The data output unit 430 transfers the JPEG encoded data generated by the JPEG encoder 420 to the back end chip 405 (or the camera control processor (CCP)).

The data output unit 430 receives a V_sync generator when the V_sync_I signal for notifying input of a subsequent frame is input from the image sensor 110 even though the encoding process for one frame is not completed by the JPEG encoder 420. 520-see FIG. 5) so that the output of the V_sync signal corresponding to the corresponding frame is skipped. Since the V_sync_I signal is a signal for notifying an input for a subsequent frame, it may be referred to herein as a "following frame input notification signal" for convenience.

As a result, the V_sync generator 520 maintains the V_sync signal output to the back end chip 405 in a low state (see V_sync2 in the dotted line form shown in FIG. 6).

Of course, in this case, the data output unit 430 may output the V_sync_skip signal to the image sensor 110, the preprocessor 410, or the JPEG encoder 420 to skip the output and / or processing of the subsequent frame corresponding to the V_sync_I signal. Can also be sent. For example, when the image sensor 110 receives the V_sync_skip signal, the raw data of the frame corresponding to the V_sync_I signal may not be transmitted to the preprocessor 410. When the preprocessor 410 receives the V_sync_skip signal, the preprocessing unit 410 may skip processing the raw data of the frame corresponding to the V_sync_ski signal or may not transmit the processed raw data to the JPEG encoder 420. Similarly, when the JPEG encoder 420 receives the V_sync_skip signal, the JPEG encoder 420 may not encode the processed raw data of the frame corresponding to the V_sync_Ip signal, or may prevent the processed raw data received from the preprocessor 410 from being stored in the memory. .

By the above-described process, even if the raw data corresponding to the first, second, and third frames are sequentially input from the image sensor 110, the back end chip 405 is controlled by the operation or control of the data output unit 430. Only encoded image data corresponding to the first and third frames may be input. This is because the data output unit 430 processes the first frame so that the raw data corresponding to the second frame is not input or the JPEG encoder 420 skips the processing of the raw data corresponding to the second frame. Because it can print.

Here, the image sensor 110, the preprocessor 410, or the JPEG encoder 420 should be pre-implemented to perform a predetermined operation when the V_sync_skip signal is received from the data output unit 430. Design and implementation method of the above-described components will be easily understood by those skilled in the art through the description of the specification will be omitted.

When the back end chip 405 receives, for example, a command to capture a picture from the baseband chip 140 that performs overall operation control of the portable terminal, the image quality-enhanced JPEG encoding received from the image signal processor 400 is received. The received data is stored in the memory, and the baseband chip 140 can be read and processed.

5 illustrates a detailed configuration of the data output unit 430.

Referring to FIG. 5, the data output unit 430 includes an AND gate 510, a V_sync generator 520, an H_sync generator 530, a transmission delay unit 540, and a transmission control unit 550. ).

The AND gate 510 outputs a clock signal (this signal may be referred to herein as a P_CLK or P_CLK signal) to the backend chip 405 only when signals are input to all inputs. That is, the clock signal is input only when the clock signal is input from a clock generator (not shown) included in the image signal processor 400 and the clock control signal is received from the transmission controller 550 to indicate the clock signal output. Is output to the backend chip 405. The clock control signal may be in the form of a high signal or a low signal, and a P_CLK enable or P_CLK disable signal, respectively (this signal is referred to herein as a P_CLK_DISABLE or clock disable signal). May be named).

The V_sync generator 520 generates and outputs a vertical synchronization signal (this signal may be referred to herein as a V_sync or V_sync signal) for indicating a valid period under the control of the transmission controller 550. The V_sync generator 520 outputs a high V_sync signal until the output command of the V_sync signal is input from the transmission control unit 550 and the output termination command of the V_sync signal is input. It will be apparent to those skilled in the art that the vertical sync signal means that the input of each frame will be initiated.

The H_sync generator 530 receives an output command under the control of the transmission control unit 550 (that is, a valid data enable signal (this signal may be referred to herein as an H_REF or H_REF signal), and outputs an H_REF signal. The valid data enable signal H_REF in the high state is generated and output until the end command is input. The high period of the valid data enable signal coincides with the output period of the JPEG encoded data in the transmission delay unit 540.

The transmission delay unit 540 receives and temporarily stores JPEG encoded data by the JPEG encoder 420, and transfers the JPEG encoded data to the backend chip 405 under the control of the transmission control unit 550. The transmission delay unit 540 sequentially delays the encoded image data input from the JPEG encoder 420 for a predetermined time (for example, during the time when the transmission control unit 550 controls each component). The chip 405 may be transmitted, or may be transmitted to the backend chip 405 by a predetermined unit (eg, a processing block unit for encoding, a frame unit, etc.). The transmission delay unit 540 may include, for example, a register for delaying and outputting data input from the JPEG encoder 420 for a predetermined time (for example, 2 to 3 clocks).

When the JPEG encoder 420 includes an output memory for outputting encoded image data, the transmission delay unit 540 may receive encoded data from the output memory. The back end chip 405 stores the received JPEG encoded data in the memory so that the baseband chip 140 can use it as needed.

The transmission control unit 550 controls the output of the clock control signal, the V_sync generator 520, the H_sync generator 530, and the transmission delay unit 540 to control the output state of each signal (ie, P_CLK, H_sync, V_sync, and data). To control.

The transmission control unit 550 captures 'START MARKER' and 'STOP MARKER' from the JPEG header and tail of the data stored in the transmission delay unit 540 to recognize the information about the start and end of the JPEG encoding. Can be. That is, through this, the JPEG encoder 420 may recognize whether all one frame is encoded.

If the V_sync_I signal is input from the image sensor 110 even though the JPEG encoding is not completed, as described in detail above, the transmission controller 550 controls the V_sync generator 520 to skip the output of the V_sync signal. To control. That is, if the current V_sync generator 520 is outputting the low state V_sync signal to the back end chip 405, it will control to maintain the current state.

Then, as described in detail above, in this case, the transmission control unit 550 outputs and processes the V_sync_skip signal to the image sensor 110, the preprocessor 410, or the JPEG encoder 420 for the subsequent frame corresponding to the V_sync_skip signal. (E.g., JPEG encoding) or the like may be controlled to be skipped.

If data corresponding to the V_sync_I signal is not input from the preceding component (for example, when the image sensor 110 which receives the V_sync_skip signal does not output raw data corresponding to the V_sync_I signal), the input data is inputted. If the following component can delete (for example, when the JPEG encoder 420 receiving the V_sync_skip signal deletes the processed raw data received from the preprocessor 410 corresponding to the V_sync_I signal without encoding), This is because the following components do not need to perform unnecessary processing. When using this method, each component of the image signal processor 400 performs a predetermined function, but since unnecessary processing of subsequent frames is not unnecessary, there is an effect of suppressing unnecessary power consumption or processing efficiency reduction.

6 illustrates a waveform of a signal input to the back end chip 405 under the control of the transmission control unit 550.

As shown in FIG. 6, while invalid encoding data (0x00) is output, the back-end chip is turned off (dashed line portion of the P_CLK signal shown in FIG. 6) to be output to the back-end chip 405. Unnecessary operation of 405 can be minimized. As a result, power consumption of the back end chip 405 may be minimized. Of course, the type of invalid data (that is, data that does not actually constitute an image) mentioned in the JPEG standard or the like is not limited to 0x00, and 0x00 is merely an example as invalid data in the present specification.

In addition, when the JPEG encoder 420 encodes an image of one frame (for example, the nth input frame, where n is a natural number) received from the image sensor 110 is slow (for example, When the V_sync_I signal is input, which means that input of a new frame is started while encoding one frame, encoding on a subsequent frame (for example, the n + 1st input frame) cannot be performed simultaneously. (A data error may occur when performed at the same time.) The data output unit 430 may be configured such that the V_sync signal for the next frame remains low (that is, the V_sync signal shown in FIG. 6) as shown in FIG. 6. As a dotted line part, the V_sync2 signal output at the corresponding time point according to the related art is skipped according to the present invention) so that JPEG encoding can be completed. Under the control of the data output unit 430, the JPEG encoder 420 skips encoding of the next frame. Of course, when the transmission control unit 550 transmits the V_sync_skip signal to the image sensor 110 or the preprocessor 410, the JPEG encoder 420 may not be provided with data corresponding to V_sync_I from a preceding component.

The conventional back end chip 405 is implemented to receive data in YUV / BAYER format, and uses the P_CLK, V_sync, H_REF, and DATA signals as an interface for receiving such data.

In consideration of this, the image signal processor 400 of the present invention is implemented to use the same interface as in the prior art.

Thus, it is apparent that the present invention can be port matched even when the back end chip 405 is implemented by a conventional back end chip design method.

For example, if the operation of the general back-end chip 405 is initialized from the interrupt of the rising edge of the V_sync signal, the present invention also applies the conventional interface structure in the same way, so that the existing V_sync signal is outputted. Likewise, by inputting the corresponding signal to the back end chip 405, interfacing between the chips is possible.

Similarly, a typical backend chip 405 should generate a V_sync rising interrupt, and also enable write enable of the valid data enable signal H_REF in memory when receiving data from the image signal processor 400. Considering the use as a signal, the power consumption of the back end chip 405 can be reduced by using the signal output method according to the present invention.

Until now, the image signal processor 400 has been described based only on the case of using the JPEG encoding scheme, but other encoding schemes such as BMP encoding scheme, MPEG (MPEG 1/2/4, MPEG-4 AVC) encoding scheme, TV out scheme, etc. Obviously, the same data transmission scheme can be used even if it supports it.

As described above, the encoded data transfer method and the imaging device performing the method according to the present invention have an effect of improving processing efficiency and preventing power consumption of the backend chip.

In addition, the present invention has an advantageous effect in terms of hardware design and control by using a general interface structure in providing the encoded data to the back-end chip to the image signal processor.

In addition, the present invention has the effect that the image signal processor can determine whether to encode the input frame according to the encoding speed can perform a smooth encoding operation.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (17)

In the image signal processor of the imaging device, An encoding unit for encoding the image data corresponding to the electrical signal input from the image sensor to generate encoded image data; And And a data output unit configured to temporarily store image data encoded by the encoding unit, and transfer the stored encoded image data to a receiving end. The data output section signals a subsequent frame input notification signal that notifies the start of input of an electrical signal for the n + 1th frame from the image sensor or the encoding section during transmission of the encoded image data of the nth frame processed by the encoding section. When the V_sync_I signal) is input, a skip command for skipping the processing of the n + 1 th frame is input to the encoding unit. By the skip command, the encoding unit skips encoding of the image data for the n + 1 th frame input from the image sensor, And n is any natural number. The method of claim 1, And the encoding unit encodes the image data in at least one of a JPEG encoding scheme, a BMP encoding scheme, an MPEG encoding scheme, and a TV out scheme. The method of claim 1, An image signal processor further comprising a clock generator. The method of claim 1, And the data output unit outputs a clock signal to the receiving end only in a section in which valid data is transmitted. The method of claim 3, And the data output unit further outputs a V_sync signal and a valid data enable signal to the receiving end. The method of claim 5, The data output unit, An AND gate for stopping output of a clock signal input from the clock generator when a clock disable signal is input; A V_sync generator for outputting a vertical sync signal in a high or low state according to a vertical sync signal control command; An H_sync generator for outputting a valid data enable signal in a high or low state according to a valid data enable control command; A transmission delay unit which temporarily stores the encoded data and outputs the stored encoded data according to a data output control command; And And a transmission controller configured to generate and output the clock disable signal, the vertical synchronization signal control command, the valid data enable control command, and the data output control command. And when the encoded data is stored in the transmission delay unit, the transmission control unit outputs the clock signal and the valid data enable signal only to an output section of valid data among the encoded data. The method of claim 6, And the valid data enable signal is interpreted as a write enable signal at the receiving end. The method of claim 6 And the transmission controller determines whether the n-th frame has been encoded by using header information and tail information of the encoded image data stored in the transmission delay unit. The method of claim 8, If a subsequent frame input notification signal (V_sync_I signal) corresponding to the n + 1th frame is input during transmission of the encoded image data of the nth frame, the transmission control unit outputs the high or low state by the V_sync generator. And control the vertical sync signal to maintain its current state. In the image signal processor of the imaging device, A clock generator; An encoding unit for encoding the image data corresponding to the electrical signal input from the image sensor to generate encoded image data; An AND gate for stopping output of a clock signal input from the clock generator when a clock disable signal is input; A V_sync generator for outputting a vertical sync signal in a high or low state according to a vertical sync signal control command; An H_sync generator for outputting a valid data enable signal in a high or low state according to a valid data enable control command; A transmission delay unit which temporarily stores the encoded data and outputs the stored encoded data according to a data output control command; And And a transmission controller configured to generate and output the clock disable signal, the vertical synchronization signal control command, the valid data enable control command, and the data output control command. The clock signal, the vertical synchronization signal, the valid data enable signal, and the encoded data are output to a receiver according to a predetermined condition. The transmission control unit may transmit a subsequent frame input notification signal that notifies the start of input of an electrical signal for the n + 1th frame from the image sensor or the encoding unit during the output of the encoded image data of the nth frame processed by the encoding unit. When the V_sync_I signal) is input, a skip command for skipping the processing of the n + 1 th frame is input to the encoding unit. By the skip command, the encoding unit skips encoding of the image data for the n + 1 th frame input from the image sensor, And n is any natural number. The method of claim 10, And the encoded data valid only in a section in which the valid data enable signal is in a high state. An imaging device comprising an image sensor and an image signal processor, The image signal processor, An encoding unit for encoding the image data corresponding to the electrical signal input from the image sensor to generate encoded image data; And And a data output unit configured to temporarily store image data encoded by the encoding unit, and transfer the stored encoded image data to a receiving end. The data output section signals a subsequent frame input notification signal that notifies the start of input of an electrical signal for the n + 1th frame from the image sensor or the encoding section during transmission of the encoded image data of the nth frame processed by the encoding section. When the V_sync_I signal) is input, a skip command for skipping the processing of the n + 1 th frame is input to the encoding unit. By the skip command, the encoding unit skips encoding of the image data for the n + 1 th frame input from the image sensor, N is an arbitrary natural number. In the image signal processing method performed in the image signal processor of the imaging device, Encoding the image data corresponding to the electrical signal input from the image sensor to generate encoded image data; Storing the encoded image data; And Outputting the stored encoded image data to a receiving end; If a subsequent frame input notification signal (V_sync_I signal) for notifying the start of the input of the electrical signal for the n + 1th frame is input from the image sensor while outputting the encoded image data of the nth frame, the image sensor is inputted from the image sensor. Skips encoding and outputting image data for the n + 1 th frame, And n is an arbitrary natural number. The method of claim 13, And the image data is encoded in at least one of a JPEG encoding scheme, a BMP encoding scheme, an MPEG encoding scheme, and a TV out scheme. The method of claim 13, And a valid data enable signal is output to the receiving end only in an output section of valid data among the stored encoded data. The method of claim 15, And the valid data enable signal is interpreted as a write enable signal at the receiving end. The method of claim 13, The encoding of the n-th frame is determined using the header information and tail information of the stored encoded image data, characterized in that the image signal processing method.

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