KR101681350B1 - Variable capacitor circuit - Google Patents

Abstract

The present invention relates to a variable capacitor circuit, comprising: a plurality of capacitors connected in parallel; A plurality of variable switch units connected in series with the respective capacitors; And a common switch unit connected to each of the variable switch units via a node a; Wherein the common switch section includes a plurality of switch elements each having an m x n array.

Description

Variable Capacitor Circuit {VARIABLE CAPACITOR CIRCUIT}

The present invention relates to a variable capacitor circuit, and more particularly, to a variable capacitor circuit having an improved Q value.

There are various kinds of frequency band signals in wireless communication. For example, in the case of UMTS (Universal Mobile Telecommunication System), which is a 3G standard, which has a higher transmission rate than the second generation standard, BAND 1 (transmission frequency band: 1920-1980 MHz) and BAND 2 (transmission frequency band: 1850-1910 There are several subdivided frequency bands such as BAND 4 (transmission frequency band: 1710-1770 MHz), BAND 5 (transmission frequency band: 824-849 MHz) and BAND 8 (transmission frequency band: 880-915 MHz) do.

Also, GSM 900 (transmission frequency band: 880-915 MHz), DCS 1800 (transmission frequency band: 1710-1785 MHz), GSM 850 (transmission Frequency band: 824-849 MHz) and PCS 1900 (transmission frequency band: 1850-1910 MHz).

In addition, recently, fourth generation mobile communication, which is termed LTE (Long Term Evolution), is emerging. As such, as the fourth generation mobile communication network is added to the third generation mobile communication network, a frequency band to be supported by one mobile phone is increasing.

According to such technical requirements, mismatching problem between the antenna and the transmission circuit becomes increasingly important issue. This is because mismatch between the antenna and the transmission circuit increases the power consumption of the power amplifier (PA) and deteriorates the reception performance of the low noise amplifier (LNA).

In order to solve the mismatch between the antenna and the transmission circuit, the conventional portable terminal uses a FMN (Fixed Matching Network) method using a fixed LC (L: Inductor, C: Capacitor) circuit. When the FMN scheme is used, much time is required in developing a terminal to find an optimal LC circuit element value for antenna matching. Furthermore, since the LC circuit element value can not be changed according to the electric field, there is a problem that a radio frequency (RF) performance problem, particularly a weak electric field, frequently causes performance problems such as call drop and mute There are disadvantages.

A technique designed to compensate for the disadvantages of the FMN scheme is a TMN (Tunable Matching Network) scheme. The TMN scheme uses a variable LC circuit instead of a fixed LC circuit and performs antenna matching with an optimal LC circuit element value according to an electric field situation and a user environment so that RF performance can be improved in various electric field situations without changing an antenna .

The variable LC circuit mainly performs the matching by varying the capacitance value C of the capacitor. In this sense, the variable LC circuit is also defined as a variable capacitor circuit. A capacitor element mainly used in such a variable capacitor circuit is a metal-insulator-metal (MIM) capacitor having an advantage in terms of cost, and a variable capacitor circuit using the same is disclosed in Korean Patent Publication No. 2006-0075660 , Prior art document).

The variable capacitor circuit disclosed in the prior art references a plurality of capacitors connected in series between a circuit input node and an output node and controls the capacitances between the input and output nodes by controlling them with a switching transistor.

However, an important factor in the variable capacitor circuit is the reversibility and the Q factor (Quality Factor) of the variable capacitor. When the capacitance value is increased by using the variable capacitor circuit shown in the prior art document, There is a problem that the impedance value increases and the Q value deteriorates.

On the other hand, in the publication No. 20110002080 published in the United States patent publication, a variable capacitor circuit which varies a capacitance value C in a binary manner is proposed. This arrangement prevents the Q value from deteriorating by arranging a unit capacitor row composed of one capacitor and a plurality of switch elements in accordance with the capacitance value C that increases proportionally.

However, when the capacitance value is changed by using the variable capacitor circuit having such a structure, it is possible to prevent the Q value from deteriorating. However, as the unit capacitor row increases, the capacitors included therein also increase accordingly. However,

Patent Document: Korean Patent Publication No. 2006-0075660 Patent Document: U.S. Published Patent Application No. 20110002080

SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable capacitor circuit with improved Q value.

According to an aspect of the present invention, there is provided a semiconductor device including: a plurality of capacitors connected in parallel; A plurality of variable switch units connected in series with the respective capacitors; And a common switch unit connected to each of the variable switch units via a node a; Wherein the common switch portion includes a plurality of switch elements arranged in an m x n array.

Each of the capacitors is connected to a first RF terminal via a node b, and the common switch part is connected to a second RF terminal through a node c.

Also, a variable capacitor circuit in which a capacitance value (C) varies in accordance with an on / off operation of each variable switch section is provided.

Further, the variable switch section includes a plurality of switch elements each of which is constituted by a k × 1 array.

Also, the k and / or l values provide a variable capacitor circuit that is different for each variable switch portion.

Also, the value of l is equal to the value of n, providing a variable capacitor circuit.

Also, the k value is 1, which provides a variable capacitor circuit.

Also, a variable capacitor circuit is provided in which the capacitance values (C) of the respective capacitors are different from each other.

In addition, the capacitor provides a variable capacitor circuit having a metal insulator metal (MIM) structure.

The variable capacitor circuit may further include a decoder including a plurality of output terminals coupled to the variable switch parts in a one-to-one relationship, and controlling ON / OFF operations of the variable switch parts through the output terminal.

According to the variable capacitor circuit according to the present invention, the Q value can be improved without adding any additional cost.

1 is a detailed circuit diagram of a variable capacitor circuit according to the present invention.
2 is a graph showing a Q value according to a capacitance value in a variable capacitor circuit according to the present invention.

The advantages and features of the present invention and the techniques for achieving them will be apparent from the following detailed description taken in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The present embodiments are provided so that the disclosure of the present invention is not only limited thereto, but also may enable others skilled in the art to fully understand the scope of the invention. Like reference numerals refer to like elements throughout the specification.

The terms used herein are intended to illustrate the embodiments and are not intended to limit the invention. In this specification, the singular forms include plural forms unless otherwise specified in the text. It is to be understood that the terms " comprise, " and / or " comprising ", as used herein, mean that a component, step, operation and / And does not exclude the presence or addition thereof.

1 is a detailed circuit diagram of a variable capacitor circuit according to the present invention.

1, a variable capacitor circuit according to the present invention includes a plurality of capacitors C1, C2, C3, C4, and C5 connected in parallel and a plurality of capacitors C1, C2, C3, C4, A plurality of variable switch parts S11, S12, S13, S14 and S15 connected in series and a common switch part S2 connected to the variable switch parts S11, S12, S13, S14 and S15 via the node a .

The number of the capacitors C1, C2, C3, C4 and C5 and the variable switch sections S11, S12, S13, S14 and S15 are not limited to a certain number. In this case, variable capacitors constituted by five capacitors and variable switch sections It will be explained by reference.

Each of the capacitors C1, C2, C3, C4, and C5 may be connected to a first RF terminal through a node b, and the common switch S2 may be connected to a second RF terminal through a node c. Accordingly, in the variable capacitor circuit according to the present invention, the capacitance value can be varied according to the signal direction between the first RF terminal and the second RF terminal.

Here, the first and second RF terminals may be connected to input nodes or output nodes of a TMN (Tunable Matching Network) circuit. Therefore, when the first RF terminal is connected to the output node of the TMN circuit, the second RF terminal can be connected to the input node. On the contrary, when the first RF terminal is connected to the input node of the TMN circuit, May be coupled to an output node.

The capacitors C1, C2, C3, C4 and C5 may be metal insulator metal (MIM) capacitors and the capacitances of the capacitors C1, C2, C3, C4 and C5 may be different from one another. For example, the capacitance of the capacitor C1 may be 1C, the capacitance of the capacitor C2 may be 2C, the capacitance of the capacitor C3 may be 4C, the capacitance of the capacitor C4 may be 8C, and the capacitance of the capacitor C5 may be 16C. In this case, the variable capacitor circuit according to the present invention has a variable capacitance value in a binary manner.

The variable switch units S11, S12, S13, S14 and S15 may be constituted by a plurality of switch elements connected in a k × 1 arrangement (k, 1 is an integer of 1 or more).

In the embodiment of the present invention, the switch element is a field effect transistor (FET), but a bipolar junction transistor (BJT), a silicon-controlled rectifier (SCR), a gate-turn-off thyristor (GTO) , An insulated gate bipolar transistor (IGBT), or the like may be used.

 K denotes the number of switch elements connected in series in order to distribute the voltage applied to the variable capacitor circuit, and 1 denotes the number of switch elements connected in parallel for improving the Q value.

As the value of k increases (that is, as the number of switch elements connected in series increases), the impedance value depending on the switch element in an on state increases to deteriorate the Q value. It is preferable to set the minimum value within the range to be distributed. In the embodiment of the present invention, the value of k is set to 1 for efficient use of space.

Since the impedance value according to the on-state switch element is divided by 1 and decreased as the value of 1 is larger (i.e., the number of the switch elements connected in parallel increases) Is set to the maximum value within the maximum permissible range that can be mounted in the product.

The value of k and / or l may be set differently for each variable switch unit S11, S12, S13, S14, and S15. For example, the first type includes a variable switch section S11 having a 2 × 3 array, a variable switch section S12 having a 2 × 4 array, a variable switch section S11 having a 3 × 2 array having a second type, A variable switch section S12 of a 2x3 array, a variable switch section S11 of a 3x2 array, and a variable switch section S12 of a 3x2 array.

The variable switch units S11, S12, S13, S14, and S15 are individually turned on / off according to the control signal of the decoder to vary the capacitance value of the variable capacitor circuit according to the present invention.

For example, when the capacitance of the capacitor C1 is 1C, the capacitance of the capacitor C2 is 2C, the capacitance of the capacitor C3 is 4C, the capacitance of the capacitor C4 is 8C, and the capacitance of the capacitor C5 is 16C, The capacitance value of the variable capacitor circuit according to the present invention changes to 1 C when the switch S11 is turned on and the variable switch portions S12, 13, 14, and 15 are turned off.

Then, when the variable switch portions S11 and S12 are turned on and the other variable switch portions S13, 14 and 15 are turned off, the capacitance value of the variable capacitor circuit according to the present invention is changed to 3C .

As described above, the variable capacitor circuit according to the present invention controls the ON / OFF operations of the variable switch parts S11, S12, S13, S14, and S15 individually through the decoder, so that the capacitors C1, The capacitance value between 0 and 31C can be varied in a binary manner when the capacitance of the capacitor C2 is 2C, the capacitance of the capacitor C3 is 4C, the capacitance of the capacitor C4 is 8C, and the capacitance of the capacitor C5 is 16C .

The decoder is connected to the output terminals out1 (out1) corresponding to the variable switch parts S11, S12, S13, S14 and S15, out2, out3, out4 and out5 and the output terminals out1, out2, out3, out4 and out5 are connected in a one-to-one manner to the variable switch parts S11, S12, S13, S14 and S15.

For example, if the variable switching unit S11 is a switching element included in the variable switching unit S11, the gate terminals of all FETs in the variable switching unit S11 are connected to the output terminal out1 of the decoder And the on / off operation of all the FETs in the variable switch unit S11 is performed integrally according to the control signal input from the output terminal out1.

The common switch unit S2 may be composed of a plurality of switch elements connected in an mxn array (m, n is an integer of 1 or more). Similarly to the variable switch parts S11, S12, S13, S14 and S15, m denotes the number of switch elements connected in series in order to distribute a voltage applied to the variable capacitor circuit, and n denotes a Q value improvement Which means the number of switching elements connected in parallel.

K of the variable switch sections S11, S12, S13, S14, and S15 and m of the common switch section S2 are the number of switch elements for voltage distribution, and k and m are in correlation with each other. Therefore, if the value of k is set small, the value of m should be set large, and if the value of k is set large, the value of m may be set small.

However, since the variable switches S11, S12, S13, S14 and S15 are designed in the same number as the capacitors C1, C2, C3, C4 and C5, It is preferable to set the value of k to 1 for use and set the value of m to a plurality of values.

As the value of n is larger than the value of n, the impedance value corresponding to the on-state switch element is divided and divided by n, so that the value of n is the maximum allowable value of the switch element It is preferable to set the value of n and the value of 1 equal to each other.

The common switch S2 is connected to the output terminal out6 of the decoder so that an on / off operation is performed according to a control signal input from the output terminal out6. That is, the gate terminals of all the switch elements included in the common switch S2 are connected to the output terminal out6 of the decoder. On / off operations of all the FETs are input from the output terminal out6 In accordance with the control signal.

The decoder outputs a control signal of the output terminal out6 together with a control signal of one of the output terminals out1 to out5.

For example, when a control signal is outputted through the output terminal out1, a control signal of the output terminal out6 is outputted together. When a control signal is outputted through the output terminal out1 and the output terminal out2 And the control signal of the output terminal out6 is outputted together.

Accordingly, when the variable switch portion of any one of the plurality of variable switch portions S11, S12, S13, S14, and S15 is turned on, the common switch portion S2 is also turned on do.

In the variable capacitor circuit according to the present invention operating in this manner, the total impedance value (Ron, total) according to the on-state switch element is given by the following equation (1) S12, S13, S14, S15) are the same, the value of k is 1, and the value of 1 is set equal to the value of m.

Accordingly, the Q value of the variable capacitor circuit according to the present invention is given by Equation 2 below.

That is, the variable capacitor circuit according to the present invention has a total value of impedance (Ron, total) according to the on-state switch element is divided by n of the common switch part S2 regardless of a certain capacitance value, .

2 is a graph showing a Q value according to a capacitance value in a variable capacitor circuit according to the present invention.

Conventional variable capacitor circuits (variable capacitor circuits disclosed in U.S. Patent Publication No. 20110002080) increase the number of unit capacitors so that the capacitors included therein increase accordingly, so that the Q value is constant.

However, in the case of the variable capacitor circuit according to the present invention, since the total impedance value Ron, total according to the on-state switch element is divided by n, the variable capacitance value (i.e., C ) Becomes smaller, the Q value increases proportionally.

The foregoing detailed description is illustrative of the present invention. It should be understood that the foregoing description is only illustrative and illustrative of preferred embodiments of the invention, and that the invention may be used in various other combinations, modifications and environments. That is, it is possible to make changes or modifications within the scope of the concept of the invention disclosed in this specification, the disclosure and the equivalents of the disclosure and / or the scope of the art or knowledge of the present invention. It should be understood that the above-described embodiments are intended to illustrate the best mode contemplated for carrying out the invention, and are not intended to limit the scope of the invention to the particular forms of application, Various modifications are also possible. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. It is also to be understood that the appended claims are intended to cover different embodiments.

C1, C2, C3, C4, C5: Capacitors
S11, S12, S13, S14, S15:
S2:

Claims (10)

A plurality of capacitors connected in parallel;
A plurality of variable switch units connected in series with the respective capacitors; And
A common switch unit connected to each of the variable switch units via a node a;
, ≪ / RTI &
Wherein the common switch unit includes a plurality of switch elements arranged in an m x n array,
Variable capacitor circuit.
The method according to claim 1,
Each capacitor being connected to a first RF terminal via a node b and the common switch part being connected to a second RF terminal via a node c,
Variable capacitor circuit.
The method according to claim 1,
Wherein the capacitance value (C) varies depending on the on / off operation of each variable switch part,
Variable capacitor circuit.
The method according to claim 1,
The variable-
and a plurality of switching elements each of which is constituted by a plurality of switching elements,
Variable capacitor circuit.
5. The method of claim 4,
The k and / or l values may be different for each variable switch unit,
Variable capacitor circuit.
5. The method of claim 4,
Wherein the l value is equal to the n value,
Variable capacitor circuit.
5. The method of claim 4,
Wherein the k value is 1,
Variable capacitor circuit.
The method according to claim 1,
The capacitance values C of the capacitors are different from each other,
Variable capacitor circuit.
The method according to claim 1,
The capacitor
A metal insulator metal (MIM)
Variable capacitor circuit.
The method according to claim 1,
A decoder including a plurality of output terminals connected to the variable switch parts in a one-to-one manner and controlling ON / OFF operations of the variable switch parts through the output terminal;
≪ / RTI >
Variable capacitor circuit.

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