KR101681122B1 - Method for fabricaing thin film transistor of liquid crystal display device - Google Patents

Abstract

A method of manufacturing a thin film transistor for a liquid crystal display, the method comprising: forming a gate electrode on a transparent insulating substrate; Forming a gate insulating film on an insulating substrate including a region covering the gate electrode; An undoped pure amorphous silicon layer formed on the gate insulating film and an n-type impurity amorphous silicon layer doped with an n-type impurity at a high concentration are sequentially deposited, and then a portion excluding a region corresponding to the gate electrode Forming an active layer composed of a pure amorphous silicon layer and an n-type impurity amorphous silicon layer by etching; Forming a metal layer on the entire surface of the transparent insulating substrate including the singly active layer; Etching the metal layer to form a source electrode and a drain electrode so as to be spaced apart from each other; And forming an ohmic contact layer by etching the n-type impurity amorphous silicon layer so that a pure amorphous silicon layer in a predetermined region corresponding to the gate electrode is exposed.

A pure amorphous silicon layer, an impurity amorphous silicon layer, a resistive contact layer, an active layer

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a thin film transistor for a liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) for a liquid crystal display (LCD), and more particularly, to a thin film transistor And a method of manufacturing a thin film transistor for a liquid crystal display device capable of increasing productivity.

Generally, a liquid crystal display device has a liquid crystal layer having an anisotropic permittivity between an array substrate, which is a transparent insulating substrate, and a color filter substrate, and then adjusting the intensity of an electric field formed on the liquid crystal layer to change the molecular arrangement of the liquid crystal material, And a desired image is displayed by adjusting the amount of light transmitted through the color filter substrate, which is a display surface.

As such a liquid crystal display device, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

A structure of a thin film transistor used as a switching element of such a thin film transistor liquid crystal display device will be described with reference to FIG.

1 is a cross-sectional view of a conventional thin film transistor element for a liquid crystal display device.

As shown in Fig. 1, a thin film transistor element for a liquid crystal display according to the related art comprises: a gate electrode 13 formed on a transparent insulating substrate 11; A gate insulating film 15 formed on the gate electrode 13; A semiconductor layer 17 formed of an amorphous silicon material not doped on the gate insulating layer 15 and corresponding to the gate electrode 13 as a channel portion and a semiconductor layer 17 exposed in the channel portion, A source electrode 21a and a drain electrode 21b formed so as to be spaced apart from each other; An ohmic contact layer 19 made of an n + hydrogenated amorphous silicon material formed at an interface between the source electrode 21a and the drain electrode 21b and the semiconductor layer 17 and doped with an n-type impurity at a high concentration, .

The semiconductor layer 17 and the ohmic contact layer 19 constitute an active layer 20. The semiconductor layer 17 is not doped to the position of the gate insulating film 15 covering the upper portion of the gate electrode 13 And a region corresponding to the gate electrode 13 is defined as a channel portion (not shown).

The thickness of the resistive contact layer 19 is about 300 Å and the thickness of the semiconductor layer 17 is about 1700 Å. The total thickness of the active layer 20 Is formed to be 2000 angstroms or more.

In addition, the semiconductor layer 17 is etched to a depth of about 700 ANGSTROM or more when the back channel etching (BCE) of the ohmic contact layer 19 is performed.

However, the thin film transistor structure for a liquid crystal display according to the related art has the following problems.

 The conventional thin film transistor for a liquid crystal display according to the related art can be manufactured by a four mask process by applying a general back channel etching (BCE) process, which is advantageous in terms of process. However, It is difficult to secure the back channel etching depth process margin because the process of forming the source electrode / drain electrode proceeds simultaneously with one mask.

Therefore, in the conventional process, the thickness of the active layer is secured to 2000 ANGSTROM or more to ensure the etching depth of the n + resistive contact layer, and the residual thickness of the constant thickness is maintained, thereby minimizing deterioration of the TFT characteristics.

However, the thin film transistor structure for a liquid crystal display according to the related art has an n + resistive contact layer removing process and a source electrode / drain electrode forming process using the same mask, There is a possibility that a problem of uniformity arises due to scattering. That is, if the n + ohmic contact layer is deeply etched, the thickness of the residue is reduced to reduce the on current (Ion) characteristic of the thin film transistor TFT, and when the thin film is etched, The off current (Ioff) characteristic of the thin film transistor (TFT) is degraded.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide a method of manufacturing a thin film transistor, A thin film transistor for a liquid crystal display device and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor for a liquid crystal display, including: forming a gate electrode on a transparent insulating substrate; Forming a gate insulating film on an insulating substrate including a region covering the gate electrode; An undoped pure amorphous silicon layer formed on the gate insulating film and an n-type impurity amorphous silicon layer doped with an n-type impurity at a high concentration are sequentially deposited, and then a portion excluding a region corresponding to the gate electrode Forming an active layer composed of a pure amorphous silicon layer and an n-type impurity amorphous silicon layer by etching; Forming a metal layer on the entire surface of the transparent insulating substrate including the singly active layer; Etching the metal layer to form a source electrode and a drain electrode so as to be spaced apart from each other; And forming a resistive contact layer by etching the n-type impurity amorphous silicon layer to expose a pure amorphous silicon layer in a predetermined region corresponding to the gate electrode.

The method of manufacturing a thin film transistor for a liquid crystal display according to the present invention has the following effects.

The method for manufacturing a thin film transistor for a liquid crystal display according to the present invention is a method for manufacturing a thin film transistor for a liquid crystal display device in which the thickness of an ohmic contact layer made of n + impurity amorphous silicon is made thinner than before, And it is easy to secure the process margin for the etch depth of the n + resistive contact layer by reducing the scattering range.

The method of manufacturing a thin film transistor for a liquid crystal display according to the present invention is characterized in that when the thickness of the n + resistive contact layer is reduced, ohmic characteristics between the metal layer for the source electrode / drain electrode and the semiconductor layer, This problem can be compensated for by increasing the phosphorus (PH ₃ ) flow rate in the formation of the ohmic contact layer, and the overall thickness of the active layer can be reduced to a slim state, The mobility characteristics and the productivity of the thin film transistor can be increased.

Hereinafter, a method of manufacturing a thin film transistor for a liquid crystal display according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a thin film transistor element for a liquid crystal display according to the present invention.

Fig. 3 is an enlarged cross-sectional view of the "A" portion of Fig. 2, which is an enlarged cross-sectional view showing the thickness of the active layer composed of the semiconductor layer and the ohmic contact layer of the thin film transistor for a liquid crystal display according to the present invention.

As shown in Fig. 2, the thin film transistor element for a liquid crystal display according to the present invention comprises: a gate electrode 103 formed on a transparent insulating substrate 101; A gate insulating film 107 formed on the gate electrode 103; A semiconductor layer 109 composed of a pure amorphous silicon material not doped on the gate insulating layer 107 and corresponding to the gate electrode 103 is defined as a channel portion and the semiconductor layer 109 is exposed in the channel portion A source electrode 115a and a drain electrode 115b formed separately from each other; An ohmic contact layer 111 made of an n + impurity-amorphous silicon material formed at an interface between the source electrode 115a and the drain electrode 115b and the semiconductor layer 109 and having a high concentration of n-type impurities ).

Here, the gate electrode 103 is formed of a metal material selected from a metal material having a low specific resistance such as aluminum (Al) on the transparent insulating substrate 101, and the gate insulating film 107 is formed of a metal material Is formed of an insulating material such as a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like.

The semiconductor layer 109 and the resistive contact layer 111 constitute an active layer 110. The semiconductor layer 109 is not doped at a position covering the gate electrode 103 on the gate insulating film 107 And a region corresponding to the gate electrode 103 is defined as a channel portion (not shown). 3, the thickness T1 of the resistive contact layer 111 is preferably about 100 to 200 angstroms, and the thickness T of the active layer 110 is less than 1500 angstroms. . In particular, the thickness (T1) of the ohmic contact layer 111 made of the n + impurity amorphous silicon material reduces the process time for removing the n + resistive contact layer and facilitates securing the process margin by reducing the scattering area Therefore, as described above, it is preferable to form the layer to a thickness of about 100 to 200 ANGSTROM thinner than the conventional one. However, if the thickness (T1) of the n + resistive contact layer 111 is reduced, the ohmic characteristics between the metal material layer for the source electrode / drain electrode and the semiconductor layer 109 and the on- It is possible to compensate for the decrease in the current characteristic in which the flow rate of the PH ₃ is increased at the time of forming the n + resistive contact layer 111 and to slim the entire thickness T of the active layer 110 The mobility characteristics and the productivity of the thin film transistor (TFT) can be improved.

The source electrode 115a and the drain electrode 115b are formed so as to expose the semiconductor layer 109 from the channel portion (not shown) and to be spaced apart from each other. The source electrode 115a and the drain electrode 115b may be formed of a metal material such as molybdenum (Mo), titanium (Ta), molybdenum alloy (Mo), aluminum and chromium.

Although not shown in the drawing, a protective film (not shown) made of an inorganic insulating material or an organic insulating material such as a silicon nitride film (SiNx) is formed on the thin film transistor element, and the drain electrode 115b A contact hole (not shown) is formed. A pixel electrode (not shown) made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed to be connected to the drain electrode 115b through the contact hole.

A method of manufacturing a thin film transistor for a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

4A to 4J are cross-sectional views illustrating a manufacturing process of a thin film transistor for a liquid crystal display according to the present invention.

5 is a graph showing a change in on-current Ion according to the thickness (T1) of the n + resistive contact layer in the method for manufacturing a thin film transistor for a liquid crystal display according to the present invention.

6 is a graph showing a change in on-current (Ion) according to the flow rate of PH ₃ at the time of forming the n + resistive contact layer in the method for manufacturing a thin film transistor for a liquid crystal display device according to the present invention.

7 is a graph showing a change in on-current Ion according to the thickness T of the active layer in the method for manufacturing a thin film transistor for a liquid crystal display according to the present invention.

4A, a gate electrode layer 103 is first deposited as a first metal layer on a transparent insulating substrate 101, a photoresist film (not shown) is coated on the gate electrode layer 103, The photoresist film (not shown) is selectively removed through a photolithography process and a development process using a first mask to form a first photoresist film pattern 105. At this time, the first metal layer may be formed of a single layer or a double layer structure of chromium (Cr), molybdenum (Mo), aluminum (Al)

Next, using the first photoresist film pattern 105 as a blocking film, the gate electrode layer 103 is selectively patterned to form a gate electrode 103a as shown in FIG. 4B.

4C, a gate insulating film 107 is formed on the entire surface of the insulating substrate 101 covering the gate electrode 103a after removing the remaining first photoresist film pattern 105. Next, as shown in FIG. At this time, the gate insulating layer 107 is selected from an organic insulating material or an inorganic insulating material, preferably selected from inorganic insulating materials, and more preferably selected from silicon insulating materials. As such a silicon-insulating material, for example, a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like can be used.

Then, as shown in FIG. 4D, a semiconductor layer 109 composed of undoped pure amorphous silicon is formed on the gate insulating film 107, and a resistive layer 103 composed of n + impurity amorphous silicon with high concentration of n-type impurity The contact layer 111 is sequentially deposited. At this time, the semiconductor layer 109 and the ohmic contact layer 111 constitute the active layer 110. Here, the thickness (T1) of the ohmic contact layer 111 is preferably about 100 to 200 angstroms. The total thickness T of the active layer 110 is preferably about 1500 Å or less, more preferably about 1300 to about 1500 Å, as shown in FIG.

Particularly, the thickness (T1) of the ohmic contact layer 111 made of the n + -type amorphous silicon reduces the process time for removing the ohmic contact layer, and it is easy to secure a process margin by reducing the scattering region. It is preferable to form it to a thickness of about 100 to 200 ANGSTROM which is a thinner thickness.

However, if the thickness (T1) of the n + ohmic contact layer 111 is reduced, the ohmic characteristics between the metal material layer for the source electrode / drain electrode and the semiconductor layer 109 and the on current (Ion) 6, it is possible to compensate for the degradation of the on-current characteristic by increasing the flow rate of the PH ₃ , and the total thickness T of the active layer 110 ) Can be formed to be slim, thereby improving the mobility characteristics and productivity of the thin film transistor (TFT). In particular, the PH ₃ / SiH ₄ flow rate during the deposition of the resistive contact layer 111 is preferably about 1.0 to 2.5 / cm ³ as shown in FIG. 5, and the resistive contact layer 111 ) Has a phosphorus concentration of about 5 x 10 < ²⁰ > To 5 x 10 < ²¹ > / cm < ² >.

4E, a photoresist film (not shown) is coated on the resistive contact layer 111, and then a photoresist film (not shown) is formed through an exposure process and a development process using a second mask Is selectively removed to form a second photoresist film pattern 113. [

Then, using the second photoresist film pattern 113 as a blocking film, the semiconductor layer 109 composed of the undoped pure amorphous silicon and the n + -type impurity, phosphorus (PH ₃ ) An active layer 110 composed of the semiconductor layer 109 and the ohmic contact layer 111 is formed by selectively patterning the ohmic contact layer 111 composed of impurity amorphous silicon as shown in FIG.

4G, the remaining second photoresist film pattern 113 is removed, and a second metal layer 115 is deposited on the entire surface of the transparent insulating substrate 101 including the active layer 110. Then, do. The second metal layer 115 may be aluminum, chromium, molybdenum, titanium, tantalum or a molybdenum alloy.

4H, a photoresist film (not shown) is coated on the second metal layer 115, and then selectively removed through an exposure process and a development process using a third mask, A photoresist film pattern 117 is formed.

4I, the second metal layer 115 is selectively patterned using the third photoresist film pattern 117 as a blocking film so that the source electrode 115a and the drain electrode 115b are electrically connected to each other .

At this time, dry etching and wet etching may be used at the time of etching the second metal layer 115. That is, after the second metal layer 115 is wet-etched, the remaining material is removed by dry etching to form the source electrode 115a and the drain electrode 115b.

The wet etching is performed by depositing the substrate in an etching solution or spraying the etching solution onto the substrate using an injection nozzle so that the etching solution is reacted with the metal layer 115 to perform an etching operation. At this time, it is preferable that the wet etching solution is formed so as to include a mixed solution of hydrofluoric acid (HF) or phosphoric acid (PH ₃ ).

After the third photoresist film pattern 117 is removed, the source electrode 115a and the drain electrode 115b are shielded to form a gate electrode 103 (a back channel etching (BCE) Etching the resistive contact layer 111 made of n + impurity amorphous silicon so that the semiconductor layer 109 in the region corresponding to the channel region 109 of the semiconductor layer 109 is exposed, 119 are defined, and the resistive contact layers 111 are separated from each other. At this time, the portion of the resistive contact layer 111 located in the channel region and the semiconductor layer 109 are etched by a thickness of about 400 Å or less, for example, through the back channel etching (BCE) process.

Then, as shown in FIG. 4J, after the back channel type rectangular thin film transistor is completed, a protective film 119 is formed on the entire surface of the substrate. At this time, the insulating material used as the protective film 119 is selected from any one of organic insulating materials and inorganic insulating materials, preferably selected from inorganic insulating materials, and more preferably selected from silicon insulating materials. As such a silicon-insulating material, for example, a silicon nitride (SiNx) film, a silicon oxide (SiOx) film, or the like can be used.

Then, a fourth photoresist film (not shown) is coated on the protective film 119, and a fourth photoresist film (not shown) is formed by an exposure process and a developing process using a fourth mask Is selectively removed to form a fourth photoresist film pattern (not shown).

Then, the protective film 119 is selectively patterned using the fourth photoresist film pattern as a blocking film to form a contact hole 121 exposing the drain electrode 115b.

 After removing the remaining fourth photoresist film pattern (not shown), a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the protective film 119.

Next, a photoresist film (not shown) is coated on the transparent conductive material layer (not shown) and selectively removed through an exposure process and a developing process using a fifth mask to form a fifth photoresist film pattern (not shown) .

Then, using the fifth photoresist film pattern (not shown) as a blocking film, the transparent conductive material layer is selectively patterned to form a pixel electrode (not shown) connected to the drain electrode 115b through the contact hole 121 123 are formed.

As described above, the method of manufacturing a thin film transistor for a liquid crystal display according to the present invention reduces the thickness of the ohmic contact layer composed of amorphous silicon doped with n + impurity, thereby reducing the etch depth of the pure amorphous silicon layer Thinning reduces the etching process time of the n + resistive contact layer and reduces the spread range, which is easy to secure a process margin for the etch depth of the n + resistive contact layer. Particularly, the etching process time of the resistive contact layer can be reduced to about half of that of the conventional resistive contact layer, which can significantly reduce the overall process time of the thin film transistor.

The thin film transistor and the method of manufacturing the same according to the present invention are characterized in that when the thickness of the n + resistive contact layer is reduced, ohmic characteristics between the metal layer and the semiconductor layer for the source electrode / (PH ₃ ) flow rate in the formation of the ohmic contact layer to compensate for this problem, and to compensate for this problem, and to improve the overall thickness of the active layer to the slim ), It is possible to increase the mobility characteristics and productivity of the thin film transistor.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand.

Therefore, it should be understood that the above-described embodiments are provided so that those skilled in the art can fully understand the scope of the present invention. Therefore, it should be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, The invention is only defined by the scope of the claims.

1 is a cross-sectional view of a conventional thin film transistor element for a liquid crystal display device.

2 is a cross-sectional view of a thin film transistor element for a liquid crystal display according to the present invention.

3 is an enlarged cross-sectional view of the portion "A" in Fig. 2, which is an enlarged cross-sectional view showing the thickness of an active layer constituted by a semiconductor layer and a resistive contact layer of a thin film transistor for a liquid crystal display according to the present invention.

4A to 4J are cross-sectional views illustrating a manufacturing process of a thin film transistor for a liquid crystal display according to the present invention.

5 is a graph showing a change in on-current Ion according to the thickness (T1) of the n + resistive contact layer in the method for manufacturing a thin film transistor for a liquid crystal display according to the present invention.

FIG. 6 is a graph showing a change in on-current (Ion) according to the flow rate of PH ₃ during the formation of the n + resistive contact layer in the method for manufacturing a thin film transistor for a liquid crystal display according to the present invention.

7 is a cross-sectional view illustrating a method of manufacturing a thin film transistor for a liquid crystal display according to the present invention,

(Ion) according to the thickness (T) of the active layer.

Description of the Related Art [0002]

101: insulating substrate 103a: gate electrode

107: gate insulating film 109: semiconductor layer

110: active layer 111: resistive contact layer

115a: source electrode 115b: drain electrode

119: Protective layer 121: Contact hole

123:

Claims (6)

Forming a gate electrode on the transparent insulating substrate; Forming a gate insulating film on an insulating substrate including a region covering the gate electrode; An undoped pure amorphous silicon layer and an n-type impurity amorphous silicon layer are sequentially deposited on the gate insulating film, and then a portion except for a region corresponding to the gate electrode is etched to form a pure amorphous silicon layer and an n- Forming an active layer composed of an impurity amorphous silicon layer; Forming a metal layer on the entire surface of the transparent insulating substrate including the singly active layer; Etching the metal layer to form a source electrode and a drain electrode so as to be spaced apart from each other; And And forming a resistive contact layer by etching the n-type impurity amorphous silicon layer and the pure amorphous silicon layer such that a pure amorphous silicon layer in a predetermined region corresponding to the gate electrode is exposed, At the time of forming the n-type impurity amorphous silicon layer, PH ₃ / SiH ₄ flow rate was 1.0 to 2.5 pieces / cm ^3, and held in, the phosphorus (phosphorus) concentration in said n-type impurity amorphous silicon layer is 5 × 10 ²⁰ To 5 x 10 < ²¹ > pieces / cm < ² >. The method of claim 1, wherein the n-type impurity-doped amorphous silicon layer has a thickness of 100 to 200 angstroms. delete The method according to claim 1, wherein the active layer composed of the pure amorphous silicon layer and the n-type impurity amorphous silicon layer has a thickness of 1300 to 1500 angstroms. The method of claim 1, wherein forming the resistive contact layer by etching the n-type impurity amorphous silicon layer to expose a predetermined region of the amorphous silicon layer corresponding to the gate electrode comprises: performing a back channel etching process Wherein the thin film transistor is formed over the substrate. 6. The method of claim 5, wherein the n-type impurity amorphous silicon layer and the pure amorphous silicon layer are etched to a thickness of 400 Å or less.

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