KR101675583B1 - Light emitting device - Google Patents

Abstract

An embodiment relates to a light emitting element.
A light emitting device according to an embodiment includes a conductive substrate, a first conductive layer disposed on the conductive substrate and electrically connected to the conductive substrate, a first semiconductor layer disposed on the first conductive layer, an active layer disposed on the first semiconductor layer, A second semiconductor layer disposed on the active layer, at least one via hole extending through the first conductive layer, the first semiconductor layer, and the active layer from the conductive substrate to a predetermined region of the second semiconductor layer, And an insulating layer disposed between the conductive substrate and the second conductive layer, between the first conductive layer and the second conductive layer, and on the side wall of the via hole.

Description

[0001] LIGHT EMITTING DEVICE [0002]

An embodiment relates to a light emitting element.

Light emitting diodes (LEDs) are a type of semiconductor devices that convert electrical energy into light. Light emitting diodes have advantages of low power consumption, semi-permanent lifetime, fast response speed, safety, and environmental friendliness compared with conventional light sources such as fluorescent lamps and incandescent lamps. Accordingly, much research has been conducted to replace an existing light source with a light emitting diode, and a light emitting diode has been increasingly used as a light source for various lamps used outside the room, a lighting device such as a liquid crystal display device, a display board, and a streetlight.

1 is a cross-sectional view of a vertical light emitting device 100 according to the related art.

Hereinafter, for convenience of explanation, it is assumed that a semiconductor layer in contact with the substrate 120 shown in FIG. 1 is an n-type semiconductor layer, and a semiconductor layer formed on the active layer 140 is a p-type semiconductor layer .

1, the light emitting device 100 includes an n-type conductive layer 110, a conductive substrate 120 formed on the n-type conductive layer 110, an n-type semiconductor layer 130 formed on the conductive substrate 120 an active layer 140 formed on the n-type semiconductor layer 130, a p-type semiconductor layer 150 formed on the active layer 140 and a p-type conductive layer 160 formed on the p-type semiconductor layer 150, .

1, when the conductive substrate 120 is used, since a voltage can be applied to the n-type semiconductor layer 130 through the conductive substrate 120, an electrode can be formed on the substrate itself . Accordingly, the n-type electrode 110 is formed on the conductive substrate 120, and the p-type conductive layer 160 is formed on the p-type semiconductor layer 150 to produce a vertical light emitting device.

1, the p-type conductive layer 160 is disposed at the uppermost portion of the light emitting device 100 and is electrically connected to the active layer 140 from the outside in the operation of the light emitting device 100. In this case, Thereby blocking a part of the light emitted from the light source. Accordingly, the vertical type light emitting device 100 shown in FIG. 1 has a disadvantage in that the light loss is large and the luminous efficiency is reduced.

Embodiments are directed to providing a light emitting device having improved current flow activation and heat flow.

A light emitting device according to an embodiment includes a conductive substrate, a first conductive layer disposed on the conductive substrate and electrically connected to the conductive substrate, a first semiconductor layer disposed on the first conductive layer, an active layer disposed on the first semiconductor layer, A second semiconductor layer disposed on the active layer, at least one via hole extending through the first conductive layer, the first semiconductor layer, and the active layer from the conductive substrate to a predetermined region of the second semiconductor layer, And an insulating layer disposed between the conductive substrate and the second conductive layer, between the first conductive layer and the second conductive layer, and on the side wall of the via hole.

A light emitting device according to another embodiment includes a conductive substrate, a first conductive layer disposed on the conductive substrate and electrically connected to the conductive substrate, a first semiconductor layer disposed on the first conductive layer, At least one via hole extending through the first conductive layer, the first semiconductor layer and the active layer from the conductive substrate and projecting to a certain region of the second semiconductor layer, and a second semiconductor layer disposed on the conductive substrate A second conductive line electrically connecting between the via holes, and an insulating layer disposed between the conductive substrate and the second conductive line, between the first conductive layer and the second conductive line, and on the side wall of the via hole.

According to the embodiment, it is possible to provide a light emitting device in which current flow activation and heat flow are improved.

1 is a cross-sectional view of a conventional vertical light emitting device.
2 is a cross-sectional view of a light emitting device according to an embodiment.
3A is a top view of a light emitting device according to another embodiment;
FIG. 3B is a cross-sectional view of the light emitting device taken along the line A-A 'in FIG. 3A; FIG.
4A is a top view of a light emitting device according to another embodiment.
4B is a cross-sectional view of the light emitting device taken along the line B-B 'in FIG. 4A.
4C shows the n-type conductive region of Fig. 4A. Fig.
5 is a cross-sectional view schematically showing a package of a light emitting element;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood, however, that the appended drawings illustrate the embodiments of the present invention in order to more easily describe the present invention and are not intended to limit the scope of the invention. It will be possible.

[Light Emitting Element 1]

2 is a cross-sectional view of a vertical light emitting device 200 according to a first embodiment having a via hole electrode shape. The vertical light emitting device 200 shown in FIG. 2 is a structure for increasing the light emitting efficiency of the vertical light emitting device 100 shown in FIG.

For convenience of explanation, a semiconductor layer which is in contact with the n-type conductive layer 220 through the via holes 220a, 220b and 220c is an n-type semiconductor layer, and the p- The semiconductor layer formed on the p-type semiconductor layer will be described as a p-type semiconductor layer.

The light emitting device 200 shown in Fig. 2 is formed by passing through the p-type conductive layer 240, the p-type semiconductor layer 250, and the active layer 260 from the n-type conductive layer 220, The via holes 220a, 220b, and 220c are extended to a predetermined region of the via hole 220a. Unlike the light emitting device 100 shown in FIG. 1, this structure is advantageous in light extraction efficiency because there is no portion where the upper portion of the n-type semiconductor layer 270 on which light is actually emitted is clogged with the electrode.

[Light Emitting Element 2]

3A is a top view of a light emitting device 300 according to the second embodiment. FIG. 3B is a cross-sectional view of the light emitting device 300 taken along the line A-A 'in FIG. 3A.

3A and 3B, a light emitting device 300 according to an embodiment includes a conductive substrate 310, a first conductive layer 320, a first semiconductor layer 330, an active layer 340, A second conductive layer 360, a via hole 350B, a second conductive layer 350A, and an insulating layer 370. And may include a first electrode pad portion 321 and a second electrode pad portion 351.

For convenience of explanation, the first conductive layer 320 is a p-type conductive layer, the first electrode pad portion 321 is a p-type electrode pad portion, and the first semiconductor layer 330 is a p-type semiconductor layer The second semiconductor layer 360 is an n-type semiconductor layer, the via hole 350B is an n-type conductive via hole, the second conductive layer 350A is an n-type conductive layer, and the second electrode pad portion 351 is n Type electrode pad portion.

The conductive substrate 310 may be formed of one or more of Au, Ni, Al, Cu, W, Si, Se, and GaAs. For example, the conductive substrate 310 may be made of a material in the form of an alloy of Si and Al.

The p-type conductive layer 320 may be disposed on the conductive substrate 310 and electrically connected to the conductive substrate 310. The electrical connection between the p-type conductive layer 320 and the conductive substrate 310 will be described later.

 The P-type conductive layer 320 may be formed of one or more of Ag, Al, Pt, Ni, Pt, Pd, Au, Ir, and a transparent conductive oxide (ITO, GZO). This is because the contact resistance of the p-type semiconductor layer 330 is minimized because the p-type conductive layer 320 is in electrical contact with the p-type semiconductor layer 330 and the light generated in the active layer 340 So as to enhance the luminous efficiency.

The p-type electrode pad portion 321 may be electrically connected to the lower portion of the conductive substrate 321. For example, the p-type electrode pad portion 321 may be bonded to the lower surface of the conductive substrate 321. Or may be omitted.

The p-type semiconductor layer 330 may be disposed on the p-type conductive layer 320. The p-type semiconductor layer 350 is a semiconductor material having a composition formula of InxAlyGa (1-xy) N (0? x? 1, 0? y? 1, 0? x + y? 1), for example, InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN and the like, and a p-type dopant such as Mg or Zn may be doped.

The active layer 340 may be formed of a semiconductor material having a composition formula of InxAlyGa (1-x-y) N (0? X? 1, 0? Y? 1, 0? X + y? When the active layer 340 is formed of a multiple quantum well structure (MQW), the active layer 340 may be formed by stacking a plurality of well layers and a plurality of barrier layers. For example, the InGaN well layer / GaN barrier layer / RTI >

The active layer 340 may be formed by selecting a different material depending on the material of the n-type semiconductor layer 360 and the p-type semiconductor layer 350. That is, the active layer 360 is a layer that converts electrons provided from the n-type semiconductor layer 360 and energy resulting from the recombination of the p-type semiconductor layer 330 into light and emits the light. Accordingly, the active layer 340 is preferably formed of a material having an energy band gap smaller than the energy band gap of the n-type semiconductor layer 340 and the p-type semiconductor layer 330.

The n-type semiconductor layer 360 may be disposed on the active layer 340. The n-type semiconductor layer 360 is a semiconductor material having a composition formula of InxAlyGa (1-xy) N (0? x? 1, 0? y? 1, 0? x + y? 1), for example, InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN and the like, and an n-type dopant such as Si, Ge, or Sn can be doped.

The n-type conductive layer 350A may be disposed on the conductive substrate 310. [ A plurality of n-type conductive via holes 350B electrically connected to each other by the n-type conductive layer 350A may be formed on the n-type conductive layer 350A. Here, the n-type conductive layer 350A may be formed in a layer type connecting the plurality of n-type conductive via holes 350B.

The n-type conductive via hole 350B may be disposed on the n-type conductive layer 350A and may be divided into a through region and a protruding region. Here, the through region means a region passing through the p-type conductive layer 320, the p-type semiconductor layer 330, and the active layer 340 from the n-type conductive layer 350A, And may be a region protruding to a certain region of the layer 360. The upper portion of the protruding region may be electrically connected to the n-type semiconductor layer 360. The upper portion of the protruding region may mean the upper surface of the protruding region, and may include the upper surface and the side surface. Accordingly, the n-type conductive layer 350A can be electrically connected to the n-type semiconductor layer 360 through the n-type conductive via hole 350B.

The n-type conductive layer 350A and the n-type conductive via hole 350B may be formed of one or more of Ag, Al, Au, Pt, Ti, Cr, Since the n-type conductive layer 350A and the n-type conductive via hole 350B are electrically connected to the n-type semiconductor layer 360, the n-type conductive layer 350A and the n- desirable.

The n-type conductive layer 350A may have at least one region in which a part thereof is exposed. It is preferable that the p-type conductive layer 320, the p-type semiconductor layer 330, the active layer 340, and the n-type semiconductor layer 360 are not formed on the exposed region. an n-type electrode pad portion 351 for connecting an external power source to the n-type conductive layer 350A and the n-type conductive via hole 350B may be formed on the exposed region of the n-type conductive layer 350A. As shown in FIG. 3A, the n-type electrode pad portion 351 may be formed at the edge of the light emitting device 300 to maximize the light emitting area.

3B, a p-type conductive layer 320 and an n-type conductive layer 350A may be disposed on the conductive substrate 310. The p-type conductive layer 320 may include an n-type conductive layer 350A, And a part of the n-type conductive via hole 350B may be present on the same layer. a region where the n-type conductive layer 350A and the n-type conductive via hole 350B do not exist in the region of the p-type conductive layer 320 may be in contact with the conductive substrate 310. [ For example, as shown in FIG. 3A, the AA region outside the region of the n-type conductive layer 350A in the region of the p-type conductive layer 320 may be in direct contact with the conductive substrate 310. [

The insulating layer 370 may be disposed such that the n-type conductive layer 350A and the n-type via hole 350B are electrically insulated from the other layers except for the n-type semiconductor layer 360. [ For example, as shown in FIG. 3B, the insulating layer 370 is formed between the n-type conductive layer 350A and the conductive substrate 310, between the n-type conductive layer 350A and the p-type conductive layer 320, and may be formed on the side wall of the n-type via hole 350B. Thus, the insulating layer 370 is formed by stacking the n-type conductive layer 350A and the n-type via hole 350B on the conductive substrate 310, the p-type conductive layer 320, the p- As shown in Fig.

The insulating layer 370 may be formed on the entire sidewall of the n-type via hole 350B and not on the sidewall of the n-type via hole 350B existing in the n-type semiconductor layer 360. In the latter case, the electrical contact area between the n-type via hole 350B and the n-type semiconductor layer 360 can be increased, and the current flow of the light emitting element 300 can be activated.

The insulating layer 370 may be formed of any one or more of silicon oxide (SiO2), silicon nitride (SiOxNy, SixNy), metal oxide (Al2O3), and fluoride compounds.

The active layer 340 exposed to the outside can act as a current leakage path during the operation of the light emitting device 300 and thus the problem can be prevented by forming the passivation layer 380 on the side surface of the light emitting device 300 . The passivation layer 380 protects the light emitting structure, in particular, the active layer 360 from the outside and suppresses the leakage current. The passivation layer 380 is formed of silicon oxide such as SiO2, SiOxNy, SixNy, silicon nitride, and fluoride Compound. ≪ / RTI > Alternatively, it may be a composite layer composed of the aforementioned materials.

[Light Emitting Element 3]

4A is a top view of the light emitting device 400 according to the third embodiment. 4B is a cross-sectional view of the light emitting device 400 taken along the line B-B 'in FIG. 4A. 4C is a diagram illustrating the n-type conductive region 450 of FIG. 4A

4A and 4B, the light emitting device 300 according to the embodiment includes a conductive substrate 410, a first conductive layer 420, a first semiconductor layer 430, an active layer 440, A via hole 460, a via hole 450B, a second conductive line 450A, and an insulating layer 470. In addition, the first electrode pad portion 421 and the second electrode pad portion 451 may be included.

Hereinafter, for convenience of explanation, the first conductive layer 420 is a p-type conductive layer, the first electrode pad portion 421 is a p-type electrode pad portion, the first semiconductor layer 430 is a p- The second semiconductor layer 460 is an n-type semiconductor layer, the via hole 450B is an n-type conductive via hole, the second conductive line 450A is an n-type conductive line, and the second electrode pad portion 451 is n Type electrode pad portion.

The conductive substrate 410 may be formed of one or more of Au, Ni, Al, Cu, W, Si, Se, and GaAs. For example, the conductive substrate 410 may be made of a material in the form of an alloy of Si and Al.

The p-type conductive layer 420 may be disposed on the conductive substrate 410 and electrically connected to the conductive substrate 410. The electrical connection between the p-type conductive layer 420 and the conductive substrate 410 will be described later.

 The P-type conductive layer 420 may be formed of one or more of Ag, Al, Pt, Ni, Pt, Pd, Au, Ir and a transparent conductive oxide (ITO, GZO). Since the p-type conductive layer 420 is in electrical contact with the p-type semiconductor layer 430, the contact resistance of the p-type semiconductor layer 430 is minimized and the light generated in the active layer 440 So as to enhance the luminous efficiency.

The p-type electrode pad portion 421 may be electrically connected to the lower portion of the conductive substrate 421. For example, the p-type electrode pad portion 421 may be bonded to the lower surface of the conductive substrate 421. Or may be omitted.

The p-type semiconductor layer 430 may be disposed on the p-type conductive layer 420. The p-type semiconductor layer 350 is a semiconductor material having a composition formula of InxAlyGa (1-xy) N (0? x? 1, 0? y? 1, 0? x + y? 1), for example, InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN and the like, and a p-type dopant such as Mg or Zn may be doped.

The active layer 440 may be formed of a semiconductor material having a composition formula of InxAlyGa (1-x-y) N (0? X? 1, 0? Y? 1, 0? X + y? When the active layer 440 is formed of a multiple quantum well structure (MQW), the active layer 440 may be formed by stacking a plurality of well layers and a plurality of barrier layers. For example, the InGaN well layer / GaN barrier layer / RTI >

The active layer 440 may be formed by selecting a different material depending on the material of the n-type semiconductor layer 460 and the p-type semiconductor layer 350. That is, the active layer 460 is a layer that converts electrons provided from the n-type semiconductor layer 460 and energy resulting from recombination of the p-type semiconductor layer 430 into light and emits the light. Accordingly, the active layer 440 is preferably formed of a material having an energy band gap smaller than the energy band gap of the n-type semiconductor layer 440 and the p-type semiconductor layer 430.

The n-type semiconductor layer 460 may be disposed on the active layer 440. The n-type semiconductor layer 460 is a semiconductor material having a composition formula of InxAlyGa (1-xy) N (0? x? 1, 0? y? 1, 0? x + y? 1), for example, InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN and the like, and an n-type dopant such as Si, Ge, or Sn can be doped.

The n-type conductive line 450A may be disposed on the conductive substrate 410. [ A plurality of n-type conductive via holes 450B electrically connected to each other by the n-type conductive line 450A may be formed on the n-type conductive line 450A. Here, the n-type conductive line 450A may be formed in a line type connecting the plurality of n-type conductive via holes 450B. For example, as shown in FIG. 4A, the n-type conductive line 450A may be in the form of a matrix, and the n-type conductive via hole 450B may be disposed on the intersection. However, the present invention is not limited to this embodiment, but may be a line type in which a plurality of n-type conductive via holes 450B are electrically connected.

The n-type conductive via hole 450B may be disposed on the n-type conductive line 450A and may be divided into a through region and a protruding region. Here, the through region means a region passing from the n-type conductive line 450A through the p-type conductive layer 420, the p-type semiconductor layer 430, and the active layer 440. The protruding region extends from the through region to the n- The layer 460 may be a region protruding to a certain region. The upper portion of the protruding region may be electrically connected to the n-type semiconductor layer 460. The upper portion of the protruding region may mean the upper surface of the protruding region, and may include the upper surface and the side surface. Accordingly, the n-type conductive line 450A can be electrically connected to the n-type semiconductor layer 460 through the n-type conductive via hole 450B.

The n-type conductive line 450A and the n-type conductive via hole 450B may be formed of one or more of Ag, Al, Au, Pt, Ti, Cr, Since the n-type conductive line 450A and the n-type conductive via hole 450B are electrically connected to the n-type semiconductor layer 460, the n-type conductive layer 450A and the n- desirable.

The n-type conductive line 450A may include at least one region in which a part of the n-type conductive line 450A is exposed. It is preferable that the p-type conductive layer 420, the p-type semiconductor layer 430, the active layer 440 and the n-type semiconductor layer 460 are not formed on the exposed region. an n-type electrode pad portion 451 for connecting an external power source to the n-type conductive line 350A and the n-type conductive via hole 350B may be formed on the exposed region of the n-type conductive line 450A. As shown in FIG. 4A, the n-type electrode pad portion 451 may be formed at the edge of the light emitting device 300 to maximize the light emitting area.

4A, a p-type conductive layer 420 and an n-type conductive line 450A may be disposed on the conductive substrate 410. The p-type conductive layer 420 may include an n-type conductive line 450A, And a part of the n-type conductive via hole 450B may be present on the same layer. a region where the n-type conductive line 450A and the n-type conductive via hole 450B do not exist in the region of the p-type conductive layer 420 may be in contact with the conductive substrate 410. [ For example, as shown in FIG. 4A, the regions BB1 and BB2 in which the n-type conductive line 450A and the n-type conductive via hole 450B are not present in the region of the p-type conductive layer 420 are electrically connected to the conductive substrate 410 ). ≪ / RTI > Here, the BB1 region and the BB2 region may be regions in which the n-type conductive line 450A and the n-type conductive via hole 450B do not exist on the vertical line in the p-type conductive layer 420 region.

The p-type conductive layer 450A increases the contact area with the conductive substrate 410 more than the p-type conductive layer 350A of the second embodiment depending on the type of the n-type conductive line 450A, .

The insulating layer 470 may be disposed such that the n-type conductive line 450A and the n-type via hole 450B are electrically insulated from the other layers except the n-type semiconductor layer 460. [ For example, as shown in FIG. 4B, the insulating layer 470 is formed between the n-type conductive line 450A and the conductive substrate 410, between the n-type conductive line 450A and the p-type conductive layer 420, and may be formed on the side wall of the n-type via hole 450B. Thus, the insulating layer 470 is formed by stacking the n-type conductive line 450A and the n-type via hole 450B on the conductive substrate 410, the p-type conductive layer 420, the p-type conductive layer 420, As shown in Fig.

The insulating layer 470 may be formed in the entire region of the side wall of the n-type via hole 450B and not on the side wall of the n-type via hole 450B existing in the n-type semiconductor layer 460. In the latter case, the electrical contact area between the n-type via hole 450B and the n-type semiconductor layer 460 can be increased, and the current flow of the light emitting element 300 can be activated.

The insulating layer 470 may be formed of any one or more of silicon oxide (SiO2), silicon nitride (SiOxNy, SixNy), metal oxide (Al2O3), and fluoride compounds.

The active layer 440 exposed to the outside may act as a current leakage path during operation of the light emitting device 300 and thus the passivation layer 480 may be formed on the side surface of the light emitting device 300 to prevent such a problem . The passivation layer 480 serves to protect the light emitting structure, in particular, the active layer 460 from the outside and suppress the leakage current. The passivation layer 480 may be formed of silicon oxide such as SiO2, SiOxNy or SixNy, silicon nitride, or a fluoride- Compound. ≪ / RTI > Alternatively, it may be a composite layer composed of the aforementioned materials.

According to the embodiment, the n-type conductive layer is connected to the external electrode pad and the p-type conductive layer (or the p-type conductive line) having high electrode resistance is electrically connected to the conductive substrate having good conductivity, And the heat flow characteristics inside the device can be improved.

Further, since the conductive substrate and the p-type conductive layer (or the p-type conductive line) are connected, the p-electrode pad portion can be omitted. Accordingly, it is possible to omit the process of depositing the bonding pads (Au series) in addition to the p-type electrode pads (Ag series) due to the bonding pads of the p-type electrode pad portions.

In addition, since adhesion of the p-type conductive metal (Ag, Au series) is poor in the prior art, a step of further depositing an adhesive layer must be involved, but such a step may be omitted.

[Light Emitting Element Package]

Hereinafter, a light emitting device package according to an embodiment will be described with reference to FIG.

5 is a cross-sectional view schematically showing a package 1000 of a light emitting element.

5, a light emitting device package 1000 according to an embodiment includes a package body 1100, a first electrode layer 1110, a second electrode layer 1120, a light emitting device 1200, and a filler material 1300 .

The package body 1100 may be formed of a silicon material, a synthetic resin material, or a metal material, and an inclined surface may be formed around the light emitting device 1200 to increase light extraction efficiency.

The first electrode layer 1110 and the second electrode layer 1120 are installed in the package body 1100. The first electrode layer 1100 and the second electrode layer 1120 are electrically isolated from each other and provide power to the light emitting device 1200. The first electrode layer 1110 and the second electrode layer 1120 may reflect the light generated from the light emitting device 1200 to increase the light efficiency and may be configured to discharge heat generated in the light emitting device 1200 to the outside It can also play a role.

The light emitting device 1200 is electrically connected to the first electrode layer 1100 and the second electrode layer 1120. The light emitting device 1200 may be mounted on the package body 1100 or on the first electrode layer 1100 or the second electrode layer 1120.

The light emitting device 1200 may be electrically connected to the first electrode layer 1110 and the second electrode layer 1120 by a wire, a flip chip, or a die bonding method.

The filler 1300 may be formed to surround and protect the light emitting device 1200. The filler 1300 may include a phosphor 1310 to change the wavelength of the light emitted from the light emitting device 1200.

The light emitting device package 1000 can be mounted with one or more than one of the light emitting devices of the above-described embodiments, but the present invention is not limited thereto.

A light guide plate, a prism sheet, a diffusion sheet, and the like, which are optical members, may be disposed on the light path of the light emitting device package 1000. The light emitting device package 1000, the substrate, and the optical member can function as a light unit.

Still another embodiment may be implemented as a display device, an indicating device, a lighting system including the semiconductor light emitting device or the light emitting device package described in the above embodiments, for example, the lighting system may include a lamp, a streetlight .

It will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

Therefore, it should be understood that the above-described embodiments are illustrative and non-restrictive in all aspects, and that the scope of the present invention is defined by the appended claims rather than the foregoing description, And all changes or modifications derived from equivalents thereof should be construed as being included within the scope of the present invention.

300, 400: Light emitting element
310, 410: conductive substrate
320, 420: first conductive layer
330, 430: a first semiconductor layer
340, 440: an active layer
350A: second conductive layer
450A: second conductive line
350B and 450B:
360, 460: a second semiconductor layer
370: insulating layer

Claims (20)

delete delete delete delete delete delete delete delete delete delete A conductive substrate;
A first conductive layer disposed on the conductive substrate and electrically connected to the conductive substrate;
A first semiconductor layer disposed on the first conductive layer;
An active layer disposed on the first semiconductor layer;
A second semiconductor layer disposed on the active layer;
At least one via hole extending through the first conductive layer, the first semiconductor layer, and the active layer from the conductive substrate to a predetermined region of the second semiconductor layer;
A second conductive line disposed on the conductive substrate and electrically connecting the via holes; And
An insulating layer disposed between the conductive substrate and the second conductive line, between the first conductive layer and the second conductive line, and on a side wall of the via hole,
Wherein the insulating layer is not disposed on a side wall of the via hole existing in the second semiconductor layer.
12. The method of claim 11,
And a first electrode pad portion electrically connected to the lower portion of the conductive substrate.
12. The method of claim 11,
Wherein the second conductive line has at least one region in which a part thereof is exposed,
And a second electrode pad portion electrically connected to the exposed region of the second conductive line.
12. The method of claim 11,
And a passivation layer disposed on a sidewall of the first semiconductor layer, the active layer, and the second semiconductor layer to suppress a leakage current of the active layer.
15. The method of claim 14,
Wherein the insulating layer and the passivation layer each comprise any one of silicon oxide, silicon nitride, and fluoride.
12. The method of claim 11,
Wherein the conductive substrate comprises at least one of Au, Ni, Al, Cu, W, Si, Se, and GaAs.
12. The method of claim 11,
Wherein the first conductive layer reflects light generated from the active layer.
12. The method of claim 11,
Wherein the first conductive layer comprises at least one of Ag, Al, Pt, Ni, Pt, Pd, Au, Ir, and a transparent conductive oxide,
Wherein the transparent conductive oxide comprises one of ITO and GZO.
12. The method of claim 11,
Wherein the second conductive line comprises at least one of Ag, Al, Au, Pt, Ti, Cr, and W.
12. The method of claim 11,
The first conductive layer is a p-type conductive layer,
The first semiconductor layer is a p-type semiconductor layer,
The second conductive line is an n-type conductive line,
The second semiconductor layer is an n-type semiconductor layer,
Wherein the via hole is an n-type via hole.

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