KR101666709B1 - All digital semi-blind oversampling clock data recovery circuitry and method therein - Google Patents

Abstract

There is provided an apparatus for restoring a semi-blind oversampled clock data comprising a blind oversampling part and a digital phase locked loop in accordance with embodiments of the present invention, the digital phase locked loop including a digital controlled oscillator and a digital filter part, In a fixed phase, a coarse oscillation fixed signal is generated when a coarse oscillation signal generated by a digital controlled oscillator is synchronized with a reference clock, and a digital controlled oscillator generates a coarse oscillation fixed signal by performing a plurality of oversampling And the digital control oscillator generates the oversampling clock signal in accordance with the fine phase control signal generated by the digital filter section based on the FIFO usage amount information about the speed at which the extracted data is stored in the first-in first-out (FIFO) register in the blind- To control the phase and frequency of Can operate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for restoring all-digital clock data in a semi-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock data restoration technique, and more particularly, to a clock data restoration technique using a semi-blind oversampling method.

The clock data recovery (CDR) technique is a technique of extracting a clock synchronization point from a received serial data stream and sampling the received data stream with a clock signal generated at the extracted clock synchronization point to reconstruct the data.

Typically, the transmission of signals between the transmitter and the receiver is difficult to precisely synchronize, and attempting to synchronize is not only uneconomical, but necessarily synchronized. Since timing information of data transmitted in the serial bit stream generated by the transmission side is included, timing information can be stably extracted by tracking the timing of switching the serial bit stream.

If the clock signal is generated as the extracted timing information and the received data stream is sampled, the data on the bit stream at the transmitting end can be accurately restored at the receiving end.

There are two main types of clock data restoration techniques. One is a blind-oversampling method that uses a reference clock on the receiving side, and the other is a method that does not use another reference clock. tracking method.

The blind oversampling scheme downsamples after oversampling and stores the downsampled candidates in first in first out (FIFO) and then determines the correct phase and data. There is no PLL, which is simpler and has the advantage of reducing the area and power consumption, but it is limited to the reference clock frequency and there is a burden of oversampling.

In contrast, the phase tracking method can extract the clock and data simultaneously by tracking the phase of the bit stream using the PLL without depending on the reference clock. There is a problem that the PLL is very flexible with respect to the frequency of the received bit stream but occupies a large area and power consumption.
[Prior Art Literature]
Korean Registered Patent No. 10-0985974 (Registered Date: September 30, 2010)

SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus and a method for restoring semblanged oversampling clock data.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus and method for recovering a semi-blind oversampled clock data that can solve the problem of the area and power consumption of an analog phase locked loop by digitally processing the phase tracking function.

The solution to the problem of the present invention is not limited to those mentioned above, and other solutions not mentioned can be clearly understood by those skilled in the art from the following description.

An apparatus for restoring a semblanged oversampled clock data comprising a blind oversampling part and a digital phase locked loop in accordance with an aspect of the present invention,

The digital phase locked loop includes a digital controlled oscillator and a digital filter section,

A coarse oscillation fixed signal is generated when a coarse oscillation signal generated in the digital controlled oscillator is synchronized with a reference clock in a coarse phase fixing step,

In the fine phase tracking step, the digitally controlled oscillator provides a plurality of oversampling clocks to the blind-over sampling part, and FIFO usage information about the speed at which extracted data is stored in a first-in first-out (FIFO) register in the blind- The digital controlled oscillator may be operable to control the phase and frequency of the oversampling clock according to the fine phase control signal generated by the digital filter unit.

According to one embodiment, the digital phase lock loop further comprises a digital frequency detector,

The digital frequency detector receives a coarse oscillation signal from the digitally controlled oscillator and generates an n-bit coarse oscillation control signal based on a phase difference between the reference clock and the coarse oscillation signal. A coarse oscillation control signal is applied to the digital controlled oscillator and the coarse oscillation signal is synchronized with the reference clock so that a coarse oscillation fixed signal is supplied to the FIFO of the blind oversampling part. To the register unit.

There is provided a clock data restoration method using a semblanged oversampling clock data restoration apparatus including a blind oversampling part and a digital phase locked loop according to another aspect of the present invention,

The digital phase locked loop includes a digital controlled oscillator and a digital filter section,

Generating a coarse oscillation fixed signal when the oscillation signal is synchronized with a reference clock, oscillating the digitally controlled oscillator according to an n-bit coarse oscillation control signal, and generating a coarse oscillation fixed signal when the oscillated coarse oscillation signal is synchronized with a reference clock;

The blind-over-sampling part over-samples an input bit stream based on a plurality of over-sampling clocks generated by the digitally controlled oscillator, detects an edge, extracts data from oversampled samples based on the detected edge Storing in a FIFO register; And

And configuring the digitally controlled oscillator according to the m-bit micro-oscillation control signal generated based on the rate at which the digital filter unit stores data in the FIFO register.

According to one embodiment, the digital phase lock loop further comprises a digital frequency detector,

The clock data recovery method includes:

The digital frequency detector receiving a coarse oscillation signal from the digital controlled oscillator;

Generating an n-bit coarse oscillation control signal based on a phase difference between the reference clock and the coarse oscillation signal;

A coarse oscillation control signal is applied to the digitally controlled oscillator and the coarse oscillation signal is synchronized to the reference clock so that the coarse oscillation fixed signal is supplied to the FIFO register unit of the blind- And the like.

According to the apparatus and method for recovering semblanged oversampling clock data of the present invention, the area and power consumption problem of the analog phase locked loop can be solved by digitally processing the phase tracking function.

According to the apparatus and method for recovering the semblanged oversampling clock data of the present invention, since it has a clock phase tracking function that is not in the blind oversampling method, it can operate more precisely than the blind oversampling method.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a conceptual diagram illustrating an apparatus for recovering a semblanged oversampled clock data according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating a method of recovering a semblanged oversampling clock data according to an embodiment of the present invention. Referring to FIG.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a conceptual diagram illustrating an apparatus for recovering a semblanged oversampled clock data according to an embodiment of the present invention.

Referring to FIG. 1, since the apparatus for restoring semisynchronous oversampled clock data 10 basically uses a blind oversampling technique, the basic principle from the input of a bitstream to the final output of data is a conventional blind oversampling technique Can be referenced.

The blind oversampling scheme utilizes the reference clock signal inside the receiver without tracking the embedded clock information in the received bitstream. Instead, this scheme over-samples the received bit stream to recover the data in the received bit stream by detecting the samples where a transition occurs, i. E., An edge, among the samples.

On the other hand, the semi-blind oversampling clock data restoration apparatus 10 may use a digital phase locked loop (PLL) to restore the clock and provide an oversampling phase, instead of using the receiver reference clock signal.

Specifically, the semi- blind oversampling clock data restoration apparatus 10 may include a blind oversampling part 11 and a digital phase lock loop 12.

The blind oversampling part 11 receives the bit stream, and uses an oversampling part 111 using a plurality of oversampling clocks provided from the digital phase locked loop 12, a synchronization part 11 for adjusting the synchronization of the oversampled samples, A downsampling unit 114 for downsampling the oversampled samples based on the detected samples of the edges to extract data, and a downsampling unit 114 for sampling the oversampled samples, After the coarse oscillation fixed signal COARSE_LOCK is applied in the digital phase locked loop 12, the data extracted from the downsampling unit 114 is stored and the stored data is output, and data is firstly input A FIFO register unit 115 for providing FIFO usage information (FIFO Utilization) concerning the speed input to the first out register to the digital phase locked loop 12, And a comma detector 116 for detecting a predetermined word pattern and determining the start of the actual data.

The digital phase locked loop 12 may include a digitally controlled oscillator 121, a digital frequency detector 122 and a digital filter unit 123 and operates with a two phase phase locking step.

The digital controlled oscillator 121 roughly changes the oscillation frequency according to a coarse oscillation control signal OSC_C input from the digital frequency detector 122 and outputs a micro oscillation The oscillation frequency can be finely adjusted according to the control signal OSC_F.

For this purpose, the digitally controlled oscillator 121 may be embodied as a ring oscillator in which, for example, a plurality of delay cells are feed forward connected. For example, in each of the delay cells, the magnitude of the bias current is determined, for example, by the coarse oscillation control signal OSC_C in a binary manner, and the capacitor is determined in a binary manner by the fine oscillation control signal OSC_F, The delay time of each delay cell can be adjusted. By using these delay cells, the oscillation frequency can be changed to be changed.

On the other hand, the digital phase locked loop 12 operates with a phase locking step of two phases consisting of a coarse phase fixing step and a fine phase tracking step.

First, the digital controlled oscillator 121 outputs the oversampling control signal OSC_C according to the n-bit coarse oscillation control signal OSC_C input from the digital frequency detecting unit 122 before providing the oversampling clocks to the oversampling unit 111. [ and applies a coarse oscillation signal V_OSC oscillating at a coarse oscillation frequency to the digital frequency detector 122. [

The digital frequency detector 122 receives a coarse oscillation signal from the digitally controlled oscillator 121 and compares the phase with a reference clock to adjust an n-bit coarse oscillation control signal OSC_C according to the phase difference. And transmits a coarse oscillation fixed signal (COARSE_LOCK) signal to the FIFO register unit 115 of the blind oversampling part 11 when the coarse oscillation signal is settled by being synchronized with the reference clock.

In response to the generation of the coarse oscillation lock signal COARSE_LOCK, the digitally controlled oscillator 121 generates the oversampling clocks and provides them to the oversampling unit 111.

With this coarse oscillation locked signal (COARSE_LOCK) and the provision of the oversampling clocks, the blind oversampling part 11 starts the data restoration operation, and the digital frequency detection part 122 stops the operation.

The digital filter unit 123 continuously receives and filters the FIFO usage amount information from the FIFO register unit 115 of the blind-over sampling unit 11 to generate an m-bit micro oscillation control signal OSC_F, Bit fine oscillation control signal OSC_F to the digitally controlled oscillator 121. [

If the FIFO usage information indicates that the amount of FIFO register unit 115 is being used, it is necessary to advance the frequency and phase of the input bitstream so as to advance the phase of the oversampling clocks, that is, the phase of the oscillation signal of the digitally controlled oscillator 121 . On the contrary, if the FIFO usage amount information indicates that the amount of usage of the FIFO register unit 115 is lowered, it means that the frequency and phase of the input bit stream become slow and the phase of the oversampling clocks, that is, the phase of the oscillation signal of the digitally controlled oscillator 121 It is necessary to slow down.

In accordance with the FIFO usage amount information, the digital filter unit 123 generates the m-bit micro oscillation control signal OSC_F based on the FIFO usage amount information, and outputs the generated m-bit micro oscillation control signal OSC_F to the digital control Oscillator 121, thereby realizing an all digital phase locked loop (ADPLL).

FIG. 2 is a flowchart illustrating a method of recovering a semblanged oversampling clock data according to an embodiment of the present invention. Referring to FIG.

2, in the step S21, the method of restoring the semblanged oversampled clock data includes oscillating the digitally controlled oscillator 121 in accordance with an n-bit coarse oscillation control signal OSC_C, coarse oscillation signal (COARSE_LOCK) when the oscillation signal is synchronized with the reference clock.

In step S22, the blind oversampling part 11 oversamples the input bit stream based on the plurality of oversampling clocks generated in the digitally controlled oscillator 121, detects an edge, and based on the detected edge The data is extracted from the oversampled samples and stored in the FIFO register.

In step S23, the digital filter unit 123 oscillates the digitally controlled oscillator 121 in accordance with the m-bit micro oscillation control signal OSC_F generated based on the rate at which data is stored in the FIFO register.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. It will be understood that variations and specific embodiments which may occur to those skilled in the art are included within the scope of the present invention.

10 Semi-blind oversampling clock data recovery device
11 blind oversampling parts
111 oversampling unit
112 synchronization section
113 edge detector
114 downsampling unit
115 FIFO register section
116 comma detector
12 digital phase locked loops
121 digitally controlled oscillator
122 digital frequency detector
123 digital filter section

Claims (4)

CLAIMS: 1. An apparatus for restoring semi- blind, oversampled clock data comprising a blind oversampling part and a digital phase locked loop,
The digital phase locked loop includes a digital controlled oscillator and a digital filter section,
A coarse oscillation fixed signal is generated when a coarse oscillation signal generated in the digital controlled oscillator is synchronized with a reference clock in a coarse phase fixing step,
In the fine phase tracking step, the digitally controlled oscillator provides a plurality of oversampling clocks to the blind-over-sampling part, and FIFO usage information on the speed at which the extracted data is stored in a first-in first- Wherein the digital controlled oscillator controls the phase and frequency of the oversampling clock according to the fine phase control signal generated by the digital filter unit,
The blind-over-sampling portion includes an oversampling portion for receiving a bitstream, using a plurality of oversampling clocks provided from a digital phase-locked loop, an edge detector for detecting samples where a transition occurs in oversampled samples, A downsampling unit for sampling the oversampled samples on the basis of the samples to extract data, a method for storing data extracted from the downsampling unit after a coarse oscillation fixed signal (COARSE_LOCK) is applied in a digital phase locked loop And a FIFO register unit for outputting the stored data and providing FIFO usage information (FIFO Utilization) regarding the speed at which data is input to the FIFO (First In First Out) register to the digital phase locked loop. An oversampling clock data recovery device. The digital phase locked loop of claim 1, further comprising a digital frequency detector,
The digital frequency detector receives a coarse oscillation signal from the digitally controlled oscillator and generates an n-bit coarse oscillation control signal based on a phase difference between the reference clock and the coarse oscillation signal. A coarse oscillation control signal is applied to the digital controlled oscillator and the coarse oscillation signal is synchronized with the reference clock so that a coarse oscillation fixed signal is supplied to the FIFO of the blind oversampling part. To the register unit. ≪ RTI ID = 0.0 > 31. < / RTI > CLAIMS 1. A method for recovering clock data using a semi- blind oversampling clock data recovery apparatus comprising a blind oversampling part and a digital phase locked loop,
The digital phase locked loop includes a digital controlled oscillator and a digital filter section,
Generating a coarse oscillation fixed signal when the oscillation signal is synchronized with a reference clock, oscillating the digitally controlled oscillator according to an n-bit coarse oscillation control signal, and generating a coarse oscillation fixed signal when the oscillated coarse oscillation signal is synchronized with a reference clock;
The blind-over-sampling part over-samples an input bit stream based on a plurality of over-sampling clocks generated by the digitally controlled oscillator, detects an edge, extracts data from oversampled samples based on the detected edge Storing in a FIFO register; And
And setting the digitally controlled oscillator according to the m-bit micro-oscillation control signal generated based on the rate at which the digital filter unit stores data in the FIFO register,
The blind-over-sampling portion includes an oversampling portion for receiving a bitstream, using a plurality of oversampling clocks provided from a digital phase-locked loop, an edge detector for detecting samples where a transition occurs in oversampled samples, A downsampling unit for sampling the oversampled samples on the basis of the samples to extract data, a method for storing data extracted from the downsampling unit after a coarse oscillation fixed signal (COARSE_LOCK) is applied in a digital phase locked loop And a FIFO register unit for outputting the stored data and providing FIFO usage information (FIFO Utilization) regarding the speed at which data is input to the FIFO (First In First Out) register to the digital phase locked loop. Clock using oversampling clock data recovery device Site restoration methods. 4. The digital phase lock loop of claim 3, wherein the digital phase lock loop further comprises a digital frequency detector,
The clock data recovery method includes:
The digital frequency detector receiving a coarse oscillation signal from the digital controlled oscillator;
Generating an n-bit coarse oscillation control signal based on a phase difference between the reference clock and the coarse oscillation signal;
A coarse oscillation control signal is applied to the digitally controlled oscillator and the coarse oscillation signal is synchronized with the reference clock to generate a coarse oscillation fixed signal signal in the FIFO register unit of the blind- The method of claim 1, wherein the clock data is clocked by a clock signal.

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