KR101539438B1 - Apparatus of generating a transmission clock in a sink and method of transmitting by using the transmission clock - Google Patents

Abstract

The present invention relates to a semiconductor device, and more particularly, to a device for generating a transmission clock without a reference clock in a sink and a method for transmitting data from a sink to a source using the generated transmission clock. A transmitting clock generating apparatus includes a digital phase detector for detecting a phase difference between a received clock of a data signal received from a source and a recovered clock, a receiver disposed in the receiver, the phase detector using a phase difference detected by the digital phase detector A first digital control oscillator located at a receiver for generating a digitally controlled oscillator code and outputting the recovered clock using the digitally controlled oscillator code; A second digital control oscillator for outputting a transmission clock; a serializer for serializing return data using the transmission clock, the serializer being located in a transmitter, comparing the received clock with the recovered clock, A locking detection signal indicating whether or not If the lock detector, and wherein the locking detection signal, the output settings include a transmit clock for providing said digital control oscillator code to said second digital control oscillator.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a transmission clock generating apparatus and a transmission method using the generated transmission clock,

The present invention relates to a semiconductor device, and more particularly, to a device for generating a transmission clock without a reference clock in a sink and a method for transmitting data from a sink to a source using the generated transmission clock.

As the data transfer speed increases, the source transmits the clock and data together, and the sink restores the clock. In such a high-speed communication method, the CDR (Clock Data Recovery) of the sink performs a function of restoring the clock and arranging the phase of the restored clock. Sources and sinks communicate over one or more unidirectional channels that can transmit synchronous data at high speed from the source. Some communication schemes include unidirectional channels that transmit data from sink to source, or bidirectional channels between source and sink. However, the bidirectional channel transmits data at a relatively low speed as compared with the unidirectional channel. In addition, a configuration for separately generating a transmission clock for bi-directional data transmission must be included in each of the source and the sink. Generally, the source is provided with a reference clock, but often it is not clear whether a reference clock is provided to the sink. For this reason, when designing a sink, it is necessary to design for a case where there is no reference clock. Also, if the number of channels increases, it becomes difficult to efficiently arrange a large number of channels.

U.S. Patent No. 7,263,153 U.S. Patent No. 7,839,965

So that a unidirectional channel can be utilized as a bidirectional channel. If data transmission from the sink to the source is required, the unidirectional channel can be used as a bi-directional channel to transmit data. In this case, the transmission clock can be secured without introducing a complicated configuration into the sink.

Simplify transmission method between sink and source when unidirectional channel is used as bidirectional channel. When the data is transmitted from the sink to the source, the clock recovery process is omitted and the data transmission and reception can be performed only by phase matching.

A transmitting clock generating apparatus includes a digital phase detector for detecting a phase difference between a received clock of a data signal received from a source and a recovered clock, a receiver disposed in the receiver, the phase detector using a phase difference detected by the digital phase detector A first digital control oscillator located at a receiver for generating a digitally controlled oscillator code and outputting the recovered clock using the digitally controlled oscillator code; A second digital control oscillator for outputting a transmission clock; a serializer for serializing return data using the transmission clock, the serializer being located in a transmitter, comparing the received clock with the recovered clock, A locking detection signal indicating whether or not If the lock detector, and wherein the locking detection signal, the output settings include a transmit clock for providing said digital control oscillator code to said second digital control oscillator.

Here, the transmission clock setter may provide a digital control oscillator code corresponding to the locking detection signal to the second digital control oscillator when the locking detection signal is output and the receiver stops operating.

Here, the return data may be transmitted in the blank interval before the start of transmission of the next data signal after the end of the transmission of the currently received data signal. The blank interval may be initiated by the source end transmitted by the source. Meanwhile, the blank interval may be terminated by the sink end transmitted by the sink.

Here, the return data may include a mini training pattern. The mini training pattern may be a training pattern aligned with at least one rising edge of the transmission clock or a training pattern aligned with at least one falling edge of the transmission clock.

The return data may further include locking data indicating a locking state of the sink.

Here, the digital phase detector may output a phase difference to adjust the phase of the recovered clock using the mini training pattern received from the source after transmitting the return data.

A transmitting clock generating apparatus includes a digital phase detector for detecting a phase difference between a received clock of a data signal received from a source and a recovered clock, a receiver disposed in the receiver, the phase detector using a phase difference detected by the digital phase detector A first digital control oscillator located at a receiver for generating a digitally controlled oscillator code and outputting the recovered clock using the digitally controlled oscillator code; A second digital control oscillator for outputting a transmission clock, a serializer located in the transmitter for serializing return data using the transmission clock, a latch for indicating whether the first digital control oscillator is locked using the detected phase difference, A lock detector for outputting a detection signal And a transmission clock configurer for providing the digital control oscillator code to the second digital control oscillator when the locking detection signal is output.

A method of transmitting data between a source and a sink using a reference clock, the method comprising the steps of: generating a transmission clock with a source clock and a reference clock, The digital control oscillator outputs a transmission clock and changes the data transmission direction between the source and the sink so that return data is transmitted to the source in the blank interval before transmission of the next data signal after transmission of the data signal currently received from the source .

Wherein the step of outputting a transmission clock by a digital control oscillator included in a transmitter of the sink using a reception clock of the data signal received from the source comprises the steps of receiving the reception clock of the data signal received from the source, Generating a digitally controlled oscillator code by using a phase difference between the received clock and the recovered clock, and outputting the recovered clock by a digital control oscillator included in a receiver of the sink using the digitally controlled oscillator code, Determining whether the digital control oscillator included in the receiver of the sink is locked; if the digital control oscillator included in the receiver of the sink is locked, Provide an oscillator It may contain.

Here, the blank interval may be started by the source end transmitted by the source.

Here, the return data may include a mini training pattern. The mini training pattern may be a training pattern aligned with at least one rising edge of the transmission clock or a training pattern aligned with at least one falling edge of the transmission clock. The return data may further include locking data indicating a locking state of the sink. Meanwhile, the blank interval may be terminated by the sink end transmitted by the sink.

The method may further include adjusting a phase of the recovered clock using the mini training pattern received from the source after the return data transmission.

A sink that generates a transmission clock without a reference clock and transmits the data generates a digitally controlled oscillator code using the phase difference between the received clock of the data signal received from the source and the recovered clock and restores it by the generated digitally controlled oscillator code A receiver for recovering data from the data signal using the recovered clock and a digitally controlled oscillator code for locking the recovered clock to the received clock, and generating a transmission clock using the transmission clock, Lt; RTI ID = 0.0 > source. ≪ / RTI >

The receiver includes a digital phase detector for detecting a phase difference between a received clock of the data signal received from the source and the recovered clock, a time-digital converter for generating a digitally controlled oscillator code using the phase difference detected by the digital phase detector, And a first digital controlled oscillator outputting the recovered clock using the digital controlled oscillator code.

Here, the transmitter may include a second digital control oscillator for outputting a transmission clock using the digital control oscillator code, and a serializer for serializing the return data using the transmission clock.

The apparatus may further include a lock detector that compares the received clock with the recovered clock and outputs a locking detection signal indicating whether the first digital controlled oscillator is locked.

The apparatus may further include a lock detector for outputting a locking detection signal indicating whether the first digital control oscillator is locked using the output of the digital phase detector.

Meanwhile, when the locking detection signal is output, the transmission clock setting unit may provide the digital control oscillator code to the second digital control oscillator.

Here, the transmitter may transmit return data to the source in the blank interval before transmission of the next data signal after the transmission of the data signal currently received from the source is completed.

Here, the data signal received from the source and the return data may be transmitted through the same channel.

The unidirectional channel can be utilized as a bidirectional channel. When data transmission from a sink to a source is required, data can be transmitted using a channel conventionally used only in one direction as a bidirectional channel. In this case, the transmission clock can be secured without introducing a complicated configuration into the sink.

When a unidirectional channel is used as a bidirectional channel, the transmission method between the sink and the source is simplified. Although the sink does not transmit the transmission clock separately, the clock recovery process can be omitted when data is transmitted from the sink to the source, and data can be transmitted and received only by phase matching.

Hereinafter, the present invention will be described with reference to the embodiments shown in the accompanying drawings. For the sake of clarity, throughout the accompanying drawings, like elements have been assigned the same reference numerals. It is to be understood that the present invention is not limited to the embodiments illustrated in the accompanying drawings, but may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.
1 is a diagram exemplarily showing a source and a sink configuration.
2A is a diagram showing a configuration of a sync clock generating apparatus.
2B is a diagram showing another configuration of a sync clock generating apparatus.
2C is a diagram showing another configuration of a sync clock generating apparatus.
FIG. 3 is a diagram for explaining the operation of the clock generating apparatus shown in FIGS. 2A to 2C. Referring to FIG.
4 is a diagram showing still another configuration of a sync clock generating apparatus.
5 is a diagram for explaining the operation of the sync clock generating apparatus shown in FIG.
Figs. 6A and 6B are diagrams illustrating an exemplary configuration of the transmission clock configurator shown in Figs. 2A to 2C and Fig.
7 is a flowchart for explaining a data transfer process between a source and a sink.
8 is a diagram showing the structure of data transmitted between a source and a sink.
9 is a view showing a mini training pattern.

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

1 is a diagram exemplarily showing a source and a sink configuration.

The source and the sink are electrically connected through the channel, and the source transmits the synchro data signal. A source transmits a synchronous data signal at a high speed through one channel, and a sink generates a transmission clock by using a clock recovered from the data signal and transmits return data to the source using the generated clock.

The source and the sink each include a transmitter and a receiver. The receiver of the source and the receiver of the sink are clock and data recovery (CDR) for recovering the clock and data from the data signal, and the sender of the sink generates a transmission clock having substantially the same frequency as the clock recovered by the CDR. The receiver of the source may recover the data and / or the clock from the return data. In the case of the source, since the clock used for transmission of the data signal and the transmission clock are substantially the same, the clock recovery process can be omitted or simplified.

The return data is transmitted from the sink to the source in a blank interval in which the transmission of the data signal from the source is suspended. During the blank interval, the data transmission direction of the channel is changed so that only the sink can transmit data. The blank interval may occur at least once during communication of the data signal between the source and the sink. The blank section may have a specific length depending on the data transmission method. On the other hand, when compared with the period in which the data signal is transmitted, the length of the blank interval is relatively shorter than the interval in which the data signal is transmitted. However, by configuring the size of the return data to be smaller than the blank interval, bi-directional communication can be performed at the same time without affecting the data transmission efficiency between the source and the sink. On the other hand, even if the size of the return data is larger than the blank interval, the return data may be divided and transmitted using the next blank interval, thus not affecting the data transmission efficiency between the source and the sink. In addition, when the size of the return data is larger than the blank interval, the transmission speed of the data can be increased and transmitted.

2A is a diagram showing a configuration of a sync clock generating apparatus.

Referring to FIG. 2A, a sink is composed of a receiver 100 and a transmitter 300, and is electrically connected to a source through a bidirectional interface. The receiver 100 generates a digitally controlled oscillator code using the phase difference between the received clock of the data signal received from the source and the recovered clock, and generates the digital control oscillator code using the recovered clock recovered by the generated digitally controlled oscillator code Restores the data from the signal. The transmitter 300 generates a transmission clock by a digitally controlled oscillator code that locks the recovered clock to the reception clock, and transmits the return data to the source using the transmission clock.

The sync clock generation device includes a digital phase detector 110, a time-to-digital converter 120, a first digital control oscillator 130, a lock detector 140, a transmit clock configurator 200, a second digital control oscillator 310).

The digital phase detector 110 detects the phase difference between the received clock and the recovered clock. And outputs the detected phase difference indicating whether the phase of the recovered clock is later or faster than the received clock by comparing the phase of the received clock of the data signal input through the bidirectional interface with the phase of the recovered clock using the received clock. Here, the data signal may include any one of a main training pattern and a mini training pattern. The digital phase detector 110 may be a non-linear detector, such as, for example, an Alexander phase detector, an Oversampled phase detector, or a Bang-Bang phase detector. Compared to the linear phase detector which compares the phase difference between the input data signal and the recovered clock and generates the up signal pulse UP and the down signal pulse DN having a width proportional to the difference, The information about the size can be ignored and the polarity of the phase error can be output.

The time-to-digital converter 120 is connected to the output of the digital phase detector 110 and converts the detected phase difference into a digitally controlled oscillator code. For example, the detected phase difference can be output in various forms such as UP / DN, Early / late, Error / Ref, etc., and the phase of the recovered clock is fast / slow , And the time-to-digital converter 120 converts the detected phase difference into a digitally controlled oscillator code which is a digital signal of n bits (n is a natural number). Thus, digital control oscillator codes having different values may continue to be output until the first digital control oscillator 130 is locked. When the first digital control oscillator 130 is locked, the time-to-digital converter 120 may output a fixed digital control oscillator code.

The first digital control oscillator 130 is connected to the output of the time-to-digital converter 120 and outputs the clock recovered by the digitally controlled oscillator code. The first digital control oscillator 130 increases or decreases the frequency of the clock in accordance with the n-bit digitally controlled oscillator code. For example, when using a 9-bit digitally controlled oscillator code, the digitally controlled oscillator can output a clock having up to 512 different frequencies.

On the other hand, a digital control oscillator can be designed to have various structures. For example, you can combine a digital-to-analog converter with a voltage-controlled oscillator to form a digitally controlled oscillator, or you can configure a digitally controlled oscillator by directly controlling the output of the oscillator using a digital input as a switch. It is needless to say that a digital control oscillator can be implemented using various methods.

The lock detector 140 is connected to the output terminal of the first digital control oscillator 130 and determines whether the first digital control oscillator 130 is locked. The lock detector 140 compares the received clock with the clock recovered by the first digital control oscillator 130 to output a locking detection signal when locking occurs. For example, if the received clock and the rising edge of the recovered clock are compared and matched, the lock detector 140 may determine that the clock has been locked. As another example, the lock detector 140 may determine whether or not to lock by counting the number of times the phase of the rising edge of the received clock and the rising edge of the recovered clock coincide. It is needless to say that it is possible to judge whether or not to be locked by using various methods.

In FIG. 2A, the lock detector 140 is shown as being located in the receiver 100, but the present invention is not limited thereto. In addition, although the locking detection signal is directly provided from the lock detector 140 to the transmission clock setter 200, this is only an example for the sake of understanding, and the locking detection signal is transmitted to the control circuit (not shown) May be provided alone or together with the control signal.

The deserializer 150 parallelizes the serial data input through the bidirectional interface using the recovered clock. The parallel data is output to the control circuit of the sink. The control circuit of the sink not only processes the parallel data but also controls the operation of the receiver 100, the transmission clock setter 200, and the transmitter 300.

The transmit clock configurator 200 is located between the receiver 100 and the transmitter 300 and provides a digitally controlled oscillator code to the second digital control oscillator 310 located at the transmitter 300. The transmission clock setter 200 may provide a digital control oscillator code to the second digital control oscillator 310 upon receipt of the locking detection signal from the lock detector 140. In order to prevent power loss caused by the transmitter 300 or to prevent noise from occurring in the transmission medium connected to the bidirectional interface, the control circuit of the sink turns off the transmitter 300 during the reception operation, May be turned off. The transmission clock setter 200 may provide a digital controlled oscillator code to the second digital control oscillator 310 by a combination of a locking detection signal and a control signal from the control circuit. An example and operation of the structure of the transmission clock setter 200 will be described with reference to Figs. 6A and 6B.

The second digital control oscillator 310 provides a transmit clock. The second digital control oscillator 310 outputs the transmission clock using a digitally controlled oscillator code corresponding to the locking detection signal. For example, the second digital control oscillator 310 and the first digital control oscillator 130 may have the same structure. Therefore, the second digital control oscillator 310 and the first digital control oscillator 130 can output the same clock by the digital control oscillator code in which the locking detection signal is outputted.

The serializer 320 serializes the data input by the control circuit and outputs the serialized data. The output data is transmitted to the source via the bidirectional interface. The control circuitry of the sink sends a sink end to the source via the serializer 320 indicating the end of the blank interval and the return data including mini training pattern (Mini training) and locking data.

The bidirectional interface 330 controls the data transfer direction between the source and the sink. Directional interface 330 stops transmitting the data signal from the sink to the source and transmits the data signal from the sink when the data signal is received from the source, the bidirectional interface 330 receives the data signal from the source to the sink Stop. The data transmission direction of the bidirectional interface 330 is determined by the control signal of the control circuit. Here, the control circuit allows the bidirectional interface 330 to send return data from the sink to the source by the source end received from the source. In addition, when the transfer of the return data is completed, the control circuit transfers the sink end to the source and the bidirectional interface 330 to receive the data signal from the source.

2B is a diagram showing another configuration of a sync clock generating apparatus.

Referring to FIG. 2B, the sync clock generation apparatus includes a digital phase detector 110, a time-to-digital converter 120, a first digital control oscillator 130, a lock detector 140, a digital filter 160, A setter 200, and a second digital control oscillator 310. Description of the components described in Fig. 2A is omitted.

Compared with FIG. 2A, the sink clock generator shown in FIG. 2B further includes a digital filter 160 located between the time-to-digital converter 120 and the first digital control oscillator 130. The digital filter 160 filters the digitally controlled oscillator code output from the time-to-digital converter 120 in digital mode. The jitter noise characteristic of the clock recovered by the digital filter 160 and the transmission clock can be improved.

2C is a diagram showing another configuration of a sync clock generating apparatus.

Referring to FIG. 2C, the sync clock generation apparatus includes a digital phase detector 110, a time-to-digital converter 120, a first digital control oscillator 130, a lock detector 140, a digital filter 160, A setter 200, and a second digital control oscillator 310. Description of the components described in Fig. 2A is omitted.

The digital phase detector 110 detects the phase difference between the received clock and the recovered clock. The phase difference output by the digital phase detector 110 may be in various forms. For example, the phase difference may be a pulse indicating fast / slow or a pulse indicating Reference / Error. Regardless of the manner in which the phase difference is output, if the digitally controlled oscillator 130 is locked, the detected value remains constant. For example, in the case of outputting as a pulse indicating fast / slow, the fast pulse and the slow pulse may be output at the same time or output as a very short pulse. In addition, the locking state can be expressed in various forms. Therefore, the lock detector 140 can determine whether or not the lock is detected by using the phase difference type output in the locked state.

FIG. 3 is a diagram for explaining the operation of the clock generating apparatus shown in FIGS. 2A to 2C. Referring to FIG.

When the data signal is input through the bidirectional interface 400, the receiver 100 operates the first digital control oscillator 130 so that the recovered clock is locked to the reception clock of the input data signal. When a lock occurs between the received clock and the recovered clock, the lock detector 140 outputs a locking detection signal (420). Thereafter, while the transmitter is in operation, the receiver 100 is turned off by control of the control circuit (430).

In the transmitter 300, an n-bit digitally controlled oscillator code corresponding to the locking detection signal is transmitted (440) to the second digital control oscillator 310 by the transmission clock setter 200. Thereafter, the second digital control oscillator 310 outputs a transmission clock having a fixed frequency by the n-bit digital control oscillator code (450). Transmitter 300 transmits the return data to the source using the transmit clock (460).

In an embodiment, when a locking detection signal is output, the transmitter 300 may be turned on to generate a transmission clock. As another embodiment, even if a locking detection signal is output, the transmitter 300 may be turned on only by control of the control circuit. In another embodiment, even if a locking detection signal is output, the transmitter 300 may be turned on only when the receiver 100 is turned off. In FIG. 2, steps 420 and 440 are shown to be performed at the same time, but they may be performed at different times according to the embodiment. Likewise, steps 430 and 450 are not necessarily performed at the same time.

4 is a diagram showing still another configuration of a sync clock generating apparatus.

4, the sync clock generation apparatus includes a digital phase detector 110, a time-to-digital converter 120, a first digital control oscillator 130, a lock detector 140, a transmission clock configurer 200, A sigma-delta converter 210, and a second digital controlled oscillator 310. [ Descriptions of the components described in Fig. 1A are omitted.

Compared to FIG. 2A, the sync clock generator of FIG. 4 further includes a sigma-delta converter 210 located between the time-to-digital converter 120 and the transmit clock configurator 200. The sigma-delta converter 210 accumulates the digital control oscillator codes output from the time-to-digital converter 120 and outputs an average value. In particular, the sigma-delta converter 210 alters the number of bits of the digitally controlled oscillator code through an error feedback operation using the difference of the two digitally controlled oscillator codes. In this embodiment, the sigma-delta converter 210 may output a digitally controlled oscillator code of K (K is a natural number) bits. The jitter noise characteristic of the clock recovered by the sigma-delta converter 210 and the transmission clock can be improved. Meanwhile, in another embodiment, the sigma-delta converter 210 may be replaced by an accumulator.

5 is a diagram for explaining the operation of the sync clock generating apparatus shown in FIG.

When the data signal is input through the bidirectional interface 400, the receiver 100 operates the first digital control oscillator 130 so that the recovered clock is locked to the reception clock of the input data signal. When a lock occurs between the received clock and the recovered clock, the lock detector 140 outputs a locking detection signal (420). Thereafter, while the transmitter is in operation, the receiver 100 is turned off by control of the control circuit (430).

In the transmitter 300, n bits of digitally controlled oscillator code corresponding to the locking detection signal is passed to the sigma-delta converter 210 (470). In this embodiment, the sigma-delta converter 210 accumulates the n-bit digitally controlled oscillator codes of the n-bit digital values and generates an average value to generate a K-bit digitally controlled oscillator code (475). When the locking detection signal is output, the sigma-delta converter 210 fixes and outputs the K-bit digitally controlled oscillator code (480). Thereafter, the second digital control oscillator 310 outputs a transmission clock having a fixed frequency by the K-bit digital control oscillator code (485). Transmitter 300 transmits the return data to the source using the transmit clock (490).

In one embodiment, driving the sigma-delta converter 210 during a receive operation can reduce the time required to acquire the transmit clock. In another embodiment, when a locking detection signal is output, the sigma-delta converter 210 and the transmitter 300 may be turned on to generate a transmit clock. As another embodiment, even if a locking detection signal is output, the transmitter 300 may be turned on only by control of the control circuit. In another embodiment, even if a locking detection signal is output, the transmitter 300 may be turned on only when the receiver 100 is turned off. In FIG. 5, steps 410 and 470 are shown to be performed at the same point in time, but they may be performed at different points in time according to the embodiment. Similarly, steps 420 and 480 are not necessarily performed at the same time, and steps 430 and 485 are also the same.

Figs. 6A and 6B are diagrams illustrating an exemplary configuration of the transmission clock configurator shown in Figs. 2A to 2C and Fig.

Referring to FIG. 6A, the transmit clock configurer 200 may be implemented using a 2: 1 multiplexer with two inputs. The first input of the multiplexer is connected to a time-to-digital converter 120, a digital filter 160 or a sigma-delta converter 210 to receive a digitally controlled oscillator code. The second input of the multiplexer is coupled to the output of the multiplexer and receives the digitally controlled oscillator code that is output. With this connection structure, a digital controlled oscillator code can be provided to the second digital controlled oscillator 310 even when the receiver 100 is turned off and no digital controlled oscillator code is provided. The control signal provided by the downstream control circuit may act as an enable signal to turn the multiplexer on or off, or it may act to select the input of the multiplexer with the locking detection signal.

In one embodiment, the signal selecting the input of the multiplexer may be a locking detection signal provided from the lock detector 140. The first input terminal can be selected by the locking detection signal. On the other hand, the multiplexer can be configured to basically select the second input terminal if the locking detection signal is not inputted. For this reason, a digital control oscillator code may not be provided to the second digital control oscillator 310 before the locking detection signal is provided. Also, even if the lock detector 140 is included in the receiver 100 and turned off, a digital control oscillator code corresponding to the lock detection signal can be continuously provided to the second digital control oscillator 310. [

In another embodiment, the signal selecting the input of the multiplexer may be a combination of a locking detection signal and a control signal. To this end, a logic circuit (not shown) may be connected to the multiplexer for receiving the locking detection signal and the control signal, performing a logic operation on the locking detection signal, and inputting the logic detection signal and the control signal to the multiplexer. On the other hand, a locking detection signal is provided to the control circuit, and the control circuit can turn on the transmitter 300 after receiving the locking detection signal.

Referring to FIG. 6B, the transmission clock setter 200 may be configured as a latch storing a digitally controlled oscillator code. Even if the receiver 100 is turned off before the operation of providing the transmit clock or before the transmitter 300 is turned on by storing the digitally controlled oscillator code, the digital control oscillator code corresponding to the lock detection signal 2 < / RTI > digital control oscillator 310. [

On the other hand, although the first input of the multiplexer of Fig. 6a is shown connected to the output of the latch, the multiplexer may be omitted or replaced by a simple circuit element such as a switch, for example, by the control circuitry controlling input and output to the latch .

7 is a flowchart for explaining an example of a data transfer process between a source and a sink. In FIG. 7, the timing controller and the data driver of the display are expressed as a source and a sink, respectively, but this is merely an example, and the present invention is not limited thereto.

In steps 600 and 605, power is supplied and internal power is supplied to the timing controller and the data driver, respectively.

In steps 610 and 615, when internal power is supplied, the start-up circuit for starting the timing controller and the data driver is driven. The timing controller and the data driver are internally reset and initialized by the start-up circuit.

In step 620, the initialized data driver waits for a data signal from the timing controller.

At step 625, the main training generation block generates a main training pattern required for the data driver to recover the clock and data in the data signal. The main training pattern is the training pattern that the data driver needs to restore the clock.

In step 630, the timing controller transmits the main training pattern generated in the main training generating block to the data driver. The main training pattern is transmitted over the connected channel between the timing controller and the data driver. Here, if either the timing controller or the data driver is transmitting a data signal, the other party can not transmit the data signal. The data transfer direction between the source and the sink can be controlled by the bidirectional interface 330. That is, the bidirectional interface 330 may prevent the return data output from the transmitter 300 from being transmitted to the timing controller while the timing controller is transmitting the data signal.

In step 635, upon receiving the main training pattern from the timing controller, the data driver performs main training and restores the clock and prepares for transmission. Using the main training pattern, the data driver recovers the received clock of the received data signal. When the receive clock is recovered, the second digital control oscillator 310 of the transmitter 300 can generate the same transmit clock as the recovered clock. Additionally, during main training, the data driver may match the phases of the received clock and the recovered clock. The phase difference between the reception clock and the recovered clock can be generated even if the clock frequency is substantially the same within the error range. Therefore, the data driver can restore the clock having the frequency of the reception clock, while simultaneously correcting the phase difference between the reception clock and the recovered clock within the error range .

In step 640, when the main training is finished, the data driver waits for the transmission of the data signal from the source.

In step 645, data to be output to the display is encoded independently of the main training performed in the data driver.

In step 650, the timing controller transmits the data signal to the data driver. In a display, an image consists of a plurality of frames, and the frame consists of encoded data to control the pixels of the display. The data signal transmitted by the timing controller includes a mini training pattern, a data enable (DE), encoded data, and a source end. The data signal may be transmitted in packet form. The mini-training pattern is a training pattern necessary for the receiving side to perform mini training in which the receiving side adjusts the phase of the restored clock, the data enable is information for identifying a pixel to receive the encoded data, Is information indicating that the transmission of the data signal from the timing controller is completed. Here, the display includes a pixel array consisting of n lines arranged with m pixels, and the source end may indicate that the encoded data transmission to the pixels located on the nth line is complete. The source end indicates the start of the H-blank interval or the V-blank interval, and one frame may include a plurality of blank intervals.

In step 655, after transmitting the data signal to the data driver, the timing controller waits for the return data transfer from the data driver.

In step 660, once the data signal is received, the data driver performs mini-training, restores the data, and confirms the locking state. Using the received mini training pattern, the data driver adjusts the phase of the recovered clock to match the phase of the received clock. The data driver can perform mini-training even when the phase of the recovered clock in the main training has already been matched to the receiving clock or the encoded data to the pixels located in a new line has been received since the end of the blank interval. On the other hand, the data driver confirms the locking state of the receiver 100. If it is determined that the receiver 100 is not locked, a Low Fix signal is transmitted to the timing controller. If the recovered data contains a source end, the data driver sends a Low Fix signal to the timing controller during the blank interval.

At step 665, the data driver encodes the return data. The return data includes mini training pattern and locking data. The locking data is data indicating the locking status of the sink. For example, the locked status is 1, and the status in which the locking is not performed or the locking is released can be represented as 0.

In step 670, if the recovered data includes a source end, the data driver transfers the return data to the timing controller during the blank interval. The timing controller can not transmit data until after the data driver transfers the return data and the blank interval ends. During this interval, the data driver does not transmit any data signals or can transmit meaningless data. At the end of the blank interval, the data driver transfers the sync end to the timing controller, causing the timing controller to transmit the data signal to the pixel on the next line.

In step 675, when the return data is received, the timing controller performs mini-training, restores the data, and confirms the locking state of the timing controller. The timing controller is diverged according to the locking state of the receiver 100 of the data driver. The transmit clock used by the data driver to transmit the return data is substantially the same as the receive clock, but a new phase difference may occur due to the characteristics of the channel. Accordingly, the timing controller can perform mini training to remove the newly generated phase difference, thereby accurately restoring the return data.

When the Low Fix signal is transmitted from the data driver, the data driver is not locked. The timing controller then returns to step 625 to regenerate the main training pattern. Steps 630 to 660 are then performed.

If the return data is received from the data driver but the data signal for the line currently being transmitted is not complete (EOL (END OF LINE), No), the timing controller returns to step 650 and returns to step 650, Or the encoded data for the remaining pixels that have not been transmitted to the data driver.

If the return data is received from the data driver and the data signal for the line currently being transmitted is complete (EOL (END OF LINE), Yes), the timing controller proceeds to step 680.

In step 680, the timing controller checks if the transmission of the frame is complete and sends the V-blank data signal to the data driver. When the transmission of the frame is completed (EOF (END OF FRAME), Yes), the timing controller notifies the end of communication via, for example, the V-blank data signal. If there is a frame to be transmitted (EOF, No), the timing controller returns to step 650.

In step 685, the data driver restores the V-blank data signal received from the timing controller and determines whether the transmission of the frame is complete. If the transmission of the frame has not been completed (EOF, No), the data driver returns to step 640. When receiving the V-blank data signal and confirming that the transmission of the frame is completed (EOF, Yes), the communication with the timing controller is terminated.

8 is a diagram showing a structure of a data signal transmitted between a source and a sink. In FIG. 8, the data signal transmitted between the timing controller and the data driver of the display is represented, but this is merely an example, and is not necessarily limited thereto.

The data signal transmitted from the timing controller is composed of a main training pattern 700 for restoring the clock of the data driver and a plurality of frames. The number of frames may be larger depending on the image to be output through the display, but for convenience of description, two frames will be described by way of example. The main training pattern 700 is first transmitted to the data driver when communication between the timing controller and the data driver is started. The frames are then transmitted to the data driver. A mini training pattern 701 is transmitted to cause the data driver to match the phase of the recovered clock to the receive clock after the main training pattern 700 is transmitted. After the mini training pattern 701 is transmitted, the data enable 702 and the encoded data 703 are transmitted to the data driver until the source end is transmitted.

When the data enable 711 and the encoded data 712 for the last pixel of the line are transmitted, the timing controller transfers the source end 730 to the data driver. When the source end 730 is received, the bi-directional interface 330 of the data driver allows data transfer from the data driver to the timing controller.

Source end 730 represents the beginning of the blank section, and sink end 760 represents the end of the blank section. Return data 740 is located in the blank interval. The blank interval is a period during which the timing controller does not transmit the data signal, and the display corresponds to a blank interval such as an H-blank interval and a V-blank interval. Return data 740 includes mini training 741 and locking data 742 and optionally may further include optional data 743 for the data driver to send to the timing controller. The length of the blank section may vary depending on the data transmission method, but has the same length in the same data transmission method. Accordingly, the length of the blank blank section 750, which does not transmit any data between the timing controller and the data driver, can be determined according to the size of the return data.

When the blank interval ends, the data driver sends the sink end 760 and notifies the timing controller that there is no return data to transmit. When the sink end 760 is transmitted, the bi-directional interface 330 of the data driver allows reception of the data signal from the timing controller.

When the sink end 760 is received, the timing controller transmits the mini training pattern 771 and then transmits the data enable 772 and the encoded data 773 to the data driver.

9 is a view showing a mini training pattern.

The mini training pattern is a training pattern necessary for the receiving side to perform mini training in which the receiving side adjusts the phase of the restored clock. Referring to FIG. 9, three mini training patterns are illustrated. Compared to the main training pattern for restoring the received clock, the mini training pattern can be generated to have a simple form compared to the main training pattern since it is used to match the phases of the recovered clock and the received clock. However, the mini training pattern may have the same pattern as the main training pattern. On the other hand, since it is also possible to make the transmission clock faster than the reception clock in order to increase the transmission speed, the mini training pattern may be generated so as to be a pattern n (n is a natural number) times faster than the source clock.

Since the return data is transmitted using the transmission clock generated using the recovered clock, the rising edge or the falling edge of the mini training pattern can be aligned to the rising edge or the falling edge of the transmission clock. The source receiving the mini training pattern may match the phase by comparing the rising edge or the falling edge of the mini training pattern with the clock used to transmit the data signal, that is, the receiving clock.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

100: receiver
110: Digital phase detector
120: time-to-digital converter
130: first digital control oscillator
140: lock detector
150: deserializer
160: Digital filter
200: Transmit clock setter
210: Sigma-delta converter
300: Transmitter
310: second digital controlled oscillator
320: Serializer
330: Bi-directional interface

Claims (28)

A digital phase detector located in the receiver and detecting a phase difference between the received clock of the data signal received from the source and the recovered clock;
A time-to-digital converter located in the receiver, for generating a digitally controlled oscillator code using the phase difference detected by the digital phase detector;
A first digital controlled oscillator located at the receiver and outputting the recovered clock using the digitally controlled oscillator code;
A second digital controlled oscillator located at the transmitter and outputting a transmission clock using the digitally controlled oscillator code;
A serializer located in a transmitter for serializing return data using the transmission clock;
A lock detector for comparing the received clock with the restored clock to output a locking detection signal indicating whether the first digital controlled oscillator is locked; And
And a transmission clock configurer for providing the digital control oscillator code to the second digital control oscillator when the locking detection signal is output.
2. The method of claim 1, wherein the transmission clock configurer comprises: a transmission clock generator for providing a digital control oscillator code corresponding to the locking detection signal to the second digital control oscillator when the locking detection signal is output and the receiver is disabled; Device.
2. The apparatus of claim 1, wherein the return data is transmitted in a blank interval before transmission of the next data signal after transmission of the currently received data signal.
4. The apparatus of claim 3, wherein the blank interval is initiated by a source end transmitted by the source.
4. The apparatus of claim 3, wherein the blank interval is terminated by a sink end transmitted by the sink.
2. The apparatus of claim 1, wherein the return data comprises a mini training pattern.
7. The apparatus of claim 6, wherein the mini training pattern is a training pattern aligned to at least one rising edge of the transmit clock.
7. The apparatus of claim 6, wherein the mini training pattern is a training pattern aligned with at least one falling edge of the transmission clock.
7. The apparatus of claim 6, wherein the return data further comprises locking data indicating a locking state of the sink.
The apparatus of claim 1, wherein the digital phase detector outputs a phase difference to adjust a phase of the recovered clock using a mini training pattern received from the source after transmitting the return data.
A digital phase detector located in the receiver and detecting a phase difference between the received clock of the data signal received from the source and the recovered clock;
A time-to-digital converter located in the receiver, for generating a digitally controlled oscillator code using the phase difference detected by the digital phase detector;
A first digital controlled oscillator located at the receiver and outputting the recovered clock using the digitally controlled oscillator code;
A second digital controlled oscillator located at the transmitter and outputting a transmission clock using the digitally controlled oscillator code;
A serializer located in a transmitter for serializing return data using the transmission clock;
A lock detector for outputting a locking detection signal indicating whether the first digital control oscillator is locked using the detected phase difference; And
And a transmission clock configurer for providing the digital control oscillator code to the second digital control oscillator when the locking detection signal is output.
A method for transmitting data between a sink and a source, the method comprising: generating a transmission clock without a source and a reference clock for transmitting data using a reference clock,
Outputting a transmission clock by a digital control oscillator included in a transmitter of the sink using a reception clock of a data signal received from the source; And
And transmitting the return data to the source in a blank interval before transmission of the next data signal after the transmission of the data signal currently received from the source is changed by changing the data transmission direction between the source and the sink. A method for transmitting data using the method.
13. The method of claim 12, wherein the digital control oscillator included in the sender of the sink using the receive clock of the data signal received from the source,
Generating a digitally controlled oscillator code using a phase difference between a received clock of the data signal received from the source and a recovered clock;
Outputting the recovered clock by a digital control oscillator included in a receiver of the sink using the digital control oscillator code;
Comparing the received clock with the restored clock to determine whether to lock the digital controlled oscillator included in the receiver of the sink;
And providing the digitally controlled oscillator code to a digital controlled oscillator included in a transmitter of the sink if the digital controlled oscillator included in the receiver of the sink is locked.
13. The method of claim 12, wherein the blank interval is generated by a source end transmitted by the source.
13. The method of claim 12, wherein the return data is generated in a sink including a mini training pattern.
16. The method of claim 15, wherein the mini training pattern is a training pattern aligned to at least one rising edge of the transmission clock.
16. The method of claim 15, wherein the mini training pattern is a training pattern aligned on at least one falling edge of the transmission clock.
16. The method of claim 15, wherein the return data further comprises locking data indicating a locking state of the sink.
16. The method of claim 15, wherein the blank interval is generated by a sink that is terminated by a sink end transmitted by the sink.
13. The method of claim 12, further comprising: adjusting a phase of a recovered clock using a mini training pattern received from the source after transmitting the return data.
1. A sink for generating a transmission clock without a reference clock to transmit data,
A digital control oscillator code is generated using a phase difference between a received clock of the data signal received from the source and the recovered clock, and data is restored from the data signal using the recovered clock recovered by the generated digital control oscillator code Receiver; And
And a transmitter for generating a transmission clock by a digitally controlled oscillator code that locks the recovered clock to the reception clock and for transmitting the return data to the source using the transmission clock.
22. The receiver of claim 21, wherein the receiver
A digital phase detector for detecting a phase difference between a received clock of the data signal received from the source and the recovered clock;
A time-to-digital converter for generating a digitally controlled oscillator code using the phase difference detected by the digital phase detector; And
And a first digital controlled oscillator outputting the recovered clock using the digitally controlled oscillator code.
23. The transmitter of claim 22,
A second digital controlled oscillator outputting a transmission clock using the digitally controlled oscillator code; And
And a serializer for serializing the return data using the transmission clock.
24. The sink as set forth in claim 23, further comprising a lock detector for comparing the received clock with the restored clock to output a locking detection signal indicating whether the first digital controlled oscillator is locked.
24. The sink of claim 23, further comprising a lock detector outputting a locking detection signal indicating whether the first digital controlled oscillator is locked using the output of the digital phase detector.
26. The sink as claimed in claim 24 or 25, further comprising a transmit clock configurer for providing the digitally controlled oscillator code to the second digital controlled oscillator when the locking detection signal is output.
22. The sink of claim 21, wherein the transmitter transmits return data to the source in a blank interval before transmission of the next data signal after transmission of the data signal currently received from the source.
22. The sink of claim 21, wherein the data signal received from the source and the return data are transmitted on the same channel.

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