KR101482233B1 - Apparatus of transmitting and receiving data - Google Patents

Abstract

The present invention relates to a semiconductor device. More particularly, the present invention relates to an apparatus for transmitting and receiving data where there is no need for a process of matching a phase of a recovered clock. An exemplary embodiment of the present invention provides an apparatus for transmitting and receiving data including a receiver to recover a clock and data in data signal, and a transmitter to transmit data as a generated transmission clock using the recovered clock. The receiver includes a digital phase detector to detect a phase difference between a received clock of a first data signal and a recovered clock; a time-digital converter to generate a digital control oscillator code using the phase difference detected from the digital phase detector; a first digital control oscillator to output the recovered clock having a frequency of the received clock using the digital control oscillator code; a lock detector to output a locking detection signal indicating presence of locking of the first digital control oscillator by comparing the received clock with the recovered clock; a selector to output the digital control oscillator code when the locking detection signal is output; a desrializer to which a delay value is set according to the digital control oscillator code output from the selector; a digital control delay line to output a recovered clock having a phase corresponding to a received clock of the second data signal when a second data signal is input; and a deserializer to recover data from the second data signal using the recovered clock output from the digital control delay line.

Description

[0001] Apparatus of transmitting and receiving data [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a data transmitting and receiving apparatus that does not require a process of adjusting the phase of a recovered clock.

As the data transfer speed increases, the source transmits the clock and data together, and the sink restores the clock. In such a high-speed communication method, the CDR (Clock Data Recovery) of the sink performs a function of restoring the clock and arranging the phase of the restored clock. Sources and sinks communicate over one or more unidirectional channels that can transmit synchronous data at high speed from the source. Some communication schemes include unidirectional channels that transmit data from sink to source, or bidirectional channels between source and sink. However, the bidirectional channel transmits data at a relatively low speed as compared with the unidirectional channel.

On the other hand, a configuration for separately generating a transmission clock for bi-directional data transmission must be included in each of the source and the sink. Generally, the source is provided with a reference clock, but often it is not clear whether a reference clock is provided to the sink. For this reason, when designing a sink, it is necessary to design for a case where there is no reference clock. Also, if the number of channels increases, it becomes difficult to efficiently arrange a large number of channels.

Korean Patent Application No. 10-2013-0029394 Korean Patent Application No. 10-2013-0124877

A main training process for adjusting the frequency of the recovered clock for securing a clock when receiving a data signal and a mini training process for adjusting the phase of the recovered clock are required. Therefore, we propose a data transmission / reception device that does not perform the mini training process.

On the other hand, when receiving the data signal through the bidirectional channel, the mini training process is performed every time the direction of the data signal is changed, so that the size of data that can be transmitted at one time between the source and the sink can be limited. Therefore, we propose a data transmission / reception device that does not perform the mini training process.

Meanwhile, the unidirectional channel can be utilized as a bidirectional channel. If data transmission from the sink to the source is required, the unidirectional channel can be used as a bi-directional channel to transmit data. In this case, the transmission clock can be secured without introducing a complicated configuration into the sink.

According to an exemplary embodiment of the present invention, there is provided a data transmitting and receiving apparatus including a receiver for recovering a clock and data from a data signal and a transmitter for transmitting data to a transmission clock generated by using a recovered clock, A digital phase detector for detecting a phase difference between a received clock of the data signal and the recovered clock, a time-to-digital converter for generating a digitally controlled oscillator code using the phase difference detected by the digital phase detector, A first digital control oscillator for outputting the recovered clock having a frequency of the reception clock, a second digital control oscillator for comparing the reception clock and the recovered clock, and outputting a locking detection signal indicating whether the first digital control oscillator is locked Lock detector, the locking detection signal A delayed value is set by a digital control oscillator code output from the selector, and when a second data signal is input, a phase of the second control signal is restored to a phase of the received clock of the second data signal, And a deserializer for recovering data from the second data signal using a digital control delay line outputting a clock and a recovered clock output from the digital control delay line.

According to another exemplary embodiment of the present invention, there is provided a data transmitting and receiving apparatus including a receiver for recovering a clock and data from a data signal and a transmitter for transmitting data to a transmission clock generated using a recovered clock, A linear phase detector for detecting a phase difference between a received clock of the first data signal and the recovered clock, a differential pump for converting the phase difference detected by the linear phase detector into a control voltage, A first digital control oscillator for outputting the recovered clock having a frequency of the received clock using the digital control oscillator code, and a second digital control oscillator for comparing the received clock with the recovered clock, Lt; RTI ID = 0.0 > The delay value is set by the digital control oscillator code output from the selector, and when the second data signal is inputted, the second data And a deserializer for recovering data from the second data signal using a digital control delay line for outputting a recovered clock whose phase coincides with a reception clock of a signal and the recovered clock output from the digital control delay line, Device is provided.

In an exemplary embodiment, the digital control delay lines are connected in series, and when a plurality of digital delay cells in which the delay value is set by the digitally controlled oscillator code and the second data signal are input, And a trigger that forms a feedback loop in the cell. Here, the trigger includes a flip-flop for receiving the second data signal as a clock terminal, an inverter connected to an output terminal of the flip-flop, a first control terminal connected to an output terminal of the flip-flop, A first transfer gate and a first control terminal connected to a first end of the plurality of digital delay cells are connected to an output terminal of the inverter, 2 control stage is connected to the output terminal of the flip flop, the input stage receives the output of the last stage of the plurality of digital delay cells, and the output stage includes a second transfer gate connected to the first stage of the plurality of digital delay cells .

In an exemplary embodiment, the number of digital delay cells constituting the first digital control oscillator may be the same as the number of digital delay lines constituting the digital control delay line.

In an exemplary embodiment, the apparatus may further include a digital filter connected between the time-to-digital converter and the first digital control oscillator, for filtering the digitally controlled oscillator code output from the time-to-digital converter.

In an exemplary embodiment, the transmitter may include a second digital controlled oscillator outputting a transmit clock using the digitally controlled oscillator code output from the selector, and a serializer serializing the data using the transmit clock. The apparatus may further include a delta-sigma converter connected to the selector and the second digital control oscillator, for accumulating and averaging digital control oscillator codes output from the selector.

According to another exemplary embodiment of the present invention, there is provided a receiver for recovering a clock and data in a data signal, comprising: a digital phase detector for detecting a phase difference between a received clock of the first data signal and a recovered clock; A digital-controlled oscillator for outputting the recovered clock having a frequency of the received clock using the digital-controlled oscillator code, a digital-controlled oscillator for outputting the recovered clock having the frequency of the received clock, A lock detector for comparing a restored clock to output a locking detection signal indicating whether or not the digital control oscillator is locked, a selector for outputting the digital control oscillator code when the locking detection signal is output, a digital control oscillator code To A digital control delay line for outputting a restored clock having a phase matched to a reception clock of the second data signal when the second data signal is input, and a digital control delay line for outputting the restored clock output from the digital control delay line And a deserializer for recovering data from the second data signal.

According to another exemplary embodiment of the present invention, there is provided a receiver for recovering clock and data from a data signal, comprising: a linear phase detector for detecting a phase difference between a received clock of the first data signal and a recovered clock; An analog-to-digital converter for generating the control voltage as a digital controlled oscillator code, and a digital controlled oscillator code for outputting the recovered clock having the frequency of the received clock as an output A lock detector for comparing the received clock with the restored clock to output a locking detection signal indicating whether the digital controlled oscillator is locked or not, a selector for outputting the digital controlled oscillator code when the locking detection signal is output, , The selector A digital control delay line for outputting a recovered clock having a phase matched to a reception clock of the second data signal when a second data signal is input; And a deserializer for recovering the data from the second data signal using the output recovered clock.

In an exemplary embodiment, the digital control delay lines are connected in series, and when a plurality of digital delay cells in which the delay value is set by the digitally controlled oscillator code and the second data signal are input, And a trigger that forms a feedback loop in the cell. Here, the trigger includes a flip-flop for receiving the second data signal as a clock terminal, an inverter connected to an output terminal of the flip-flop, a first control terminal connected to an output terminal of the flip-flop, A first transfer gate and a first control terminal connected to a first end of the plurality of digital delay cells are connected to an output terminal of the inverter, 2 control stage is connected to the output terminal of the flip flop, the input stage receives the output of the last stage of the plurality of digital delay cells, and the output stage includes a second transfer gate connected to the first stage of the plurality of digital delay cells .

In an exemplary embodiment, the number of digital delay cells constituting the digital control oscillator and the number of digital delay lines constituting the digital control delay line may be the same.

In an exemplary embodiment, the apparatus may further include a digital filter connected between the time-to-digital converter and the digital control oscillator, for filtering the digitally controlled oscillator code output from the time-to-digital converter.

In an exemplary embodiment, the first data signal may be a main training pattern.

A main training process for adjusting a frequency of a recovered clock for securing a clock when receiving a data signal and a mini training process for adjusting the phase of a restored clock are omitted, The size can be increased.

On the other hand, when receiving a data signal through a bidirectional channel, the mini training process can also remove the limitation of the size of data that can be transmitted at one time between a source and a sink due to a change in the direction of a data signal.

Meanwhile, the unidirectional channel can be utilized as a bidirectional channel. If data transmission from the sink to the source is required, the unidirectional channel can be used as a bi-directional channel to transmit data. In this case, the transmission clock can be secured without introducing a complicated configuration into the sink.

Hereinafter, the present invention will be described with reference to the embodiments shown in the accompanying drawings. For the sake of clarity, throughout the accompanying drawings, like elements have been assigned the same reference numerals. It is to be understood that the present invention is not limited to the embodiments illustrated in the accompanying drawings, but may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.
1 is a diagram exemplarily showing a data transmitting and receiving apparatus.
2A is a diagram showing an exemplary configuration of a data transmission / reception apparatus.
2B is a diagram showing another exemplary configuration of the data transmission / reception device.
FIG. 3A is a detailed illustration of an exemplary configuration of the receiver shown in FIG. 2A or 2B.
FIG. 3B is a diagram for explaining an exemplary operation of the receiver shown in FIG. 3A.
4A is a diagram showing an exemplary configuration of a data transmission / reception apparatus in which a reference clock is not provided.
4B is a diagram showing another exemplary configuration of a data transmission / reception apparatus in which a reference clock is not provided.
FIG. 5 is a diagram for explaining an exemplary operation of the data transmission / reception apparatus shown in FIGS. 4A and 4B.
Figs. 6A and 6B are diagrams illustrating exemplary configurations of the selectors shown in Figs. 2A and 2B.
7 is a flowchart exemplarily showing a data transmission process between data transmission / reception devices.
8 is a diagram showing an exemplary structure of data transmitted between data transmission / reception apparatuses.

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

1 is a diagram exemplarily showing a data transmitting and receiving apparatus.

The data transmission / reception device can be distinguished from the source and the sink according to the basic function. The source and the sink are electrically connected through the channel, and the source basically transmits the synchronous source side data signal. That is, the source transmits the synchronous source side data signal at high speed through the unidirectional channel. The sink basically receives the source-side data signal from the source via the unidirectional channel. In one embodiment, the sink may transmit the sink side data signal to the source via one bidirectional channel. Therefore, the source basically transmits the source-side data signal to the synchro- nus, and additionally receives the sink-side data signal from the sink. In one embodiment, the sink may generate the transmission clock using the recovered clock in the source-side data signal, and may use it to transmit the return data as the sink-side data signal to the source. Therefore, a data transmitting and receiving apparatus that does not require a mini-training process can be applied not only to unidirectional data transmission between a source and a sink but also to bidirectional data transmission. Hereinafter, for convenience of explanation, it is assumed that one data transmitting and receiving apparatus has both a receiver and a transmitter and data transmission is performed through a bidirectional channel. However, when the data transmitting and receiving apparatus is divided into a receiver and a transmitter, It does not exclude the case where it is performed through a channel.

The source and sink comprise a transmitter Tx and a receiver Rx, respectively. The receiver Rx of the source is a clock and data recovery (CDR) for restoring the clock and data in the sink-side data signal transmitted by the transmitter Tx of the sink. The receiver Rx of the sink is a source Side data signal and a CDR that restores the clock and data. In one embodiment, the sender Tx of the sink may generate a transmit clock having a frequency substantially equal to the clock recovered by the CDR. Here, the transmitter Tx of the source can transmit the source side data to the multi-phase clock generated by using the reference clock.

The return data which is the sink side data signal is transmitted from the sink to the source in the blank section where the source side data signal transmission is suspended. During the blank interval, the data transmission direction of the channel is changed so that only the sink can transmit data. The blank interval may occur at least once during communication of the data signal between the source and the sink. The blank section may have a specific length depending on the data transmission method. On the other hand, when compared with the period in which the data signal is transmitted, the length of the blank interval is relatively shorter than the interval in which the data signal is transmitted. However, by configuring the size of the return data to be smaller than the blank interval, bi-directional communication can be performed at the same time without affecting the data transmission efficiency between the source and the sink. On the other hand, even if the size of the return data is larger than the blank interval, the return data may be divided and transmitted using the next blank interval, thus not affecting the data transmission efficiency between the source and the sink. In addition, if the size of the return data is larger than the blank interval, the bit rate may be increased. In this case, the serializer of the sender Tx of the sink can transmit the bit rate of the restored clock using the multiphase clock .

2A is a diagram showing an exemplary configuration of a data transmission / reception apparatus.

Referring to FIG. 2A, a sink is composed of a receiver Rx 100 and a transmitter Tx 300, and is electrically connected to a source through a bidirectional interface. The receiver Rx 100 generates a digitally controlled oscillator code using the received clock of the source-side data signal received from the source and the phase difference of the recovered clock, and outputs the digitally controlled oscillator code using the clock recovered by the generated digitally controlled oscillator code. Side data signal. The transmitter Tx 300 transmits the sink side data to the source. Here, since the sink and the source can have substantially the same configuration, the sink will be described as an example of the data transmission / reception device in FIG.

The sink receiver Rx 100 includes a digital phase detector 110, a time-to-digital converter 120, a digital control oscillator 150, a lock detector 160, a selector 170, a digital control delay line 180, and a deserializer (190). Meanwhile, the receiver Rx 100 of the sink may further include a digital filter 130.

The digital phase detector 110 detects the phase difference between the received clock and the recovered clock. A phase difference between the phase of the received clock of the source-side data signal input through the bidirectional interface 330 and the phase of the recovered clock using the received clock, and a detected phase difference indicating whether the phase of the recovered clock is later or earlier than the received clock . Here, the source side data signal may include a main training pattern. The digital phase detector 110 may be a non-linear detector, such as, for example, an Alexander phase detector, an Oversampled phase detector, or a Bang-Bang phase detector. Compared to a linear phase detector that compares the phase difference between the input source side data signal and the recovered clock and generates an up signal pulse UP and a down signal pulse DN having a width proportional to the difference, The information on the magnitude of the error can be ignored and the polarity of the phase error can be outputted.

The time-to-digital converter 120 is connected to the output of the digital phase detector 110 and converts the detected phase difference into a digitally controlled oscillator code. For example, the detected phase difference can be output in various forms such as UP / DN, Early / late, Error / Ref, etc., and the phase of the recovered clock is fast / slow , And the time-to-digital converter 120 converts the detected phase difference into a digitally controlled oscillator code which is a digital signal of n bits (n is a natural number). Therefore, until the digital control oscillator 150 is locked, digital control oscillator codes having different values can be continuously output. When the digitally controlled oscillator 150 is locked, the time-to-digital converter 120 may output a fixed digitally controlled oscillator code.

The digital filter 130 may filter the digitally controlled oscillator code output from the time-to-digital converter 120 in digital mode. The jitter noise characteristic of the clock recovered by the digital filter 130 and the transmission clock can be improved.

The digital control oscillator 150 is connected to the output of the time-to-digital converter 120 or the output of the digital filter 130 and outputs the clock recovered by the digitally controlled oscillator code. The digital control oscillator 150 increases or decreases the frequency of the clock according to the n-bit digitally controlled oscillator code. For example, when using a 9-bit digitally controlled oscillator code, the digitally controlled oscillator 150 may output a clock having a maximum of 512 different frequencies. The digital control oscillator 150 may use the main training pattern to substantially match the frequency of the recovered clock to the frequency of the receive clock. To this end, the digital phase detector 110, the time-to-digital converter 120, and the digital controlled oscillator 150 form a loop, and the recovered clock may not be supplied to the deserializer 190.

The lock detector 160 is connected to the output terminal of the digital phase detector 110 and determines whether the digital control oscillator 150 is locked. Specifically, the lock detector 160 outputs a locking detection signal when the recovered clock coincides with the reception clock using the phase difference output from the digital phase detector 110. The digital phase detector 110 detects the phase difference between the received clock and the recovered clock. The phase difference output by the digital phase detector 110 may be in various forms. For example, the phase difference may be a pulse indicating fast / slow or a pulse indicating Reference / Error. Regardless of the manner in which the phase difference is output, if the digital control oscillator 150 is locked, the output of the digital phase detector 110 will remain constant. For example, in the case of outputting as a pulse indicating fast / slow, the fast pulse and the slow pulse may be output at the same time or output as a very short pulse. In addition, the locking state can be expressed in various forms. Therefore, the lock detector 160 can determine whether the lock detector 160 is in the locked state using the output pattern of the digital phase detector 110.

Meanwhile, the lock detector 160 is connected to the output terminal of the digital control oscillator 150, and may determine whether the digital control oscillator 150 is locked. The lock detector 160 compares the received clock with the clock recovered by the digital control oscillator 150 and outputs a locking detection signal when the locking is detected. For example, if the received clock is compared with the rising edge of the recovered clock and matches, the lock detector 160 may determine that the clock has been locked. As another example, the lock detector 160 may determine whether or not to lock by counting the number of times the phases of the received clock and the rising edge of the recovered clock coincide with each other. As another example, it is possible to compare two recovered clocks selected from a plurality of recovered clocks output from the digital control oscillator 150, and determine whether the recovered clock coincides with the received clock. Accordingly, the position of the lock detector 160 can be changed according to the manner of detecting whether or not the lock detector 160 is locked. Of course, it is also possible to judge whether or not the camera is locked by using various methods other than the exemplary method.

2A, the lock detector 160 is located at the receiver Rx 100, but the present invention is not limited thereto. It is also shown that the locking detection signal is directly provided from the lock detector 160 to the selector 170, but this is merely an example for the sake of understanding, and the locking detection signal can be transmitted either alone Signal. ≪ / RTI >

The selector 170 is connected to the output of the time-to-digital converter 120 or the digital filter 130 and outputs a digitally controlled oscillator code. The selector 170 may provide a digitally controlled oscillator code to the digital control delay line 180 upon receipt of the locking detection signal from the lock detector 160. [ Meanwhile, in order to prevent power loss caused by the transmitter Tx 300 or to prevent noise from occurring in the transmission medium to which the bidirectional interface 330 is connected, the sink control circuit turns off the transmitter Tx 300 during the reception operation, And may turn off receiver Rx 100 during operation. The selector 170 may provide a digitally controlled oscillator code to the digital control delay line 180 by a combination of a locking detection signal and a control signal from the control circuit. The example and operation of the selector 170 structure will be described with reference to Figs. 6A and 6B. On the other hand, in one embodiment, the selector 170 may provide the digitally controlled oscillator code to the transmitter Tx 300 when the transmitter Tx 300 utilizes the recovered clock as the transmit clock. An embodiment in which the selector 170 provides a digitally controlled oscillator code to the transmitter Tx 300 will be described with reference to Figures 4A and 4B.

The digital control delay line 180 substantially matches the phase of the recovered clock with the phase of the received clock. The digital control delay line 180 is provided with a digitally controlled oscillator code from the selector 170 and receives a data signal from the bidirectional interface 330. The digital control delay line 180 may have substantially the same structure as the digital control oscillator 150. That is, the digital control delay line 180 may be set to output the recovered clock output by the digital control oscillator 150 by a digitally controlled oscillator code that locks the digitally controlled oscillator 150. Here, the digital control delay line 180 may not output the recovered clock until the data signal is input. To this end, the output of the final stage of the digital control delay line 180 is not fed back to the first stage until the data signal is input, and the output of the final stage is fed back to the first stage only when the data signal is input, Lt; / RTI > The configuration and operation of the digital control oscillator 150 and the digital control delay line 180 will be described with reference to FIGS. 3A and 3B.

The deserializer 190 parallelizes the serial data signal input through the bidirectional interface 330 using the recovered clock. The parallel data is output to the control circuit (not shown) of the sink. The sink control circuit not only processes the parallel data but also controls the operation of the receiver Rx 100, the transmitter Tx 300, and the like.

The bidirectional interface 330 controls the data transfer direction between the source and the sink. When receiving the source-side data signal, the bidirectional interface 330 stops transmission of the sink-side data signal from the sink to the source, and when transmitting the sink-side data signal, the bidirectional interface 330 transmits the source- And stops receiving the data signal. The data transmission direction of the bidirectional interface 330 is determined by the control signal of the control circuit. Here, the control circuit allows the bidirectional interface 330 to send return data from the sink to the source by the source end received from the source. Further, when the transmission of the return data is completed, the control circuit transmits the sink end to the source and allows the bidirectional interface 330 to receive the source-side data signal.

2B is a diagram showing another exemplary configuration of the data transmission / reception device.

Referring to FIG. 2B, a sink is composed of a receiver Rx 100 and a transmitter Tx 300, and is electrically connected to a source through a bidirectional interface. The sync clock generation device includes a linear phase detector 115, a charge pump / LPF 125, an analog-to-digital converter 135, a digital control oscillator 150, a lock detector 160, a selector 170, And a control oscillator 310. The same description of the components described in FIG. 2A is omitted.

The linear phase detector 115 detects the phase difference between the received clock and the recovered clock. A phase difference between the phase of the received clock of the source-side data signal input through the bidirectional interface 330 and the phase of the recovered clock using the received clock, and a detected phase difference indicating whether the phase of the recovered clock is later or earlier than the received clock . The Hogge-type phase detector, which is a typical linear phase detector 115, has a structure in which two simple phase detectors including a D flip-flop and an XOR gate are connected, but the present invention is not limited thereto and a linear phase detector having various configurations can be applied . The linear phase detector 115 compares the phase difference between the data signal and the recovered clock and generates an up signal pulse UP and a down signal pulse DN having a width proportional to a phase difference, for example.

The charge pump / LPF 125 includes a charge pump and a low pass filter, and is connected to the output terminal of the linear phase detector 115. The charge pump / LPF 125 outputs the control voltage Vctrl according to the detected phase difference. Taking the simplest configuration as an example, the charge pump may consist of two constant current sources and two switches controlling the current supply by each constant current source, but this is not necessarily the case. The current supplied by each constant current source is changed by the switch which is switched by the up signal pulse UP and the down signal pulse DN output from the linear phase detector 115. [ Similarly, taking the simplest configuration as an example, the low-pass filter may be an RC filter composed of a combination of a resistor and a capacitor connected to the output terminal of the charge pump, but is not limited thereto. With the up signal pulse UP and the down signal pulse DN, the charge pump can perform, for example, a pull operation for absorbing charge from a capacitor included in the low pass filter or a push operation for supplying charge. The control voltage Vctrl output from the low-pass filter is lowered by the pull-up operation of the charge pump, and the control voltage Vctrl can be raised by the push operation.

The analog-to-digital converter 135 converts the control voltage Vctrl into an n-bit digitally controlled oscillator code. Therefore, until the digital control oscillator 150 is locked, digital control oscillator codes having different values can be continuously output. When the digitally controlled oscillator 150 is locked, the analog-to-digital converter 135 can output a substantially fixed, digitally controlled oscillator code. Here, substantially fixed means that the digitally controlled oscillator code changes within an allowable error range (margin).

Meanwhile, the analog-to-digital converter 135 may be designed to have various structures. For example, the analog-to-digital converter 135 may convert the control voltage Vctrl to an 8-bit digitally controlled oscillator code, but the number of bits of the digitally controlled oscillator code may be increased for precise control. For example, the analog-to-digital converter 135 may comprise eight resistors (R1 to R8) for voltage dividing the reference voltage Vref and eight comparators (C1 to C8) for comparing the control voltage and the voltage divided Vref have. R1 to R8 have the same resistance value and divide Vref by 1/8. Here, Vref can be determined in consideration of the maximum value of Vctrl. The comparators C1 to C8 compare the input control voltage Vctrl with the divided Vref to output the most significant bit C7 to the least significant bit C0, respectively. The outputted C7 to C0 can constitute an 8-bit digitally controlled oscillator code. On the other hand, the analog-to-digital converter 135 may further comprise a code converter for converting the output C7 to C0 into a digitally controlled oscillator code for controlling the first and second digital control oscillators.

The lock detector 160 outputs a locking detection signal when the recovered clock coincides with the reception clock. A method of determining whether the recovered clock coincides with the reception clock can be variously implemented. 2B, when the lock detector 160 is connected to the output terminal of the linear phase detector 115, when the digital control oscillator 150 is locked and the recovered clock substantially matches the receive clock, the up signal pulse UP And the down signal pulse DN are output in a specific pattern. For example, if the up signal pulse UP and the down signal pulse DN are outputted as a short pulse or no pulse is outputted, the lock detector 160 can output a locking detection signal. On the other hand, when the lock detector 160 is connected to the output terminal of the digital control oscillator 150, when the digital control oscillator 150 is locked, the lock detector 160 is restored by the receive clock and the digital control oscillator 150 And outputs a locking detection signal when the locking occurs. For example, if the received clock is compared with the rising edge of the recovered clock and matches, the lock detector 160 may determine that the clock has been locked. As another example, the lock detector 160 may determine whether or not to lock by counting the number of times the phases of the received clock and the rising edge of the recovered clock coincide with each other. As another example, it is possible to compare two recovered clocks selected from a plurality of recovered clocks output from the digital control oscillator 150, and determine whether the recovered clock coincides with the received clock. As another example, when the lock detector 160 is coupled to the output of the analog-to-digital converter 135, the lock detector 160 may output a locking detection signal if the digitally controlled oscillator code is substantially fixed. It is needless to say that it is possible to judge whether or not to be locked by using various methods.

FIG. 3A is a detailed view of an exemplary configuration of the receiver shown in FIG. 2A or 2B, and FIG. 3B is a diagram for explaining an exemplary operation of the receiver shown in FIG. 3A.

Referring to FIG. 3A, the digital control delay line 180 is composed of the same number of digital delay cells as the number of digital delay cells constituting the digital control oscillator 150. A plurality of digital delay cells 150a, 150b, 150c and 150d constituting the digital control oscillator 150 are connected in series, and a final-stage output is a digital DLL (delay-locked loop) fed back to the input of the first stage . A plurality of digital delay cells 150a, 150b, 150c, and 150d may be set to a delay value by a digital control oscillator code DIG_CON. In order to adjust the delay value by the digital control oscillator code DIG_CON, the digital delay cell can be implemented in various forms. For example, in a simple form, the digital delay cell is composed of a MUX for selecting one of a plurality of branches and a plurality of branches, and each branch is connected to a different number of buffers in series, and the digitally controlled oscillator code DIG_CON Any one of a plurality of branches can be selected. In addition, Mohammad Maymandi-Nejad et al., "A Digitally Programmable Delay Element: Design and Analysis" (IEEE Transactions on Very Large Scale Integration Systems, Vol. , A digitally controlled delay element, a delay element using variable resistor, and the like. That is, the digital delay cell shown in FIG. 3A is not limited to a specific configuration and can be implemented to have a known configuration.

The configuration of the digital delay cell of the digital control delay line 180 is the same as that of the digital delay cell of the digital control oscillator 150. [ If both digital delay cells are the same, the digital control delay line 180 is enabled to operate by the digitally controlled oscillator code DIG_CON where the digitally controlled oscillator 150 is locked. A plurality of digital delay cells 180a, 180b, 180c and 180d constituting a digital control delay line 180 are connected in series and are connected to a digital DLL 180a through which the output of the final stage is fed back to the input of the first stage (Delay-locked loop). A plurality of digital delay cells 180a, 180b, 180c, and 180d may be set to a delay value by a digitally controlled oscillator code DIG_CON.

The digital control delay line 180 having the delay value set by the digitally controlled oscillator code DIG_CON operates as a digitally controlled oscillator by the trigger 181 when a data signal is input. The output of the last stage of the digital control delay line 180 is not fed back to the input of the first stage until the data signal is input. The output of the digital control delay cell 180d which is the final stage of the digital control delay line 180 is input to the digital control delay cell 180a which is the first stage of the digital control delay line 180, (Delay-locked loop).

The trigger 181 prevents the output terminal of the digital delay cell 180d which is the final stage of the digital control delay line 180 from being connected to the input terminal of the digital delay cell 180a which is the first stage while the data signal is not input, When a signal is input, a feedback loop is established in which the output terminal of the digital delay cell 180d is connected to the input terminal of the digital delay cell 180a. Referring to FIG. 3A, an exemplary configuration of a trigger 181 is shown. The exemplary trigger 181 includes a flip flop 183, an inverter 185, and a pair of transfer gates 187a and 187b. The clock terminal of the flip-flop 183 is connected to the bidirectional interface 330 to receive the source-side data signal, and the input terminal of the flip-flop 183 is connected to the driving voltage VDD. The output terminal of the flip flop 183 is connected to the input terminal of the inverter 185, the first control terminal of the first transfer gate 187a formed of PMOS, and the second control terminal of the second transfer gate 187b formed of the NMOS . The output terminal of the inverter 185 is connected to the second control terminal of the first transfer gate 187a formed of NMOS and the first control terminal of the second transfer gate 187b formed of the PMOS. The input terminal of the first transfer gate 187a is connected to the bidirectional interface 330 to receive the source side data signal and the input terminal of the second transfer gate 187b is connected to the digital delay cell And is connected to the output terminal of the second switch 180d. The output terminal of the first transfer gate 187a and the output terminal of the second transfer gate 187b are connected to the input terminal of the digital delay cell 180a which is the first stage of the digital control delay line 180. [

Referring to FIG. 3B, an exemplary operation of the receiver will be described. The digitally controlled oscillator code DIG_CON that locks the digitally controlled oscillator 150 is delivered to the plurality of digital delay cells 180a, 180b, 180c, and 180d of the digitally controlled delay line 180 by the selector 170. The selector 170 delivers the digitally controlled oscillator code DIG_CON to the digital control delay line 180 in accordance with the locking detection signal provided by the lock detector 160 and controls the plurality of digital delay cells 180a 180b, 180c, 180d are set to the same state as the plurality of digital delay cells 150a, 150b, 150c, 150d of the digital control oscillator 150. [ That is, the delay values of the plurality of digital delay cells 180a, 180b, 180c and 180d and the plurality of digital delay cells 150a, 150b, 150c and 150d corresponding to them are substantially the same. Even if the delay value of the plurality of digital delay cells 180a, 180b, 180c and 180d is set, the trigger 181 is not fed back to the feedback loop of the digital control delay line 180 while the source side data signal is not received (t < Is not set. That is, the first transfer gate 187a is in an ON state and the second transfer gate 187b is in an OFF state. Thus, the digital control delay line 180 does not output the recovered clock.

When the source side data signal is received (t = t1), the bidirectional interface 330 supplies the source side data signal to the digital delay cell 180a which is the first stage of the plurality of digital delay cells 180a, 180b, 180c and 180d do. When the source-side data signal is input, the digital delay cells 180a, 180b, 180c and 180d start to output clocks corresponding to the delay values. That is, the digital delay cells 180a, 180b, 180c, and 180d output the recovered clocks that are in phase with the source side data signal. At this time, the source-side data signal is also input to the clock terminal of the flip-flop 183, and the trigger signal F_EN is output at time t2-t1 through the output terminal of the flip-flop 183 (t = t2). Here, the time difference t2-t1 may be sufficiently smaller than one period of the reception clock or the restored clock. The output trigger signal F_EN is input to the PMOS of the first transfer gate 187a and the NMOS of the second transfer gate 187b and the trigger signal F_ENB inverted by the inverter 185 is input to the first transfer gate 187a The NMOS, and the PMOS of the second transfer gate 187b. Thus, the first transfer gate 187a is turned off and the second transfer gate 187b is turned on to set the feedback loop of the digital control delay line 180. [ By the set feedback loop, the digital control delay line 180 operates as a digital controlled oscillator and outputs a recovered clock that is in phase with the receive clock. Time t3 is the time at which the edge of the clock recovered by the digital control oscillator 150 occurs and time t4 is the time at which the edge of the clock recovered by the digital control delay line 180 occurs, 180). &Lt; / RTI &gt;

4A is a diagram showing an exemplary configuration of a data transmission / reception apparatus in which a reference clock is not provided.

Referring to FIG. 4A, a sink is composed of a receiver Rx 100 and a transmitter Tx 300, and is electrically connected to a source through a bidirectional interface. The receiver Rx 100 generates a digitally controlled oscillator code DIG_CON using the received clock of the source-side data signal received from the source and the phase difference of the recovered clock, and uses the clock recovered by the generated digital control oscillator code DIG_CON And restores the data in the source-side data signal. Transmitter Tx 300 generates a transmission clock by a digitally controlled oscillator code DIG_CON that locks the recovered clock to the reception clock, and transmits the return data to the source using the transmission clock. Here, since the sink and the source can have substantially the same configuration, the sink will be described as an example of the data transmission / reception device in FIG.

The digital control oscillator 310 provides a transmit clock. The digital control oscillator 310 outputs the transmit clock using the digitally controlled oscillator code DIG_CON provided by the selector 170 by the locking detection signal. For example, the digital control oscillator 150 of the receiver Rx 100 and the transmitter Tx 300 digital control oscillator 310 may have the same structure. Therefore, the digital control oscillator 310 and the digital control oscillator 150 can output clocks having the same frequency by the digital control oscillator code DIG_CON for outputting the locking detection signal.

The serializer 320 serializes the data input by the control circuit and outputs the serialized data. The output data is transmitted to the source via the bidirectional interface 330. The control circuit of the sink transmits the return data including the locking data and the sink end indicating the end of the blank interval to the source via the serializer 320. Meanwhile, the serializer 320 may transmit the return data at a bit rate equal to or higher than the bit rate of the recovered transmission clock using the multi-phase clock.

4B is a diagram showing another exemplary configuration of a data transmission / reception apparatus in which a reference clock is not provided. The same description of the components described in Fig. 4A is omitted.

Compared to FIG. 4A, the sink shown in FIG. 4B further includes a sigma-delta converter 200 located between receiver Rx 110 and transmitter Tx 300. The sigma-delta converter 200 accumulates the digital control oscillator code DIG_CON output from the selector 170 and outputs an average value. In detail, the sigma-delta converter 200 changes the number of bits of the digitally controlled oscillator code through an error feedback operation using the difference of the two digitally controlled oscillator codes. In this embodiment, the sigma-delta converter 200 can output a digitally controlled oscillator code of K (K is a natural number) bits. The jitter noise characteristic of the clock recovered by the sigma-delta converter 210 and the transmission clock can be improved. Meanwhile, in another embodiment, the sigma-delta converter 210 may be replaced by an accumulator.

In one embodiment, driving the sigma-delta converter 200 during a receive operation can reduce the time required to acquire the transmit clock. In another embodiment, when a locking detection signal is output, the sigma-delta converter 200 and the transmitter Tx 300 may be turned on to generate a transmit clock. As another embodiment, even if a locking detection signal is output, the transmitter Tx 300 may be turned on only by control of the control circuit. As another embodiment, even if a locking detection signal is output, the transmitter Tx 300 may be turned on only when the receiver Rx 100 is turned off.

FIG. 5 is a diagram for explaining an exemplary operation of the data transmission / reception apparatus shown in FIGS. 4A and 4B.

In the receiver Rx 100, when the source-side data signal is inputted through the bidirectional interface 500, the digital-control oscillator 150 operates so that the recovered clock is locked to the received clock of the input source-side data signal (510) . When a locking occurs between the received clock and the recovered clock, the lock detector 160 outputs a locking detection signal (520). Thereafter, while the transmitter Tx 300 is operating, the receiver Rx 100 is turned off by control of the control circuit (530).

In the transmitter Tx 300, an n-bit digitally controlled oscillator code corresponding to the locking detection signal is transmitted to the second digital controlled oscillator 310 by the selector 170 (540). Thereafter, the second digital control oscillator 310 outputs a transmission clock having a fixed frequency by the n-bit digital control oscillator code (550). Transmitter Tx 300 transmits the sync data to the source using the transmit clock (560).

In one embodiment, when a locking detection signal is output, the transmitter Tx 300 may be turned on to generate a transmit clock. In another embodiment, even if a locking detection signal is output, the transmitter Tx 300 may be turned on only by control of the control circuit. As another embodiment, even if a locking detection signal is output, the transmitter Tx 300 may be turned on only when the receiver Rx 100 is turned off. 5, steps 520 and 540 are shown to be performed at the same point in time, but may be performed at different points in time according to the embodiment. Likewise, steps 530 and 550 are not necessarily performed at the same time.

6A and 6B are diagrams showing exemplary configurations of the selectors shown in Figs. 2A to 2B.

Referring to FIG. 6A, the selector 170 may be implemented using a 2: 1 multiplexer with two inputs. The first input of the multiplexer is coupled to an analog-to-digital converter 160 to receive a digitally controlled oscillator code. The second input of the multiplexer is coupled to the output of the multiplexer and receives the digitally controlled oscillator code that is output. This connection structure allows a digital controlled oscillator code to be provided to the digital controlled oscillator 310 of the transmitter Tx 300 even when the receiver Rx 100 is turned off and no digitally controlled oscillator code is provided. The control signal provided by the control circuitry of the sink may act as an enable signal to turn the multiplexer on or off, or it may act to select the input of the multiplexer with the locking detection signal.

In one embodiment, the signal selecting the input of the multiplexer may be a locking detection signal provided from the lock detector 160. The first input terminal can be selected by the locking detection signal. On the other hand, the multiplexer can be configured to basically select the second input terminal if the locking detection signal is not inputted. Thereby, a digital control oscillator code may not be provided to the digital control oscillator 310 of the transmitter Tx 300 before the locking detection signal is provided. Also, even if the lock detector 160 is included in the receiver Rx 100 and turned off, a digitally controlled oscillator code corresponding to the lock detection signal can be continuously provided to the digital control oscillator 310 of the transmitter Tx 300.

In another embodiment, the signal selecting the input of the multiplexer may be a combination of a locking detection signal and a control signal. To this end, a logic circuit (not shown) may be connected to the multiplexer for receiving the locking detection signal and the control signal, performing a logic operation on the locking detection signal, and inputting the logic detection signal and the control signal to the multiplexer. On the other hand, a locking detection signal is provided to the control circuit, and the control circuit can turn on the transmitter Tx 300 after receiving the locking detection signal.

Referring to FIG. 6B, the selector 170 may be configured as a latch storing a digitally controlled oscillator code. The digital control oscillator code corresponding to the locking detection signal is generated even if the receiver Rx 100 is turned off before the operation of providing the transmission clock is started or before the transmitter Tx 300 is turned on, To be provided to the digital control oscillator 310 of the transmitter Tx 300.

On the other hand, although the output terminal of the latch is shown connected to the first input terminal of the multiplexer of Fig. 6A, the control circuit may control the input / output of the latch so that the multiplexer may be omitted or replaced with a simple circuit element such as a switch have.

7 is a flowchart exemplarily showing a data transmission process between data transmission / reception devices. In FIG. 7, the timing controller and the data driver of the display are expressed as a source and a sink, respectively, but this is merely an example, and the present invention is not limited thereto.

In steps 700 and 705, power is supplied and internal power is supplied to the timing controller and the data driver, respectively.

In steps 710 and 715, when the internal power is supplied, the start-up circuit for starting the timing controller and the data driver is driven. The timing controller and the data driver are internally reset and initialized by the start-up circuit.

In step 720, the initialized data driver waits for a data signal from the timing controller.

In step 725, the main training generation block generates a main training pattern necessary for the data driver to recover the clock and data in the data signal. The main training pattern is a training pattern required for the data driver to recover the receive clock of the source-side data signal.

In step 730, the timing controller transmits the main training pattern generated in the main training generating block to the data driver. The main training pattern is transmitted over the connected channel between the timing controller and the data driver. Here, if either the timing controller or the data driver is transmitting the data signal, the other party can not transmit the data signal. The data transfer direction between the source and the sink can be controlled by the bidirectional interface 330. That is, the bidirectional interface 330 may prevent the return data output from the transmitter Tx 300 from being transmitted to the timing controller while the timing controller is transmitting the data signal.

In step 735, upon receiving the main training pattern from the timing controller, the data driver may perform main training to restore the clock and prepare for transmission. Using the main training pattern, the digital control oscillator 150 of the data driver restores the clock of the source-side data signal. Accordingly, when the digital control oscillator 150 located in the receiver Rx 100 is locked, the digital control delay line 180 becomes the same state as the digital control oscillator 150. When the source side data signal is input, Can be output. Meanwhile, when the digital control oscillator 150 of the receiver Rx 100 is locked, the digital control oscillator 310 of the transmitter Tx 300 can generate the same transmission clock as the restored clock.

In step 740, when the main training is finished, the data driver waits for the transmission of the data signal from the source.

In step 745, data to be output to the display is encoded independently of the main training performed in the data driver.

In step 750, the timing controller transmits the data signal to the data driver. In a display, an image consists of a plurality of frames, and the frame consists of encoded data to control the pixels of the display. The data signal transmitted by the timing controller includes data enable (DE), encoded data, and a source end. The data signal may be transmitted in packet form. The data enable is information for identifying a pixel to receive the encoded data, and the source end is information indicating that the transmission of the data signal from the timing controller is completed. Here, the display includes a pixel array consisting of n lines arranged with m pixels, and the source end may indicate that the encoded data transmission to the pixels located on the nth line is complete. The source end indicates the start of the H-blank interval or the V-blank interval, and one frame may include a plurality of blank intervals.

In step 755, after transmitting the data signal to the data driver, the timing controller waits for a return data transfer from the data driver.

In step 760, once the data signal is received, the data driver restores the data and confirms the locking state. The received source-side data signal is input to the digital control delay line 180 set by the digitally controlled oscillator code in step 735. After the reception of the source-side data signal, the last and last ends of the digital control delay line 180 are connected so that the digital control delay line 180 operates as a digital controlled oscillator and the phase of the clock signal of the received source- And output the matched restored clock. On the other hand, the data driver confirms the locking state of the receiver Rx 100. If it is confirmed that the receiver Rx 100 is not locked, a Low Fix signal is transmitted to the timing controller. If the recovered data contains a source end, the data driver sends a Low Fix signal to the timing controller during the blank interval.

In step 765, the data driver encodes the return data. The return data may include the locking data. The locking data is data indicating the locking state of the data driver. For example, the locking state is 1, and the state where the locking is not performed or the locking is released can be represented by 0.

In step 770, if the recovered data includes a source end, the data driver transfers the return data to the timing controller during the blank interval. The timing controller can not transmit data until after the data driver transfers the return data and the blank interval ends. During the interval in which the timing controller transmits the source-side data signal, the data driver may not send any data signal or output meaningless data, and may not be transmitted to the timing controller by the bidirectional interface 330. At the end of the blank interval, the data driver transfers the sync end to the timing controller, causing the timing controller to transmit the data signal to the pixel on the next line.

In step 775, when the return data is received, the timing controller restores the return data and confirms the locking state of the timing controller. The timing controller is diverged according to the locked state of the receiver Rx 100 of the data driver. The transmit clock used by the data driver to transmit the return data is substantially the same as the receive clock, but a new phase difference may occur due to the characteristics of the channel.

When the Low Fix signal is transmitted from the data driver, the data driver is not locked. The timing controller then returns to step 725 to regenerate the main training pattern. Steps 730 to 760 are then performed.

If the return data is received from the data driver but the data signal for the line currently being transmitted is not complete (EOL (END OF LINE), No), the timing controller returns to step 750 to return all pixels Or the encoded data for the remaining pixels that have not been transmitted to the data driver.

If the return data is received from the data driver and the data signal for the line currently being transmitted is complete (EOL (END OF LINE), Yes), the timing controller proceeds to step 780.

In step 780, the timing controller checks whether the transmission of the frame is completed and transmits the V-blank data signal to the data driver. When the transmission of the frame is completed (EOF (END OF FRAME), Yes), the timing controller notifies the end of communication via, for example, the V-blank data signal. If there is a frame to be transmitted (EOF, No), the timing controller returns to step 750.

In step 785, the data driver restores the V-blank data signal received from the timing controller, and determines whether the transmission of the frame is completed. If the transmission of the frame is not completed (EOF, No), the data driver returns to step 740. When receiving the V-blank data signal and confirming that the transmission of the frame is completed (EOF, Yes), the communication with the timing controller is terminated.

8 is a diagram showing an exemplary structure of data transmitted between data transmission / reception apparatuses. In FIG. 8, a data signal transmitted between the timing controller and the data driver of the display is expressed, but this is merely an example, and the present invention is not limited thereto.

The data signal transmitted by the timing controller is composed of a main training pattern 800 for restoring the clock of the data driver and a plurality of frames. The number of frames may be larger depending on the image to be output through the display, but for convenience of description, two frames will be described by way of example. The main training pattern 800 is first transmitted to the data driver when communication between the timing controller and the data driver is started. The frames are then transmitted to the data driver. After the main training pattern 800 is transmitted, the data enable 801 and the encoded data 802 are transmitted to the data driver until the source end is transmitted.

When the data enable 811 and the encoded data 812 for the last pixel of the line are transmitted, the timing controller transfers the source end 830 to the data driver. When the source end 830 is received, the bidirectional interface 330 of the data driver allows data transfer from the data driver to the timing controller.

The source end 830 indicates the beginning of the blank interval 820 and the sync end 860 indicates the end of the blank interval 820. The return data 840 is located in the blank interval 820. The blank interval 820 is a period during which the timing controller does not transmit the data signal, and the display corresponds to the blank interval 820, for example, the H-blank interval and the V-blank interval. The return data 840 includes the locking data 841 and may optionally include optional data 842 to be transmitted by the data driver to the timing controller. The length of the blank section 820 may vary depending on the data transmission scheme, but may have the same length in the same data transmission scheme. Accordingly, the length of the blank blank section 850, which does not transmit any data between the timing controller and the data driver, can be determined according to the size of the return data.

When the blank interval 820 ends, the data driver sends the sink end 860 and notifies the timing controller that there is no return data to transmit. When the sink end 860 is transmitted, the bi-directional interface 330 of the data driver allows reception of the data signal from the timing controller.

When the sink end 860 is received, the timing controller transmits the data enable 871 and the encoded data 872 to the data driver.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

100: receiver
110: Digital phase detector
115: linear phase detector
120: time-to-digital converter
125: Charge pump / LPF
130: Digital filter
135: Analog-to-digital converter
150: Digital controlled oscillator
160: Rock detector
170: selector
180: Digital control delay line
190: Deserializer
200: Transmit clock setter
300: Transmitter
310: Digital controlled oscillator
320: Serializer
330: Bi-directional interface

Claims (15)

A data transmitting and receiving apparatus comprising: a receiver for recovering a clock and data from a data signal; and a transmitter for transmitting data to a transmission clock generated by using the recovered clock,
The receiver
A digital phase detector for detecting a phase difference between a received clock of the first data signal and the recovered clock;
A time-to-digital converter for generating a digitally controlled oscillator code using the phase difference detected by the digital phase detector;
A first digital controlled oscillator outputting the recovered clock having a frequency of the received clock using the digital controlled oscillator code;
A lock detector for comparing the received clock with the restored clock to output a locking detection signal indicating whether the first digital controlled oscillator is locked;
A selector for outputting the digital control oscillator code when the locking detection signal is output;
A digital control delay line for outputting a recovered clock whose phase is matched to a reception clock of a second data signal when a delay value is set by a digital control oscillator code output from the selector and a second data signal is input; And
And a deserializer for recovering data from the second data signal using the recovered clock output from the digital control delay line. A data transmitting and receiving apparatus comprising: a receiver for recovering a clock and data from a data signal; and a transmitter for transmitting data to a transmission clock generated by using the recovered clock,
The receiver
A linear phase detector for detecting a phase difference between a received clock of the first data signal and the recovered clock;
A differential pump for converting the phase difference detected by the linear phase detector into a control voltage;
An analog-to-digital converter for generating said control voltage as a digitally controlled oscillator code;
A first digital controlled oscillator outputting the recovered clock having a frequency of the received clock using the digital controlled oscillator code;
A lock detector for comparing the received clock with the restored clock to output a locking detection signal indicating whether the first digital controlled oscillator is locked;
A selector for outputting the digital control oscillator code when the locking detection signal is output;
A digital control delay line for outputting a recovered clock whose phase is matched to a reception clock of a second data signal when a delay value is set by a digital control oscillator code output from the selector and a second data signal is input; And
And a deserializer for recovering data from the second data signal using the recovered clock output from the digital control delay line. 3. The method of claim 1 or 2, wherein the digital control delay line
A plurality of digital delay cells connected in series and in which the delay value is set by the digitally controlled oscillator code; And
And a trigger for forming a feedback loop of the plurality of digital delay cells when the second data signal is input. 4. The method of claim 3,
A flip-flop receiving the second data signal as a clock terminal;
An inverter coupled to the output of the flip-flop;
A first control end is connected to an output end of the flip flop, a second control end is connected to an output end of the inverter, an input end receives the second data signal, and an output end is connected to a first end of the plurality of digital delay cells A connected first transfer gate; And
A first control end is connected to an output terminal of the inverter, a second control end is connected to an output end of the flip-flop, an input end receives an output of a rearmost end of the plurality of digital delay cells, And a second transfer gate connected to a first stage of the delay cells. 3. The data transmitting and receiving apparatus according to claim 1 or 2, wherein the number of digital delay cells constituting the first digital control oscillator and the number of digital delay lines constituting the digital control delay line are the same. The apparatus of claim 1, further comprising a digital filter coupled between the time-to-digital converter and the first digital control oscillator, for filtering the digitally controlled oscillator code output from the time-to-digital converter. 3. The apparatus of claim 1 or 2, wherein the transmitter
A second digital control oscillator outputting a transmission clock using the digital control oscillator code output from the selector; And
And a serializer for serializing the data using the transmission clock. 8. The method of claim 7,
And a delta-sigma converter connected to the selector and the second digital control oscillator for cumulatively averaging the digital control oscillator codes output from the selector. A receiver for recovering a clock and data from a data signal,
A digital phase detector for detecting a phase difference between a received clock of the first data signal and the recovered clock;
A time-to-digital converter for generating a digitally controlled oscillator code using the phase difference detected by the digital phase detector;
A digital controlled oscillator for outputting the recovered clock having a frequency of the received clock using the digital controlled oscillator code;
A lock detector for comparing the received clock with the recovered clock and outputting a locking detection signal indicating whether the digital controlled oscillator is locked;
A selector for outputting the digital control oscillator code when the locking detection signal is output;
A digital control delay line for outputting a recovered clock whose phase is matched to a reception clock of a second data signal when a delay value is set by a digital control oscillator code output from the selector and a second data signal is input; And
And a deserializer for recovering data from the second data signal using the recovered clock output from the digital control delay line. A receiver for recovering a clock and data from a data signal,
A linear phase detector for detecting a phase difference between a received clock of the first data signal and the recovered clock;
A differential pump for converting the phase difference detected by the linear phase detector into a control voltage;
An analog-to-digital converter for generating said control voltage as a digitally controlled oscillator code;
A digital controlled oscillator for outputting the recovered clock having a frequency of the received clock using the digital controlled oscillator code;
A lock detector for comparing the received clock with the recovered clock and outputting a locking detection signal indicating whether the digital controlled oscillator is locked;
A selector for outputting the digital control oscillator code when the locking detection signal is output;
A digital control delay line for outputting a recovered clock whose phase is matched to a reception clock of a second data signal when a delay value is set by a digital control oscillator code output from the selector and a second data signal is input; And
And a deserializer for recovering data from the second data signal using the recovered clock output from the digital control delay line. 11. The method of claim 9 or 10, wherein the digital control delay line
A plurality of digital delay cells connected in series and in which the delay value is set by the digitally controlled oscillator code; And
And a trigger to form a feedback loop of the plurality of digital delay cells when the second data signal is input. 12. The method of claim 11,
A flip-flop receiving the second data signal as a clock terminal;
An inverter coupled to the output of the flip-flop;
A first control end is connected to an output end of the flip flop, a second control end is connected to an output end of the inverter, an input end receives the second data signal, and an output end is connected to a first end of the plurality of digital delay cells A connected first transfer gate; And
A first control end is connected to an output terminal of the inverter, a second control end is connected to an output end of the flip-flop, an input end receives an output of a rearmost end of the plurality of digital delay cells, And a second transfer gate connected to a first stage of the delay cells. 11. The receiver of claim 9 or 10, wherein the number of digital delay cells constituting the digital control oscillator is equal to the number of digital delay lines constituting the digital control delay line. 10. The receiver of claim 9, further comprising a digital filter coupled between the time-to-digital converter and the digital control oscillator, for filtering the digitally controlled oscillator code output from the time-to-digital converter. 11. The receiver of claim 9 or 10, wherein the first data signal is a main training pattern.

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