KR101665667B1 - Nand flash memory type controlling apparatus - Google Patents

Nand flash memory type controlling apparatus Download PDF

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Publication number
KR101665667B1
KR101665667B1 KR1020150053870A KR20150053870A KR101665667B1 KR 101665667 B1 KR101665667 B1 KR 101665667B1 KR 1020150053870 A KR1020150053870 A KR 1020150053870A KR 20150053870 A KR20150053870 A KR 20150053870A KR 101665667 B1 KR101665667 B1 KR 101665667B1
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KR
South Korea
Prior art keywords
nand flash
nand
control
control logic
mode
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KR1020150053870A
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Korean (ko)
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황태래
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황태래
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

Abstract

The present invention relates to a NAND flash memory control apparatus. According to the present invention, there is provided a computer system including a PC interface for connecting a PC, a NAND slave input / output bus for connecting a NAND flash controller, a NAND host input / output bus for connecting a NAND flash, A slave I / O bus, and a NAND host I / O bus, respectively. The operation mode includes a first operation mode in which the control logic directly controls the NAND flash through the PC interface, a second operation mode in which the control logic directly controls the NAND flash through the NAND host input / output bus, And a third operation mode in which the control logic and the NAND flash controller connected through the NAND slave input / output bus recognize and control the control logic as a NAND flash. According to the present invention, since data of the NAND flash can be confirmed through the PC screen regardless of whether or not the NAND flash is connected, there is an advantage that the NAND flash controller for controlling the NAND flash can be designed more easily.

Description

[0001] NAND FLASH MEMORY TYPE CONTROLLING APPARATUS [0002]

The present invention relates to a NAND flash memory, and more particularly, to a NAND flash memory control apparatus capable of easily checking data stored in a NAND flash through a PC screen or recognizing it as a NAND flash memory by an external NAND flash controller .

Flash memory devices are widely used in various electrical / electronic applications where nonvolatile memory devices are employed. And flash memory devices use one transistor cell as a unit cell, which provides high memory density, high reliability and low power consumption.

Among the above-mentioned flash memory devices, a NAND flash memory (hereinafter, referred to as NAND flash) has an advantage of obtaining a high memory density even at a relatively low cost, that is, low power, low area, This is a widely used memory chip.

However, the above-mentioned advantage is also disadvantageous in that the NAND flash can not be in-place-updated, has a limited number of erasures, and is operated on a page-by-page basis. In particular, NAND flash has a characteristic that read / write units and erase units are different from each other. That is, when the read and write commands are received, the commands are executed page by page through the cache register and the data register, and the erase command is executed block by block. Therefore, if the NAND flash receives a write command, the write operation is performed after all the data of the block is erased. For example, the speed of the write operation depends on the block erase speed and the speed of the write operation. The time (tBER) required for block erase is usually several msec, which is relatively long time (tPROG) Lt; / RTI > Therefore, the time until the entire write operation is completed by the block erase becomes longer.

In this way, the design of the NAND flash controller that makes it possible to control the NAND flash is made more difficult because of the difference between the erase unit and the program unit.

When designing a NAND flash using a NAND flash controller, it is impossible to check information such as data stored in the NAND flash. This is also one of the difficulties to implement the NAND flash controller easily.

Korean Patent No. 10-1102754 (November 30, 2011, NAND flash memory file system and file access method in NAND flash memory system)

It is therefore an object of the present invention to provide a NAND flash memory control apparatus which can more easily design a NAND flash controller for controlling a NAND flash.

That is, the present invention enables the NAND flash controller to be designed while checking the state information of the NAND flash by displaying the data of the NAND flash through the PC screen. In addition, when the NAND flash is not connected, This allows NAND flash controllers to be designed with NAND flash in mind as well.

According to an aspect of the present invention, there is provided a computer system including a PC interface for connecting a PC; NAND slave I / O bus to connect NAND flash controller; NAND host input / output bus connecting NAND flash; And a control logic for controlling the PC interface, the NAND slave I / O bus, and the NAND host I / O bus according to a control operation of the PC, respectively, and operating in an operation mode with each other.

The operation mode includes: a first operation mode in which the control logic directly controls the NAND flash through the PC interface; A second operating mode in which the control logic directly controls the NAND flash through the NAND host input / output bus; And a third operation mode in which the NAND flash controller connected to the control logic and the NAND slave I / O bus recognizes and controls the control logic as a NAND flash.

The control logic transfers data stored in the NAND flash to the PC to display the first and second operation modes.

Wherein the PC is provided with a control program in which the control logic is provided for selectively operating in any one of the first operation mode to the third operation mode; And a RAM memory for storing data of the NAND flash copied by the control logic.

The PC and the control logic perform control operations with different control signals.

Wherein the PC is a PC control signal, the control logic is a NAND control signal, the control logic converts the PC control signal into the NAND control signal to control the NAND flash, And transmits the NAND control signal to the PC.

The NAND flash memory controller according to the present invention has the following effects.

The present invention provides a control device for connecting a PC, a NAND flash controller, and a NAND flash, and operates in three operation modes in which a NAND flash can be accessed according to a series of control operations.

In other words, the NAND host mode in which the PC directly controls the NAND flash to receive and display the data of the NAND flash, and when the NAND flash is not connected, the NAND flash controller recognizes the control device like a NAND flash NAND Slave Mode for checking information and NAND Direct Mode for monitoring the communication between the NAND flash controller and the NAND flash while transmitting data stored in the NAND flash to the PC and displaying the data on the screen.

Therefore, the present invention has the effect of allowing the user to directly check the contents of the NAND flash, thereby easily designing the NAND flash controller provided to realize the NAND flash.

Furthermore, since the NAND flash can be virtually recognized by mimicking various status information of the NAND flash even when the NAND flash is not connected as described above, it is possible to perform the design implementation method of the NAND flash controller more efficiently Can be expected.

FIG. 1 is a block diagram illustrating a NAND flash memory control apparatus according to a preferred embodiment of the present invention.
2 is a block diagram of a NAND flash memory control apparatus when operating in a NAND host mode
Figure 3 is a flow chart illustrating the NAND host mode of Figure 2;
FIG. 4 is a block diagram of the NAND flash memory control apparatus when operating in the NAND slave mode
5 is a flowchart illustrating the NAND slave mode of FIG.
6 is a configuration diagram of the NAND flash memory control apparatus when operating in the NAND direct mode
FIG. 7 is a flowchart illustrating the NAND direct mode of FIG.

The present invention relates to designing a NAND flash controller while checking data of a NAND flash memory device as a flash memory device and designing a NAND flash controller through an emulation function even when the NAND flash is not connected. .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a NAND flash memory control device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an NAND flash memory control apparatus according to a preferred embodiment of the present invention. Hereinafter, a NAND flash memory controller will be referred to as a 'controller' 100.

Referring to FIG. 1, the control device 100 controls the NAND flash 170 (or the NAND flash) 170 according to a PC control operation in a state that a PC (or host) 150, a NAND flash controller 160 and at least one NAND flash 170 To allow the user to check the data on the PC screen as a basic operation. In the present invention, when the NAND flash 170 is not connected, the controller 100 itself is virtually recognized by the NAND flash 170 through an emulation function, thereby designing the NAND flash controller 160.

The configuration of the control apparatus 100 will be described in detail.

A control logic (Control Logic) 110 is configured in the control device 100. The control logic 110 functions to control the operation of the control device 100 as a whole. Particularly, the operation of the control device 100 can be operated in three operation modes through the control operation of the PC 150 do. The three operation modes may be classified into a first operation mode to a third operation mode. Each operation mode may be a NAND host mode, a NAND slave mode, a NAND direct mode, . The NAND host mode (or 'first mode') is a mode in which the PC 150 directly controls the NAND flash 170 to receive data of the NAND flash 170 and displays the data on the screen. The NAND slave mode (or 'second mode') is a mode for allowing the NAND flash controller 160 to recognize the controller 100 as a virtual NAND flash. In this mode, the NAND flash 170 may be unconnected to the controller 100. The control logic 100 controls the communication between the NAND flash controller 160 and the NAND flash 170 in the state where the NAND flash controller 160 and the NAND flash 170 are directly connected to each other, And transmits the data of the NAND flash memory 170 to the PC 150 to display the data on the screen.

The control device 100 is connected through a series of connection media corresponding to the PC 150, the NAND flash controller 160, and the NAND flash 170, respectively.

The PC interface 120 is responsible for the connection between the control device 100 and the PC 150. [ The PC interface 120 is designed to transmit and receive control commands, address signals, and data signals between the control logic 110 and the PC 150. At this time, various methods such as USB, peripheral component interconnect (PCI), PCIe (PCI Ecpress) and ThunderBold may be applied to the PC interface 120. Of course, a method of connecting external devices such as the PC 150 and the control device 100 may be a method capable of transmitting / receiving control / address / data signals and the like, so that the connection method is not necessarily limited.

The connection between the controller 100 and the NAND flash controller 160 is performed by a NAND slave I / O bus 130. The NAND slave input / output bus 130 is an interface for providing an emulation function such that the control device 100 is recognized as a NAND flash.

The connection between the controller 100 and the NAND flash 170 is controlled by a NAND host I / O bus 140. The NAND host input / output bus 140 is an interface for allowing the NAND flash controller 160 to control the NAND flash 170 by transmitting a NAND control signal to the NAND flash 170.

As described above, the NAND slave input / output bus 130 is a NAND interface that allows the control logic 110 to receive the NAND control signal from the NAND flash controller 160 and emulate the NAND control signal into the NAND flash. The NAND host input / output bus 140 is connected to the NAND interface 170 which allows the NAND flash controller 160 to directly control the NAND flash 170 by transferring the NAND control signal directly to the NAND flash 170. [ to be. Here, the NAND slave mode and the NAND direct mode, which are performed through the respective input / output buses 130 and 140, are performed by the NAND control signal. The NAND control signal refers to a combination of an instruction, an address and a data. The type of the NAND control signal is a combination of 'READ', 'PROGRAM', 'ERASE', 'COPY BACK', 'READ STATUS', 'READ BUFFER' NAND control created with the user's specific intentions, 'RESET', 'READ ID', 'SET FEATURE', 'GET FEATURE', 'READ PARAMETER PAGE', 'MULTI-PLANE OPERATION' And a 'USER DEFINITION CMD' signal.

The PC 150 performs a function of controlling the control device 100 to operate in any one of the first to third operation modes. To this end, the PC 150 may be provided with a control program 160 for selecting an operation mode. The control program 160 is stored in a storage medium such as a memory provided in the PC 150. Accordingly, the user can select one operation mode through the control program 160 and can drive the control apparatus 100 according to the selected operation mode. The PC 150 also displays data stored in the NAND flash memory 170 on the PC screen according to the operation mode. The PC 150 is also provided with a RAM memory 154 as another memory device. The RAM memory 154 stores data to be copied from the NAND flash memory 170 according to the operation mode. The stored data is displayed on the screen according to the PC operation.

Next, the operation of each of the operation modes performed according to the control operation of the control device and the PC having the above-described configuration will be described with reference to FIG. 1 and the related drawings.

First, the first mode is the NAND host mode.

The NAND host mode is a case where the PC 150 and the NAND flash 170 form a data transmission path directly as shown in FIG. 2, and the operation thereof is described with reference to FIG.

The user selects the NAND host mode using the control program 152 stored in the PC. Then, the control device 100 connected to the PC 150 transitions to the initial state for operating in the NAND host mode (S200).

If a PC control signal is generated from the PC 150 in this state, the PC control signal is transmitted to the control logic 110 through the PC interface 120 (S202). At this time, the PC control signal refers to a signal transmitted / received between the PC 150 and the control device 100. And the PC control signal is different from the signal form used in the controller 100. [ That is, the control device 100 can not access the NAND flash 170 using the PC signal.

Accordingly, the control logic 110 converts the PC control signal into a NAND control signal capable of controlling the NAND flash 170 (S204). The control logic 110 transfers the converted NAND control signal to the NAND host input / output bus 140 to directly access and control the NAND flash 170 (S206). The control operation performed by the control logic 110 includes checking whether data is present in the NAND flash memory 170. [ If there is data in the NAND flash memory 170, the data stored in the NAND flash memory 170 is accessed by the NAND control signal (S208). The accessed data is transferred to the control logic 110 via the NAND host input / output bus 140 and transferred to the PC 150 through the PC interface 120 (S210).

Then, the PC 150 stores the data transferred from the controller 100 in the RAM memory 154 and displays the data on the screen (S212).

Accordingly, the user can confirm the data stored in the NAND flash memory 170 through the PC screen. If there is no data stored in the NAND flash memory 170 in step 208, there is no data to be transmitted to the PC 150, so that the PC 150 displays a related message on the screen or terminates the system. An example of the guidance message may be a message for instructing the status information of the NAND flash 170 or asking for execution of switching to another operation mode (for example, NAND slave mode or NAND direct mode).

The NAND host mode controls the control logic 110 between the PC 150 and the NAND flash 170 to transfer the data of the NAND flash 170 to the PC 150.

The second mode is the NAND slave mode, which is the second mode.

4, when the PC 150 and the NAND flash controller 160 form a direct data transmission / reception path, the NAND flash controller 160 transmits the control device 100 as the NAND flash 170 Fig. 5 is a flowchart illustrating an operation of the present invention.

The user selects a NAND slave mode in which the control device 100 can be emulated as a virtual NAND flash by using the control program 152 stored in the PC 150. [ According to the selection operation, the PC 150 and the control apparatus 100 transition to the initial state for operating in the NAND slave mode (S300).

In the initial state, the control logic 110 of the control device 100 receives the NAND control signal from the NAND flash controller 160 through the NAND slave input / output bus 130 (S302). At this time, since the NAND flash 170 is not connected to the controller, the control logic 110 virtually receives the NAND control signal emulating the operation state information of the NAND flash 170 and the like.

The control logic 110 converts the NAND control signal into a PC control signal and transmits it to the PC 150 via the PC interface 120 (S304).

In step 306, the control logic 110 transfers the data received from the PC 150 to the NAND flash controller 160 when there is data corresponding to the control signal in the PC 150 (S308). On the other hand, if there is no data, the guidance message is displayed on the screen or the system is terminated like the first mode.

The NAND slave mode is a mode in which the NAND flash controller 10 recognizes the controller 100 as the NAND flash 170 in a state where the NAND flash 170 is not connected to the controller 100, .

Third, the third mode is NAND Direct Mode.

In the NAND direct mode, as shown in FIG. 6, the NAND flash 170 and the NAND flash controller 160 are directly connected, and the control logic 110 transfers the data of the NAND flash 170 to the PC 150 Mode, which operation refers to Fig.

The user selects the NAND direct mode using the control program 152 stored in the PC 150. [ In response to the selection operation, the controller 100 transitions to the initial state for operating in the NAND direct mode (S400).

In the initial state, the control logic 110 receives the NAND control signal from the NAND flash controller 160 through the NAND slave I / O bus 130 (S402).

The control logic 110 transfers the NAND control signal to the NAND flash 170 through the NAND host input / output bus 140 to control the NAND flash 170 (S404). At the same time, the control logic 110 converts the NAND control signal into a PC control signal, and then transmits the PC control signal to the PC 150 through the PC interface 120 (S406). That is, the control logic 110 monitors the inter-NAND flash controller 160 and the NAND flash 170, and checks whether there is data in the NAND flash 170 as a result of the monitoring (S408).

If there is data in the NAND flash memory 170, the control logic 110 transfers the data to the PC 150 via the PC interface 120 (S410), and the PC 150 displays the data (S412). Of course, if there is no data, the control logic 110 causes the guide message to be displayed or the system is terminated such as the first mode and the second mode.

The NAND direct mode is a mode in which the control logic 110 monitors the communication between the NAND flash 170 and the NAND flash controller 160 and transmits the data of the NAND flash 170 to the PC 150 according to the monitoring result to be. Through this, NAND flash controller is designed.

As described above, the present embodiment can design the NAND flash controller while checking the status information or data of the NAND flash connected to the control device directly through the PC screen. Even if the NAND flash is not connected, the control device is recognized as a NAND flash And to provide a technical point of view.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It will be apparent that modifications, variations and equivalents of other embodiments are possible. Therefore, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: NAND flash memory control device
120: PCI interface 130: NAND slave input / output bus
140: NAND host input / output bus 150: PC
152: control program 154: RAM memory
160: NAND flash controller 170: NAND flash

Claims (6)

A PC interface for connecting a PC;
NAND slave I / O bus to connect NAND flash controller;
NAND host input / output bus connecting NAND flash; And
And control logic for controlling the PC interface, the NAND slave input / output bus, and the NAND host input / output bus in accordance with a control operation of the PC, respectively, and operating in an operation mode with respect to each other. The method according to claim 1,
The operation mode includes:
A first operating mode in which the control logic directly controls the NAND flash through the PC interface;
A second operating mode in which the control logic directly controls the NAND flash through the NAND host input / output bus; And
And a third operation mode in which the NAND flash controller connected to the control logic and the NAND slave I / O bus recognizes and controls the control logic as a NAND flash. 3. The method of claim 2,
Wherein the first operation mode and the second operation mode include:
Wherein the control logic transfers data stored in the NAND flash to the PC and displays the data on the screen. 3. The method of claim 2,
In the PC,
Wherein the control logic is provided for selectively operating in one of the first operation mode to the third operation mode; And
And a RAM memory for storing data of the NAND flash copied by the control logic. 5. The method of claim 4,
Wherein the PC and the control logic perform control operations with different control signals. 6. The method of claim 5,
Wherein the PC is a PC control signal, the control logic is a NAND control signal,
Wherein the control logic controls the NAND flash by converting the PC control signal into the NAND control signal,
Wherein the control logic converts the NAND control signal transferred from the NAND flash controller into the PC control signal and transfers the converted PC control signal to the PC.
KR1020150053870A 2015-04-16 2015-04-16 Nand flash memory type controlling apparatus KR101665667B1 (en)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
KR20050078206A (en) * 2004-01-30 2005-08-04 삼성전자주식회사 Volatile memory device for buffering between non-volatile memory and host, multi-chip packaged semiconductor device and apparatus for processing data using the same
JP2007272635A (en) * 2006-03-31 2007-10-18 Toshiba Corp Memory system and controller
US20110107076A1 (en) * 2006-05-25 2011-05-05 Samsung Electronics Co., Ltd. System comprising electronic device and external device storing boot code for booting system
KR101102754B1 (en) 2005-02-28 2012-01-05 삼성전자주식회사 Nand flash memory file system and method for accessing file thereof
KR20120010698A (en) * 2010-07-27 2012-02-06 주식회사 셀픽 Solid state disk using multi channel cache and method for storing cache data using it

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050078206A (en) * 2004-01-30 2005-08-04 삼성전자주식회사 Volatile memory device for buffering between non-volatile memory and host, multi-chip packaged semiconductor device and apparatus for processing data using the same
KR101102754B1 (en) 2005-02-28 2012-01-05 삼성전자주식회사 Nand flash memory file system and method for accessing file thereof
JP2007272635A (en) * 2006-03-31 2007-10-18 Toshiba Corp Memory system and controller
US20110107076A1 (en) * 2006-05-25 2011-05-05 Samsung Electronics Co., Ltd. System comprising electronic device and external device storing boot code for booting system
KR20120010698A (en) * 2010-07-27 2012-02-06 주식회사 셀픽 Solid state disk using multi channel cache and method for storing cache data using it

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