KR101649238B1 - Level shifter - Google Patents

Abstract

The present invention relates to a level shifter capable of normally performing a turn-off operation of a pull-down switching device by preventing a leakage current, comprising: a high potential supply unit for supplying a high potential voltage from the outside to an output terminal; A first clock transmission line for transmitting a first clock pulse; A second clock transmission line for transmitting a second clock pulse having an inverted phase with respect to the first clock pulse; And a pull-down switching element which is turned on / off according to a first clock pulse from the first clock transmission line and connects the output terminal and the second clock transmission line when turned on .

Description

Level Shifter {LEVEL SHIFTER}

The present invention relates to a level shifter, and more particularly, to a level shifter capable of normally performing a turn-off operation of a pull-down switching device by preventing a leakage current.

The level shifter shifts the level of the input signal by raising the high level of the input signal by using the high potential voltage and lowering the low level of the input signal by using the low potential voltage.

Generally, the voltage of the gate electrode and the source electrode of the pulldown switching element maintains the same potential during the turn-off operation of the pull-down switching device provided in the level shifter. That is, by maintaining the gate-source electrode voltage of this pull-down switching device at 0 [V], this pull-down switching device is turned off. However, when the pull-down switching element is deteriorated, the threshold voltage of the pull-down switching element shifts, and a leakage current is generated even when the gate-source electrode voltage of the switching element is maintained at 0 [V]. Due to such a leakage current, the pull-down switching device can not be completely turned off. As a result, the voltage of the output terminal can not be maintained in a high state, and a normal level shifting operation can not be performed.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a plasma display panel in which clock pulses having phases opposite to each other are supplied to a gate electrode and a source electrode of a pulldown switching element, So that the leakage current of the pull-down switching device can be prevented by keeping the inter-electrode voltage always negative.

According to an aspect of the present invention, there is provided a level shifter including: a high potential supply unit for supplying a high potential voltage from the outside to an output terminal; A first clock transmission line for transmitting a first clock pulse; A second clock transmission line for transmitting a second clock pulse having an inverted phase with respect to the first clock pulse; And a pull-down switching element which is turned on / off according to a first clock pulse from the first clock transmission line and connects the output terminal and the second clock transmission line when turned on to

The high-potential supply unit may include a first switching device that is turned on / off according to the high-potential voltage, and connects the high-potential transmission line and the node to each other to transmit the high- A second switching element which is turned on / off according to a signal state of the node and connects the high-potential transmission line and the output terminal to each other when turned on; And a capacitor connected between the node and the output terminal.

And the area of each of the first and second switching elements is smaller than the area of the pull-down switching element.

According to another aspect of the present invention, there is provided a level shifter including: a first high potential supply unit for supplying a first high potential voltage from the outside to a first output terminal; A second high potential supply unit for supplying a second high potential voltage from the outside to the second output terminal; A third high potential supply unit for supplying a first high potential voltage from the outside to the third output terminal; A fourth high potential supply unit for supplying a second high potential voltage from the outside to the fourth output terminal; A first clock transmission line for transmitting a first clock pulse; A second clock transmission line for transmitting a second clock pulse having an inverted phase with respect to the first clock pulse; A first pull-down switching element which is turned on / off according to a first clock pulse from the first clock transmission line and connects the first output terminal and the second clock transmission line to each other when the first switch is turned on; A second pull-down switching element for controlling the turn-on / off of the first output terminal in accordance with a signal state from the first output terminal and connecting the first output terminal and the second clock transmission line to each other; A third pull-down switching element that is turned on / off according to a second clock signal from the second clock transmission line and connects the third output terminal and the first clock transmission line to each other when turned on; And a fourth pull-down switching element that is turned on / off according to a signal state of the third output terminal and connects the fourth output terminal and the first output terminal when turned on. do.

The first high-potential supply unit may be turned on / off according to the first high-potential voltage. The first high-potential supply unit may connect the first high-potential transmission line, which transmits the first high- A first switching device for switching the first switching device; A second switching element which is turned on / off according to a signal state of the first node and connects the high-potential transmission line and the first output terminal to each other when the first node is turned on; And a first capacitor connected between the first node and the first output terminal.

The second high-potential supply unit is controlled to turn on / off according to the second high-potential voltage, and when the second high-potential supply unit turns on the second high-potential transmission line and transmits the second high- A third switching element; A fourth switching element for controlling the turn-on / off of the second node in accordance with the signal state of the second node and for connecting the second high-potential transmission line and the second output terminal to each other; And a second capacitor connected between the second node and the second output terminal.

The third high-potential supply unit may include a fifth switching device that is turned on / off according to the first high-potential voltage and turns on the first high-potential transmission line and the third node when the first high-potential supply line is turned on; A sixth switching element for controlling the turn-on / off of the third node in accordance with a signal state of the third node and connecting the first high-potential transmission line and the third output terminal to each other; And a third capacitor connected between the third node and the third output terminal.

The seventh high potential supply unit may include a seventh switching device that is turned on / off according to the second high potential voltage and connects the second high potential transmission line and the fourth node to each other when the first high potential supply unit is turned on; An eighth switching element for controlling the turn-on / off of the fourth node in accordance with the signal state of the fourth node and for connecting the second high-potential transmission line and the fourth output terminal to each other; And a fourth capacitor connected between the fourth node and the fourth output terminal.

The areas of each of the first to fourth pulldown switching elements are equal to each other; The areas of the first to eighth switching elements are equal to each other; And the area of each of the first to fourth pulldown switching elements is larger than the area of each of the first to eighth switching elements.

And the second high potential voltage is larger than the first high potential voltage.

The level shifter according to the present invention has the following effects.

In the present invention, clock pulses having phases opposite to each other are supplied to the gate electrode and the source electrode of the pull-down switching device, so that the voltage between the gate and the source of the pull-down switching device is always kept negative during the turn- Leakage current of the switching element can be prevented.

1 is a view showing a level shifter according to a first embodiment of the present invention;
FIG. 2 is a timing chart of various signals supplied to the level shifter of FIG. 1; FIG.
3 is a view illustrating a level shifter according to a second embodiment of the present invention;
4 is a timing chart of various signals supplied to the level shifter of FIG. 3; FIG.
5 is a view for explaining the effect of the present invention

1st Example

1 is a view illustrating a level shifter according to a first embodiment of the present invention.

1, the level shifter according to the first embodiment of the present invention includes a high potential supply unit HS for supplying a high potential voltage VDD from the outside to the output terminal OT, A second clock transmission line for transmitting a second clock pulse Vin_b having a phase inverted with respect to the first clock pulse Vin_a and a second clock transmission line for transmitting a second clock pulse Vin_a, Tr_PD). The pull-down switching device Tr_PD is controlled to be turned on / off according to a first clock pulse Vin_a from the first clock transmission line, and is connected to the output terminal OT and the second clock transmission line Connect each other.

The high potential supply section HS includes a first switching device Tr1, a second switching device Tr2, and a capacitor C.

The first switching element Tr1 is controlled to turn on / off according to a high-potential voltage (VDD) from a high-potential transmission line, and includes a high-potential transmission line for transmitting the high- (N).

The second switching device Tr2 is turned on / off according to the signal state of the node N, and connects the high potential transmission line and the output terminal OT to each other when turned on.

The capacitor C is connected between the node N and the output terminal OT.

The operation of the level shifter according to the first embodiment of the present invention will now be described.

2 is a timing chart of various signals supplied to the level shifter of FIG.

First, the operation of the level shifter when the first clock pulse Vin_a is supplied to the gate electrode of the pull-down switching device Tr_PD and the second clock pulse Vin_b is supplied to the source electrode will be described.

The first clock pulse Vin_a is inverted by 180 degrees with respect to the second clock pulse Vin_b so that the second clock pulse Vin_b maintains the high voltage while the first clock pulse Vin_a is maintained at the high voltage, ≪ / RTI > When this first clock pulse Vin_a is held at a high voltage and the second clock pulse Vin_b is held at a low voltage, the pulldown switching element Tr_PD is turned on. Then, the second clock pulse Vin_b held at the low voltage through the turn-on pull-down switching device Tr_PD is supplied to the output terminal OT, and the output terminal OT is discharged. At this time, the output terminal OT is also supplied with the high-potential voltage VDD transmitted by the first and second switching elements Tr2, and the area of the pull-down switching element Tr_PD is the same as that of the first and second switching elements Tr2, (Tr1, Tr2), the output terminal OT is maintained in the discharged state by the second clock pulse Vin_b of the low voltage supplied by the pull-down switching device Tr_PD having a larger area. However, the voltage of the output terminal OT is not completely lowered to the low voltage level of the second clock pulse Vin_b due to the influence of the turned-on first and second switching elements Tr1 and Tr2. Therefore, when the first clock pulse Vin_a of high voltage is supplied to the gate electrode of the pull-down switching device Tr_PD and the second clock pulse Vin_b of the low voltage is supplied to the source electrode thereof, And outputs a voltage.

On the other hand, when the first clock pulse Vin_a of the low voltage is supplied to the gate electrode of the pull-down switching device Tr_PD and the second clock pulse Vin_b of the high voltage is supplied to the source electrode thereof, Tr_PD) is turned off. Then, the high-potential voltage VDD is supplied to the output terminal OT through the turned-on first and second switching elements Tr2. Therefore, when the first clock pulse Vin_a of the low voltage is supplied to the gate electrode of the pull-down switching device Tr_PD and the second clock pulse Vin_b of the high voltage is supplied to the source electrode thereof, And outputs a high voltage.

2 is supplied to the gate electrode of the pull-down switching device Tr_PD and a second clock pulse Vin_b as shown in Fig. 2 is applied to the source electrode When supplied, this level shifter generates a level-shifted output to the same level as Output A of FIG. That is, the level shifter receives the second clock pulse Vin_b as an input, and level-shifts the second clock pulse Vin_b in the form of Output A.

On the other hand, when the second clock pulse Vin_b is supplied to the gate electrode of the pull-down switching device Tr_PD and the first clock pulse Vin_a is supplied to the source electrode thereof, Lt; / RTI > That is, the level shifter receives the first clock pulse Vin_a as an input, and level-shifts the first clock pulse Vin_a in the form of Output B.

Second Example

3 is a view illustrating a level shifter according to a second embodiment of the present invention.

3, the level shifter according to the second embodiment of the present invention includes a first high potential supply unit HS1 for supplying a first high potential voltage VDD1 from the outside to a first output terminal OT1, A second high potential supply unit HS2 for supplying a second high potential voltage VDD2 from the outside to the second output terminal OT2 and a second high potential supply unit HS2 for supplying a first high potential voltage VDD1 from the outside to the third output terminal OT2, A fourth high potential supply unit HS4 for supplying the second high potential voltage VDD2 from the outside to the fourth output terminal OT4, A first clock transmission line for transmitting a first clock pulse Vin_a and a second clock transmission line for transmitting a second clock pulse Vin_b having an inverted phase relative to the first clock pulse Vin_a, To fourth pull-down switching elements Tr_PD.

The first pull-down switching device Tr_PD is controlled to be turned on / off according to a first clock pulse Vin_a from the first clock transmission line and is turned on when the first output terminal OT1 and the second clock Connect the transmission lines to each other.

The second pull-down switching device Tr_PD is controlled to be turned on / off according to a signal state from the first output terminal OT1 and is turned on when the second output terminal OT2 and the third output terminal OT3 ).

The third pull-down switching device Tr_PD is controlled to be turned on / off according to a second clock signal from the second clock transmission line. When the third pull-down switching device Tr_PD turns on the third output terminal OT3 and the first clock transmission line Connect each other.

The fourth pull-down switching device Tr_PD is turned on / off according to the signal state of the third output terminal OT3 and is turned on when the fourth output terminal OT4 and the first output terminal OT1 are turned on, .

The first high potential supply unit HS1 includes a first switching device Tr1, a second switching device Tr2, and a first capacitor C1.

The first switching element Tr1 is controlled to turn on / off according to the first high potential voltage VDD1 and is connected to the first high potential transmission line for transmitting the first high potential voltage VDD1 at turn- One node N1 are connected to each other.

The second switching device Tr2 is turned on / off according to the signal state of the first node N1 and connects the high potential transmission line and the first output terminal OT1 to each other when the first node N1 is turned on.

The first capacitor C1 is connected between the first node N1 and the first output terminal OT1.

The second high potential supply section HS2 includes a third switching device Tr3, a fourth switching device Tr4, and a second capacitor C2.

The third switching device Tr3 is controlled to turn on / off according to the second high potential voltage VDD2. The third switching device Tr3 includes a second high potential transmission line for transmitting the second high potential voltage VDD2 at turn- Two nodes N2 are connected to each other.

The fourth switching device Tr4 is turned on / off according to the signal state of the second node N2, and connects the second high-potential transmission line and the second output terminal OT2 to each other at turn-on.

The second capacitor C2 is connected between the second node N2 and the second output terminal OT2.

The third high potential supply unit HS3 includes a fifth switching device Tr5, a sixth switching device Tr6, and a third capacitor C3.

The fifth switching element Tr5 is turned on / off according to the first high potential voltage VDD1 and connects the first high potential transmission line and the third node N3 to each other at turn-on.

The sixth switching element Tr6 is turned on / off according to the signal state of the third node N3 and connects the first high-potential transmission line and the third output terminal OT3 to each other at the turn-on time .

The third capacitor C3 is connected between the third node N3 and the third output terminal OT3.

The fourth high potential supply unit HS4 includes a seventh switching device Tr7, an eighth switching device Tr8, and a fourth capacitor C4.

The seventh switching device Tr7 is turned on / off according to the second high voltage VDD2 and connects the second high potential transmission line and the fourth node N4 to each other at turn-on.

The eighth switching element Tr8 is turned on / off according to the signal state of the fourth node N4, and connects the second high-potential transmission line and the fourth output terminal OT4 to each other at turn-on.

The fourth capacitor C4 is connected between the fourth node N4 and the fourth output terminal OT4.

The areas of the first pull-down switching element and the third pull-down switching element are the same, and the areas of the second pull-down switching element and the fourth pull-down switching element are the same. It is also preferable that the first and fifth switching elements have the same area, the second switching element and the sixth switching element have the same area, the third switching element and the seventh switching element have the same area, The area of the switching element and the area of the eighth switching element are the same.

At this time, the area of each of the first to fourth pulldown switching elements Tr_PD is larger than the area of each of the first to eighth switching elements Tr8. For example, the area of the first pull-down switching device Tr_PD is larger than the area of the first switching device Tr1.

The operation of the level shifter according to the second embodiment of the present invention will now be described.

4 is a timing chart of various signals supplied to the level shifter of FIG. 3. FIG.

First, a first clock pulse Vin_a is supplied to the gate electrode of the first pull-down switching device Tr_PD, a second clock pulse Vin_b is supplied to the source electrode of the first pull-down switching device Tr_PD, When the second clock pulse Vin_b is supplied to the gate electrode of the third pull-down switching device Tr_PD and the first clock pulse Vin_a is supplied to the source electrode of the third pulldown switching device Tr_PD, Will be described.

The first clock pulse Vin_a is inverted by 180 degrees with respect to the second clock pulse Vin_b so that the second clock pulse Vin_b maintains the high voltage while the first clock pulse Vin_a is maintained at the high voltage, ≪ / RTI > When the first clock pulse Vin_a is held at a high voltage and the second clock pulse Vin_b is held at a low voltage, the first pull-down switching device Tr_PD is turned on while the third pulldown switching device (Tr_PD) is turned off. Then, a second clock pulse Vin_b, which is held at a low voltage through the turned-on first pull-down switching device Tr_PD, is supplied to the first output terminal OT1, and the first output terminal OT1 is discharged do. Output A in Fig. 4 shows the waveform of the voltage output from this first output terminal OT1. Then, the second pull-down switching device Tr_PD connected to the first output terminal OT1 through the gate electrode is turned off. Accordingly, the second output terminal OT2 is charged by the second high-potential voltage VDD2 supplied by the turned-on third and fourth switching devices Tr4. That is, the second output terminal OT2 is the output terminal OT of the first level shifter LS1, and a high voltage is outputted through the second output terminal OT2. Output B in Fig. 4 shows the waveform of the voltage output from this second output terminal OT2.

On the other hand, as described above, since the third pull-down switching device Tr_PD is turned off, the third output terminal OT3 is turned on at the first high potential (Vs) supplied by the fifth and sixth switching elements Tr6 turned on And is charged by the voltage VDD1. Output C in Fig. 4 shows the waveform of the voltage output from this third output terminal OT3. Thus, the fourth pull-down switching device Tr_PD connected to the charged third output terminal OT3 through the gate electrode is turned on. As the fourth pull-down switching device Tr_PD is turned on, the fourth output terminal OT4 is discharged by the second clock pulse Vin_b of the low voltage. That is, the fourth output terminal OT4 is the output terminal OT of the second level shifter LS2, and a low voltage is outputted through the fourth output terminal OT4. Output D in Fig. 4 shows the waveform of the voltage output from this fourth output terminal OT4.

That is, the first level shifter LS1 receives the first clock pulse Vin_a as an input, and level-shifts the first clock pulse Vin_a in the form of Output B. On the other hand, the second level shifter LS2 receives the second clock pulse Vin_b as an input, and level-shifts the second clock pulse Vin_b in the same manner as Output D.

On the other hand, the second clock pulse Vin_b is supplied to the gate electrode of the first pull-down switching device Tr_PD, the first clock pulse Vin_a is supplied to the source electrode of the first pull-down switching device Tr_PD, When the first clock pulse Vin_a is supplied to the gate electrode of the third pull-down switching device Tr_PD and the second clock pulse Vin_b is supplied to the source electrode of the third pull-down switching device Tr_PD, A voltage having the same waveform as the output B is generated at the first output terminal OT1 and a voltage having the same waveform as the output D of FIG. 4 is generated at the second output terminal OT2, A voltage is generated at the third output terminal OT3, and a voltage of the waveform like Output C of Fig. 4 is generated at the fourth output terminal OT4.

That is, the first level shifter LS1 receives the second clock pulse Vin_b as an input, and level-shifts the second clock pulse Vin_b in the same manner as Output D. On the other hand, the second level shifter LS2 receives the first clock pulse Vin_a as an input, and level-shifts the first clock pulse Vin_a in the same manner as Output C.

According to the first and second embodiments of the present invention, clock pulses of opposite phases are always supplied to the gate electrode and the source electrode of each pull-down switching device Tr_PD. Therefore, the gate-source electrode voltage of the pull-down switching device Tr_PD is always kept negative during the turn-off operation of the pull-down switching device Tr_PD. Therefore, in the present invention, even when the threshold voltage of the pull-down switching device Tr_PD is shifted, the pull-down switching device Tr_PD can surely maintain the turn-off state.

FIG. 5 is a diagram for explaining the effect of the present invention. As shown in FIG. 5, the output (Out_A) of the conventional level shifter with respect to the input maintains a high voltage lower than normal, It can be seen that the output (Out_B) of the shifter maintains a normal high voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

HS: High potential supply Tr_PD: Pulldown switching element
Tr1: first switching element Tr2: second switching element
N: node C: capacitor
OT: Output terminal Vin_a: 1st clock pulse
Vin_b: Second clock pulse

Claims (10)

A high potential supply unit for supplying a high potential voltage from the outside to the output terminal;
A first clock transmission line for transmitting a first clock pulse;
A second clock transmission line for transmitting a second clock pulse having an inverted phase with respect to the first clock pulse; And
And a pull-down switching element that is turned on / off according to a first clock pulse from the first clock transmission line and connects the output terminal and the second clock transmission line to each other when turned on,
The high-
A first switching element that is turned on / off according to the high-potential voltage and connects the node with the high-potential transmission line that transmits the high-potential voltage when the first switching element is turned on;
A second switching element which is turned on / off according to a signal state of the node, and connects the high-potential transmission line and the output terminal to each other when turned on; And
And a capacitor connected between the node and the output terminal. delete The method according to claim 1,
And the area of each of the first and second switching elements is smaller than the area of the pull-down switching element. A first high potential supply unit for supplying a first high potential voltage from the outside to the first output terminal;
A second high potential supply unit for supplying a second high potential voltage from the outside to the second output terminal;
A third high potential supply unit for supplying a first high potential voltage from the outside to the third output terminal;
A fourth high potential supply unit for supplying a second high potential voltage from the outside to the fourth output terminal;
A first clock transmission line for transmitting a first clock pulse;
A second clock transmission line for transmitting a second clock pulse having an inverted phase with respect to the first clock pulse;
A first pull-down switching element which is turned on / off according to a first clock pulse from the first clock transmission line and connects the first output terminal and the second clock transmission line to each other when the first switch is turned on;
A second pull-down switching element that turns on / off according to a signal state from the first output terminal and connects the second output terminal and the third output terminal to each other when turned on;
A third pull-down switching element that is turned on / off according to a second clock signal from the second clock transmission line, and connects the third output terminal and the first clock transmission line to each other when turned on; And
And a fourth pull-down switching element that is turned on / off according to the signal state of the third output terminal and connects the fourth output terminal and the first output terminal to each other when the first switch is turned on. 5. The method of claim 4,
Wherein the first high potential supply portion includes:
A first switching element that is turned on / off according to the first high potential voltage and connects the first high potential transmission line and the first node transmitting the first high potential voltage when the first high potential voltage is turned on;
A second switching element that is turned on / off according to a signal state of the first node and connects the first high potential transmission line and the first output terminal to each other when the first node is turned on; And
And a first capacitor connected between the first node and the first output terminal. 6. The method of claim 5,
The second high potential supply unit includes:
A third switching element that is turned on / off according to the second high-potential voltage and connects the second high-potential transmission line transmitting the second high-potential voltage to the second node when the first high-voltage transmission line is turned on;
A fourth switching element for controlling the turn-on / off of the second node in accordance with the signal state of the second node and for connecting the second high-potential transmission line and the second output terminal to each other; And
And a second capacitor connected between the second node and the second output terminal. The method according to claim 6,
The third high potential supply unit may include:
A fifth switching element that is turned on / off according to the first high potential voltage and connects the first high potential transmission line and the third node to each other when the first high potential transmission line is turned on;
A sixth switching element for controlling the turn-on / off of the third node in accordance with a signal state of the third node and connecting the first high-potential transmission line and the third output terminal to each other; And
And a third capacitor connected between the third node and the third output terminal. 8. The method of claim 7,
The fourth high potential supply unit supplies,
A seventh switching element for turning on / off the first high-potential transmission line and the fourth node when the first high-potential transmission line is turned on;
An eighth switching element for controlling the turn-on / off of the fourth node in accordance with the signal state of the fourth node and for connecting the second high-potential transmission line and the fourth output terminal to each other; And
And a fourth capacitor connected between the fourth node and the fourth output terminal. 9. The method of claim 8,
The first pull-down switching element and the third pull-down switching element have the same area;
The second pull-down switching element and the fourth pull-down switching element have the same area;
The area of the first switching element and the area of the fifth switching element are the same;
The area of the second switching element and that of the sixth switching element are the same;
The third switching element and the seventh switching element have the same area;
The fourth switching element and the eighth switching element have the same area; And,
Wherein the area of each of the first to fourth pulldown switching elements is larger than the area of each of the first to eighth switching elements. 5. The method of claim 4,
A level shifter having a second higher potential voltage than the first higher potential voltage.

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