KR101626032B1 - Method and system for splitting wafer - Google Patents

Abstract

The present invention relates to a wafer segmentation method and a wafer segmentation system. A wafer dividing method of the present invention comprises: cutting a wafer into chips; And etching the backside of the chip unit wafer using a plasma source. According to the wafer dividing method and the wafer dividing system of the present invention, after the wafer is cut, the rear surface of the wafer is etched using plasma to prevent the wafer from being deformed or warped by the heat at a high temperature. In addition, defective semiconductor chips can be prevented from being formed due to the deformed wafer, and the defect rate can be reduced. Further, a filler is provided in the cut portion of the wafer divided into chip units so that the cut portion is not etched by the plasma source.

Wafer division, wafer cutting, wafer deformation prevention, wafer thinning, plasma etching

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer dividing method,

The present invention relates to a wafer dividing method and a wafer dividing system, and more particularly, to a wafer dividing method and a wafer dividing system for minimizing a defective rate generated when a wafer is cut into chip units and then a wafer is thinned to produce chips on a chip- .

The semiconductor production process is divided into a front process, which is a process of forming a chip-by-chip circuit on a wafer, and a post-process, which is an assembly process.

Of these, the post-process is divided into a laminating adhesive process, a back-grinding process, a laminating process, a wafer-ring process process, and a wafer-cutting process. Hereinafter, each step of the post-process will be briefly described.

A method of dividing a wafer into chips is divided into a thinning process for thinning the wafer and a wafer cutting process for cutting the wafer into chips.

The laminating bonding process is a process of bonding a film for protecting the front surface of a wafer in which a plurality of integrated circuit elements are arrayed longitudinally and laterally through a previous process. This is to protect the circuit formed on the front side of the wafer transfer. The film to be used at this time has properties such that when the specific conditions of lightness and lightness are satisfied with the UV tape, the photosensitive component in the adhesive component of the tape is hardened and the adhesive force is lost.

The back grinding process is a process for reducing the thickness of the wafer by grinding the unused rear surface of the wafer, which is opposite to the active surface on which the integrated circuit is formed, of the wafer so as not to affect the integrated circuit. Such a process is generally called a back-grinding process. The wafer generally has a thickness of 730 to 750 탆 for 8 and a thickness of 790 to 800 탆 for 12 inch. The wafer backside grinding process thinly processes these wafer thicknesses to 50 to 450 μm. At this time, the final thickness of the target wafer may vary depending on the kind of the semiconductor product or the demand of the customer.

In the laminating removal and wafer processing process, a film for a subsequent process is removed by irradiating ultraviolet rays to a film which adheres and protects the front face of the wafer to eliminate adhesive force, and a wafer ring for fixing the wafer is placed on the rear face of the wafer .

The wafer cutting process is a process of separating individual chips arranged on the front surface of the wafer. In this process, the elements arranged on the wafer are separated by a mechanical method using a blade rotating at a high speed and a method using a plasma source. The wafer of the separated chip unit is commercialized through the assembly process. In other words, it provides electrical connection to the devices of the separated chip unit and hermetically packs it to withstand the external impact, so that it has the physical function and shape.

Recently, the productivity of the wafer is increased by increasing the yield of the wafer, the manufacturing cost is reduced, the package is lighter, and the miniaturization trend is accelerating. In order to satisfy this requirement, it is necessary to realize a thin wafer. Particularly, in order to make the wafer thin and thin, the rear surface of the wafer is etched by using a plasma source.

When the wafer is etched using the plasma, the wafer may be bent or deformed. Particularly, in the case of mass production of a device by increasing the size of the wafer, defective chip unit wafers and defective semiconductor products are produced when the wafer is bent or deformed due to the high temperature inside the plasma reactor. In addition, such defective wafers may cause even more serious problems as semiconductor products become thinner and thinner as the thickness of wafers becomes thinner.

In addition, the wafer can be cut in chip units using a plasma source, wherein the wafer is attached to a wafer ring or carrier equipped with a UV tape and cut. However, the uvi tape may be damaged by the heat of the high temperature and may not fix the wafer properly. In addition, the carrier formed of quartz is easily broken by heat at high temperature to shorten the lifetime, and a carrier formed of metal generates arcing with the metal chuck.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wafer dividing method and a wafer dividing system that can prevent a wafer from being deformed or broken by a plasma when a wafer is thinned using plasma, thereby minimizing a defective rate.

According to an aspect of the present invention, there is provided a wafer dividing method and a wafer dividing system. A wafer dividing method of the present invention comprises: cutting a wafer into chips; And etching the backside of the chip unit wafer using a plasma source.

In one embodiment, polishing the backside of the wafer mechanically prior to etching the backside of the wafer using a plasma source.

In one embodiment, the step of bonding the front adhesive layer to the front surface of the cut wafer is included.

In one embodiment, the wafer is formed with cutouts in units of chips.

In one embodiment, the cutout is formed over the entire thickness of the wafer.

In one embodiment, the cut portion of the wafer further includes a filler to prevent etching of the cut portion of the wafer by a plasma source.

In one embodiment, the filler is formed by injecting resin into the cut.

In one embodiment, the filler is formed by inserting a wire insertion member formed in a mesh shape into the cut portion.

In one embodiment, the filler is formed by flowing the front adhesive layer into the cut portion.

The wafer dividing system of the present invention includes: a wafer cutting device for cutting the wafer into chips; And a wafer etch device for etching the backside of the wafer using a plasma source.

In one embodiment, the apparatus includes a front adhesive layer attachment device for attaching a front adhesive layer to a front surface of the wafer.

In one embodiment, the plasma source is formed in the manner of a remote plasma generator (RPG), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP).

In one embodiment, the wafer dividing system further comprises a transferring means for sucking and transferring one surface of the wafer.

According to the wafer dividing method and the wafer dividing system of the present invention, after the wafer is cut, the rear surface of the wafer is etched using plasma to prevent the wafer from being deformed or warped by the heat at a high temperature. In addition, defective semiconductor chips can be prevented from being formed due to the deformed wafer, and the defect rate can be reduced. Further, a filler is provided in the cut portion of the wafer divided into chip units so that the cut portion is not etched by the plasma source.

For a better understanding of the present invention, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. The embodiments of the present invention may be modified into various forms, and the scope of the present invention should not be construed as being limited to the embodiments described in detail below. The present embodiments are provided to enable those skilled in the art to more fully understand the present invention. Therefore, the shapes and the like of the elements in the drawings can be exaggeratedly expressed to emphasize a clearer description. It should be noted that in the drawings, the same members are denoted by the same reference numerals. Detailed descriptions of well-known functions and constructions which may be unnecessarily obscured by the gist of the present invention are omitted.

FIG. 1 is a flowchart showing a wafer dividing process according to a preferred embodiment of the present invention, and FIG. 2 is a view showing a cross section of a wafer processed in the steps shown in FIG.

As shown in FIGS. 1 and 2, the overall process steps of dividing the wafer of the present invention into chip units can roughly be divided into a wafer cutting process and a wafer thinning process. The wafer cutting process includes a wafer backside adhesive layer adhering step and a wafer cutting step. The wafer thinning process includes a wafer front adhesive layer deposition step, a wafer backside adhesive layer removal step, and a wafer backside plasma etching step.

Hereinafter, the wafer cutting step and the wafer thinning step will be described in order.

First, the wafer cutting process will be described.

The step of adhering the back surface adhesive layer of the wafer is a step of adhering the back surface adhesive layer 22 to the back surface of the wafer 10 on which the circuit is formed from the front step (S100). The backside adhesive layer 22 includes an adhesive component and is adhered to the rear surface of the wafer 10. [ In the present invention, a UV tape is used as the backside contact layer 22 (shown in Fig. 2 (a)).

The wafer cutting step is a step of cutting the wafer 10 fixed on the adhesive layer 20 on a chip basis along a cutting line between a plurality of chips formed on the wafer 10 (S110). A method of cutting the wafer 10 in units of chips includes a mechanical cutting method and a plasma source cutting method. In the present invention, a mechanical device or a method of cutting using a plasma source can be applied. When the wafer is cut using a plasma source, the wafer is cut by masking in chip units. When the wafer 10 is cut in chip units, the cut portions 12 are formed between the wafers of each chip unit to a predetermined depth. The cut portion 12 in the present invention is formed over the entire thickness of the wafer 10 to completely cut the wafer 10 in units of chips (shown in FIG. 2 (b)).

Next, the wafer thinning process will be described.

The front adhesive layer 24 is attached to the front surface of the wafer 10 cut in chip units (S120). The front adhesive layer 24 uses a UV tape in the same configuration as the back surface adhesive layer 22. The front adhesive layer 24 is attached to the front surface of the wafer 10 and fixes the wafers 10 cut in chip units so as not to be separated from the rear adhesive layer 22 bonded to the rear surface of the wafer 10 2 (c)).

The wafer 10 is inverted and positioned so that the rear mating layer 22 adhered to the rear surface can be positioned at the top. The wafer backside adhesive layer 22 located on the upper side is removed so that the backside of the wafer 10 can be exposed to the outside by irradiating ultraviolet rays with UV tape to dissipate the adhesive force (S130) (see FIG. 2 (d) ).

In order to form the wafer 10 of a chip unit to have a desired thickness, the rear surface of the wafer 10 is etched using a plasma source (S140). The plasma source is generated inside the plasma reactor by a remote plasma generation (RPG) method, a capacitive coupled plasma (CCP) method and an inductively coupled plasma (ICP) method. In the plasma reactor, the wafer 10 formed in the above process is positioned and etched through a plasma source (shown in FIG. 2 (e)).

The rear surface of the wafer 10 to be etched is warped or deformed because high temperature heat is generated when the rear surface of the wafer 10 is etched using the plasma source. The greater the area of the wafer 10 that the plasma source touches, the higher the probability of deformation. Thus, the present invention cuts the wafer 10 into chips and then etches the backside. Since the unit area of the wafer 10 to which the plasma source touches is smaller than the area of the entire wafer 10, wafer deformation due to high temperature heat does not occur.

3 is a block diagram of a wafer segmentation system showing devices for performing a wafer segmentation process.

As shown in FIG. 3, the wafer 10 having a circuit formed on the front side from the previous step is transferred to the rear adhesive layer attaching device 90, and the rear adhesive layer 22 is attached to the rear face of the wafer 10. The wafer 10 to which the backside adhesive layer 22 is adhered is cut in chip units in the wafer cutting apparatus 91. The front adhesive layer 24 is attached to the front surface of the wafer 10 in the front adhesive layer attaching device 93. [ The wafer 10 to which the front adhesive layer 24 and the rear adhesive layer 22 are attached is inverted and transferred to the rear adhesive layer removing device 95 so that the rear adhesive layer 22 is positioned at the top. In the backside adhesive layer removing device 95, the backside adhesive layer 22 provided on the wafer 10 is removed. This is the step of exposing the backside of the wafer 10 to etch the backside of the wafer 10. The rear surface of the wafer 10 is transferred to the plasma etching apparatus 97 with the rear surface exposed, and the rear surface of the wafer 10 is etched by the plasma source.

The wafer 10 is transferred to the next device to perform the next process when the process is completed in the present process device. Between each processing apparatus, the wafer 10 is processed and transported by a wafer ring (not shown).

Fig. 4 is a view showing a wafer rear surface plasma etching apparatus arranged in parallel along a working line.

As shown in FIG. 4, the plurality of plasma etching apparatuses 97 are arranged in parallel along one operation line 110, such as a conveyor belt. The wafer 10 from which the backside adhesive layer 22 has been removed in the backside adhesive layer removing apparatus 95 is provided to a plurality of plasma etching apparatuses 97 to perform a plasma etching process followed by an assembling process. In an embodiment of the present invention, a plurality of plasma etch devices 97 are arranged in parallel along the operation line 110, but they may also be arranged in a line along the operator 110.

5 to 6 are views showing wafer transfer means used in the wafer division system.

As shown in Figs. 5 and 6, the wafer division system requires a transfer means 200 for transferring the wafer 10 between the respective devices. The conveying means 200 is composed of an arm 212 and a suction portion 214. The arm 212 is vertically adjustable in length and is horizontally rotatable so that the wafer 10 can be inserted and withdrawn between the devices. The adsorption unit 214 is provided at the end of the arm 212 to supply the respective surfaces of the wafer 10, preferably the front surface of the wafer 10, to each apparatus through adsorption. The processed wafer 10 in each apparatus is again attracted by the conveying means 200 and output from each apparatus.

The integrated conveying means 300 may be constructed by connecting the upper portion of the arm 312 of the plurality of conveying means 200 with the horizontal bar 320 so that a plurality of wafers 10 can be conveyed at a time. In an embodiment of the present invention, the three conveying means 200 are connected by the horizontal bar 520 to form the integral conveying means 300. Three adsorption units 314 were used to simultaneously adsorb three wafers 10. The integrated conveyance means 300 can control the number of conveyance means 200 according to the number of wafers 10 to be conveyed.

7 is a diagram showing a plasma reactor providing plasma by an inductively coupled plasma (ICP) method.

As shown in FIG. 7, the plasma etching apparatus includes a plasma reactor 330 and a process gas supply unit 338. The plasma reactor 330 is provided with an inlet 331 at one side so that the wafer 200 can be input and output and a gas inlet 332 for supplying the process gas and an upper electrode 335 for distributing the process gas And a substrate support 336 on which a substrate to be processed is placed. Further, a coil antenna 334 is provided on the upper part of the plasma reactor 330. The coil antenna 334 receives the frequency power from the power source 410 to induce inductively coupled plasma. The frequency power supplied from the power supply source 410 is applied to the coil antenna 334 through the impedance matcher 420. The coil antenna 334 can be driven at a single frequency or at multiple frequencies. A substrate support 336 is coupled to bias power source 412 and biased. For example, two bias power supplies or one power supply 412 supplying different frequency power are electrically coupled and biased to the substrate support 336 through the impedance matcher 422. The dual bias structure of the substrate support 336 facilitates plasma generation within the plasma reactor 330 and may further improve plasma ion energy control to improve process throughput. Or a single bias structure. Alternatively, the substrate support 336 may be deformed into a structure having a zero potential without the supply of bias power. And the substrate support 336 may comprise an electrostatic chuck (not shown). Or the substrate support may include a heater (not shown). The substrate support 336 is also connected to a DC power source 430.

The process gas supply unit 338 is connected to a gas inlet 332 provided in the plasma reactor 330 to supply a process gas for inducing an inductively coupled plasma.

Figure 8 is a diagram illustrating a plasma reactor providing plasma in a capacitively coupled plasma (CCP) fashion.

As shown in FIG. 8, includes a plasma reactor 330, a gas supply unit 350, and a capacitive coupling electrode assembly 337. The plasma reactor 330 is constructed in the same manner as the inductively coupled plasma reactor described above. A gas supply part 350 for distributing the process gas is provided on the upper part of the plasma reactor 330. The gas supply unit 350 includes a baffle 335 therein and receives the process gas through the gas inlet 339 and injects the process gas into the plasma reactor 330 through the plurality of gas injection holes 339. The capacitive coupling electrode assembly 337 is provided under the gas supply unit 350 to induce capacitive coupling plasma using a process gas.

9 is a view showing a first embodiment of a plasma reactor.

As shown in FIG. 9, the plasma reactor 330 has an inlet / outlet 331 on one side thereof, and the wafer 10 can be taken in and out. The wafer 10 is introduced into the plasma reactor 330 through the inlet 331 of the plasma reactor 330 and placed on the substrate support 336 so that the plasma treatment is performed and then flows out through the inlet 331 again when the plasma treatment is completed .

10 is a view showing a second embodiment of a plasma reactor.

As shown in FIG. 10, the plasma reactor 330 is divided into an upper body 330-1 and a lower body 330-2. The upper body 330-1 is located on the upper portion of the lower body 330-2 and one side is connected to the lower chamber 333-2 by the hinge 450 to be opened and closed.

11 is a view showing a third embodiment of the plasma reactor.

As shown in FIG. 11, the plasma reactor 330 is divided into an upper body 330-1 and a lower body 330-2. The upper body 330-1 is located on the upper part of the lower body 330-2 and one side is connected to the lower body 330-2 by the elevating member 440. [ The upper body 330-1 is disconnected from the lower body 330-2 while the lifting member 440 is lifted so that the inside of the plasma reactor 330 is opened and the lifting member 440 is lowered again to the plasma reactor 330 are sealed.

The wafer 10 having undergone the wafer cutting step is formed with a cut portion 12 between each chip by a wafer cutting apparatus. The cut portion 12 may be etched together with the backside of the wafer 10 by a plasma source in the backside etching process of the wafer 10 using plasma. When the cut portion 12 is etched by the plasma, a normal chip can not be formed and a defective product is produced.

In order to prevent the etching of the cut portion 12 of the wafer 10 by the plasma, the step of cutting the wafer 10 is performed and then the step of providing the filler to the wafer cut portion 12 is performed. The filler is made of a material that can be easily separated from the wafer 10 without being etched by the plasma source so that the cut portion 12 is not etched even when the plasma source contacts the cut portion 12. Further, a separate step for removing the filler inserted into the cut portion 12 may be performed.

12 is a view showing a state in which a mesh wire is inserted into a wafer cutting portion.

As shown in Fig. 12, a mesh wire 44 formed in a mesh shape is used as a filler. Since the cut portion 12 of the wafer 10 attached to the front adhesive layer 24 is formed in a mesh shape, the mesh wire 44 is formed in the same shape as the cut portion 12 so as to be fitted in the cut portion 12.

13 is a diagram showing a cross section of a wafer in a state in which a mesh wire is inserted into a wafer cut portion.

As shown in Fig. 13, each wire of the mesh wire 44 is provided in the cutout 12 of the wafer 10 to prevent the cutout 12 from being etched by the plasma source.

14 is a view showing a cross section of a wafer in a state in which a resin is injected into a wafer cut portion.

As shown in Fig. 14, a resin 42 is injected into the cut portion 12 to prevent plasma etching, thereby forming a filler. The resin 42, which is a natural resin, is not etched by the plasma, and can be injected into the cut portion 12 to prevent etching. In addition, the height of the rear surface of the wafer to be etched can be confirmed by injecting the resin 42 into the cut portion 12 at a height other than the height of the rear surface of the wafer 10 to be etched.

15 is a view showing a cross section of a wafer in a state in which an adhesive layer is inserted into a wafer cut-out portion.

As shown in FIG. 15, the filler may be formed by using the front adhesive layer 24. That is, when the front adhesive layer 30 adhered to the front surface of the wafer 10 is pressed, the front adhesive layer 24 flows into the cut portion 12 and functions as a filler. The front adhesive layer 24 introduced into the cut portion 12 prevents the plasma source from being contacted with the wafer 10 to be etched.

16 is a flowchart showing a step of mechanically polishing the rear surface of the wafer and then etching the rear surface of the wafer using plasma to thin the wafer.

As shown in Fig. 16, the wafer is thinned first and secondarily.

First, laminating is performed on the entire surface of the wafer 10 on which a circuit is formed from the entire process (S200). The rear surface of the wafer 10 subjected to the laminating treatment is first mechanically polished (S210). The pre-polished wafer 10 removes lamination attached to the front side (S220). The mechanically polished wafer 10 is secondarily thinned using a plasma source to make the wafer 10 more finely thin. The backside adhesive layer 22 is attached to the rear surface of the wafer 10 (S230), and the wafer is cut into chips (S240). The front adhesive layer 24 is attached to the front surface of the cut wafer 10 (S250). The rear adhesive layer 22 adhered to the rear surface of the wafer 10 is removed (S260), and the rear surface of the wafer is etched using plasma (S270).

The embodiments of the wafer dividing method and the wafer dividing system of the present invention described above are merely illustrative and those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. You will know the point. Accordingly, it is to be understood that the present invention is not limited to the above-described embodiments. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims. It is also to be understood that the invention includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

1 is a flowchart illustrating a wafer dividing process according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view of the wafer processed in the steps shown in FIG. 1. FIG.

3 is a block diagram of a wafer segmentation system showing devices for performing a wafer segmentation process.

Fig. 4 is a view showing a wafer rear surface plasma etching apparatus arranged in parallel along a working line.

5 to 6 are views showing wafer transfer means used in the wafer division system.

7 is a diagram showing a plasma reactor providing plasma by an inductively coupled plasma (ICP) method.

Figure 8 is a diagram illustrating a plasma reactor providing plasma in a capacitively coupled plasma (CCP) fashion.

9 is a view showing a first embodiment of a plasma reactor.

10 is a view showing a second embodiment of a plasma reactor.

11 is a view showing a third embodiment of the plasma reactor.

12 is a view showing a state in which a mesh wire is inserted into a wafer cutting portion.

13 is a diagram showing a cross section of a wafer in a state in which a mesh wire is inserted into a wafer cut portion.

14 is a view showing a cross section of a wafer in a state in which a resin is injected into a wafer cut portion.

15 is a view showing a cross section of a wafer in a state in which an adhesive layer is inserted into a wafer cut-out portion.

16 is a flowchart showing a step of mechanically polishing the rear surface of the wafer and then etching the rear surface of the wafer using plasma to thin the wafer.

Description of the Related Art [0002]

10: wafer 12:

22: rear adhesive layer 24: front adhesive layer

42: Resin 44: Mesh wire

90: Backside adhesive layer adhering device 91: Wafer cutting device

93: front adhesive layer attachment device 95: rear adhesive layer removal device

97: Plasma etching apparatus 110: Operation line

200: conveying means 212, 312: arm

214, 314: suction part 320: horizontal bar

300: Integrated delivery means 330: Plasma reactor

330-1, 330-2: upper body, lower body 332, 339: gas inlet

334: coil antenna 335: baffle

336: substrate support 337: capacitive coupling electrode assembly

338: Process gas supply unit 339: Gas injection nozzle

350: gas supply unit 410: power supply source

412: Bias power source 420, 422: Impedance matcher

430: DC power supply 440:

450: Hinge

Claims (13)

Cutting the wafer into chips and forming cuts formed in the entire thickness of the wafer between the chip units; Inserting a wire insertion member formed in a mesh shape into the cut portion as a filler for preventing a cut portion of the wafer from being etched by a plasma source at a cut portion of the wafer; And And etching the backside of the chip unit wafer using a plasma source. The method according to claim 1, And mechanically polishing the backside of the wafer before etching the backside of the wafer with a plasma source. The method according to claim 1, And bonding the front adhesive layer to the front surface of the cut wafer before inserting the wire insertion member formed in a mesh shape into the cut portion. delete delete delete The method according to claim 1, Wherein the filler is formed by injecting resin into the cut portion. delete The method of claim 3, Wherein the filler is formed by flowing the front bonding layer into the cut portion. A wafer cutting device for cutting a wafer into chips; A mesh-shaped wire insertion member formed as a filler for preventing a cut portion of the wafer from being etched by a plasma source at a cut portion of the wafer; And And a wafer etch device for etching the backside of the wafer using a plasma source. 11. The method of claim 10, And a front adhesive layer attaching device for attaching a front adhesive layer to a front surface of the wafer. 11. The method of claim 10, Wherein the plasma source is formed in the manner of a remote plasma generator (RPG), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP). 11. The method of claim 10, Wherein the wafer dividing system further comprises transfer means for sucking and transferring one surface of the wafer.

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