KR101620683B1 - Cascode amplifier for changing a power - Google Patents

Abstract

A cascode amplifier capable of power conversion is disclosed. The folded cadence code amplifier includes a mirror circuit portion having first transistors of a mirror structure, a current source portion having second transistors connected to the first transistors, and a current source portion through which current flows through the mirror circuit portion and the current source portion, And an additional current portion for providing an additional current.

Description

{CASCODE AMPLIFIER FOR CHANGING A POWER}

The present invention relates to a cascode amplifier.

A cascode amplifier with high amplification efficiency is widely used in electronic devices. The cascode amplifier is designed to amplify to a specific voltage and power conversion is not possible.

In recent years, a mobile device that requires power conversion and a wearable device have appeared. However, current cascode amplifiers can not be used for power conversion because they can not be used in the mobile devices.

Korean Registered Patent No. 1125906 (registered on Mar. 5, 2012)

The present invention provides a cascode amplifier capable of power conversion.

According to an aspect of the present invention, there is provided a folded cascode amplifier including: a mirror circuit part having first transistors of a mirror structure; A current source having second transistors connected to the first transistors; And an additional current portion for providing an additional current to the current path through the mirror circuit portion and the current source portion according to a mode.

A cascode amplifier according to another embodiment of the present invention includes first transistors of a cascode structure; And an additional current portion providing additional current to the current path through the first transistors. Here, the additional current portion does not provide the additional current to the current path in the first mode but provides the additional current to the current path in the second mode.

The cascode amplifier according to the present invention, in particular, the folded cascode amplifier, provides an additional current in the cascode gain stage in the high power mode, thereby selectively implementing low power and high power.

1 is a schematic diagram illustrating a circuit of a cascode amplifier according to an embodiment of the present invention.
2 is a circuit diagram of a folded cascode amplifier according to another embodiment of the present invention.
3 is a mode control circuit according to an embodiment of the present invention.
4 is a diagram showing a circuit of a folded cascode amplifier in the low power mode.
5 is a diagram showing a circuit of a folded cascode amplifier in a high power mode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cascode amplifier, and more particularly, to a cascode amplifier that can be implemented in a high-power mode and a low-power mode.

For example, the cascode amplifier may operate in a high power mode or a low power mode depending on a user's selection. According to one embodiment, the cascode amplifier can provide additional current in the current path of the cascode gain stage in the high power mode to achieve high power.

Therefore, the cascode amplifier of the present invention can be used in mobile devices, wearable electronic devices, and the like that require power conversion.

Hereinafter, various embodiments of the cascode amplifier of the present invention capable of power conversion will be described.

1 is a schematic diagram illustrating a circuit of a cascode amplifier according to an embodiment of the present invention. However, FIG. 1 shows a folded cascode amplifier in which only a gain stage is illustrated and a current source is omitted for convenience of explanation.

Referring to Fig. 1, the cascode amplifier of the present embodiment may include a cascode gain stage and additional current portions (current sources, SW1 and SW2) having mirror circuits PM1 and PM2 and bias circuits PM3 and PM4 have.

The sources of the transistors PM1 and PM2 as mirror circuits are connected to the power supply voltage V _DD , respectively.

The same bias voltage is applied to the gates of the transistors PM3 and PM4 as a bias circuit and the source of the transistor PM3 is connected to the drain of the transistor PM1 and the source of the transistor PM4 is connected to the drain of the transistor PM2 Lt; / RTI >

The additional current section may or may not provide the specific current i2 according to the mode to the current path of the cascode gain stage. According to one embodiment, the additional current portion is inactivated when the user selects the low power mode, and can be activated when the high power mode is selected. Specifically, when the user selects the low power mode, the switches SW1 and SW2 are turned off, so that the current i2 is not provided to the cascode gain stage. On the other hand, when the user selects the high power mode, the switches SW1 and SW2 are turned on, and as a result, the current i2 is provided to the cascode gain stage. Therefore, the output current of the cascode amplifier increases and the power of the cascode amplifier can be increased.

In summary, the cascode amplifier of this embodiment can realize high power by providing the additional current i2 in the high power mode as a cascode gain stage.

However, as long as the additional current i2 in the high power mode is provided as a cascode gain stage, the circuit configuration of the cascode gain stage and the additional current section may be variously modified. Although FIG. 1 shows a folded cascode amplifier, the technical features of the present invention can be applied to a cascode amplifier having a single structure rather than a folded structure.

Although not described above, the two current sources of the supplementary current portion can have the same intensity. For stable operation of the cascode amplifier, the current i1 flowing through the cascode gain terminal and the current i2 supplied from the additional current section may be the same.

Although the current source supplies the current of the additional current portion in FIG. 1, a transistor connected to the power source voltage may be used instead of the current source. In contrast, the transistor may have the same size as the transistors PM1 and PM2.

FIG. 2 is a circuit diagram of a folded cascode amplifier according to another embodiment of the present invention, and FIG. 3 is a mode control circuit according to an embodiment of the present invention. Fig. 4 is a diagram showing a circuit of a folded cascode amplifier in a low power mode, and Fig. 5 is a diagram showing a circuit of a folded cascade amplifier in a high power mode.

Referring to FIG. 2, the folded cascode amplifier of the present embodiment includes an input section 200, a cascode gain stage, and an additional current section.

The cascade gain stage includes a current source 202 and a mirror circuit 204 and the additional current includes transistors PM11, PM8, PM9, PM10, NM5, NM6 and NM7.

The input section 200 may include three P-MOS transistors PM1, PM2 and PM3 forming a differential amplifier.

The source of the transistor PM1 is connected to the power source voltage V _DD and the drain is connected to the source of the differential transistor pair PM2 and PM3. A bias voltage V _b4 is applied to the gate of the transistor PM1. As a result, a bias current is provided to the differential transistor pair PM2 and PM3.

The gate of the transistor PM2 is connected to the positive differential input terminal, and the input voltage V _INP is input to the gate.

The gate of the transistor PM3 is connected to the negative differential input terminal, and the input voltage V _INN is input to the gate.

P-MOS transistors PM11 and PM8 among the components of the additional current part may be connected to the input part 200 having such a circuit configuration.

A first control signal CS1 is input to the gate of the switch PM11, a bias voltage _Vb4 is applied to the source, and a drain thereof is connected to the gate of the transistor PM8.

The source of the transistor PM8 is connected to the power source voltage V _DD and the gate is connected to the bias voltage V _b4 and the drain is connected to the source of the differential transistor pair PM2 and PM3. That is, the transistor PM8 is connected in parallel to the transistor PM1 of the input unit 200 on the basis of the power supply voltage V _DD .

According to one embodiment, in the low power mode, the transistor PM11 is turned off by the first control signal CS1 having a high logic, so that the bias voltage V _b4 is not input to the gate of the transistor PM8 Do not. On the other hand, in the high power mode, the transistor PM11 is turned on by the first control signal CS1 having the low logic, so that the bias voltage V _b4 is input to the gate of the transistor PM8. As a result, a bias current having the same magnitude as the bias current flowing through the transistor PM1 can flow through the transistor PM8. Therefore, the current flowing from the high-power mode to the differential-transistor pair PM2 and PM3 can be twice the current flowing from the differential-transistor pair PM2 and PM3 in the low-power mode.

Of course, if the size of the transistor PM8 is adjusted, the bias current flowing through the transistor PM1 and the bias current flowing through the transistor PM8 may be different. However, in order to supply a stable bias current, PM8. To this end, the transistors PM1 and PM8 may have the same size.

A current flowing through the input unit 200 may be provided to the current source 202. [

The current source 202 may include a current source made up of an N-MOS transistor NM1 and a current source made up of an N-MOS transistor NM2.

The drain of the transistor NM1 is connected to the current mirror portion 204, the source is connected to the ground voltage V _SS , and the bias voltage V _b1 can be applied to the gate.

The drain of the transistor NM2 is connected to the current mirror portion 204, the source is connected to the ground voltage V _SS , and the bias voltage V _b1 can be applied to the gate.

Among the components of the additional current portion, the P-MOS transistors NM5, NM6, and NM7 may be connected to the current source 202 having such a circuit configuration.

To the gate of the switch transistor (NM7) is input to the second control signal (CS2), the drain is applied with a bias voltage (V _b1), the source may be connected to the gates of the transistors (NM5 and NM6) .

The drain of the transistor NM5 is connected to the drain of the transistor NM1, and the source thereof may be connected to the ground voltage _Vss .

The drain of the transistor NM6 is connected to the drain of the transistor NM2, and the source thereof may be connected to the ground voltage _Vss .

According to one embodiment, in the low power mode, the second control signal CS2 having the low logic is input to the gate of the transistor NM7 to turn off the transistor NM7, so that the transistors NM5 and NM6 are turned on Deactivated. On the other hand, the second control signal (CS2) having a high-logic is input to the gate of the transistor (NM7) transistor (NM7) is turned on, the gate of when turned on, the bias voltage (V _b1) the transistors (NM5 and NM6) . As a result, the transistors NM5 and NM6 can be activated.

In this case, the current flowing through the transistor NM5 may be equal to the current flowing through the transistor NM1, and the current flowing through the transistor NM6 may be equal to the current flowing through the transistor NM2. Preferably, the currents flowing to the transistors NM1, NM2, NM5, and NM6 may all be the same. Transistors NM1, NM2, NM5 and NM6 of the same size can be used for this purpose.

Of course, by adjusting the sizes of the transistors NM5 and NM6, the intensity of the current flowing through the transistors NM5 and NM6 may be different from the current flowing through the transistors NM1 and NM2, but in order to operate as a stable current source It is effective that the same current flows through the transistors NM1, NM2, NM5, and NM6. For this purpose, the transistors NM1, NM2, NM5 and NM6 may have the same size.

The mirror circuit unit 204 includes a pair of P-MOS transistor PM4 and PM5 forming a current mirror, a pair of P-MOS transistor PM6 and PM7 as a first bias circuit, and a pair of NMOS transistor NM3 And NM4).

The sources of the transistors PM4 and PM5 may be connected to the power supply voltage V _DD .

The source of the transistor PM6 is connected to the drain of the transistor PM4, and the bias voltage _Vb3 can be applied to the gate.

The source of the transistor PM7 is connected to the drain of the transistor PM5, and the bias voltage _Vb3 can be applied to the gate.

The drain of the transistor NM3 is connected to the drain of the transistor PM6, the source is connected to the drain of the transistor NM1, and the bias voltage _Vb2 may be applied to the gate.

The drain of the transistor NM4 is connected to the drain of the transistor PM7, the source thereof is connected to the drain of the transistor NM2, and the bias voltage _Vb2 may be applied to the gate.

The P-MOS transistors PM12, PM9 and PM10 among the components of the additional current portion can be connected to the mirror circuit portion 204 having such a circuit configuration.

The third control signal CS3 may be input to the gate of the transistor PM12, and the drain may be coupled to the drain of the transistor PM6. According to one embodiment, the third control signal CS3 may be the first control signal CS1.

The gate of the transistor PM9 may be connected to the source of the transistor PM12, the source may be connected to the power supply voltage V _DD , and the drain may be connected to the drain of the transistor PM4.

The gate of the transistor PM10 may be connected to the source of the transistor PM12, the source may be connected to the power supply voltage V _DD and the drain may be connected to the drain of the transistor PM5.

According to one embodiment, in the low power mode, the third control signal CS3 having a high logic is input to the gate of the transistor MP12 to turn off the transistor PM12, so that the transistors PM9 and PM10 Can be deactivated. On the other hand, in the high power mode, the third control signal CS3 having the low logic is input to the gate of the transistor PM12 to turn on the transistor PM12, so that the transistors PM9 and PM10 are activated .

In this case, the current flowing through the transistor PM9 may be equal to the current flowing through the transistor PM4, and the current flowing through the transistor PM10 may be equal to the current flowing through the transistor PM5. Preferably, the currents flowing to the transistors PM4, PM5, PM9 and PM10 may all be the same. Transistors PM4, PM5, PM9 and PM10 of the same size can be used for this purpose.

Of course, when the sizes of the transistors PM9 and PM10 are adjusted, the intensity of the current flowing through the transistors PM9 and PM10 may be different from the current flowing through the transistors PM4 and PM5. However, PM5, PM9, and PM10 through the transistors PM4, PM5, PM9, and PM10. For this purpose, the transistors PM4, PM5, PM9 and PM10 may have the same size.

Hereinafter, a mode-dependent operation of the folded cascode amplifier of this structure will be described.

In the low power mode, the control signals CS1 and CS3 of the high logic are input to the transistors PM11 and PM12 of the additional current portion, and the control signal CS2 having the low logic can be input to the transistor NM7. At this time, the control signal CS2 may be an inverting signal generated by inverting the control signal CS1 or CS3 as shown in Fig.

In this case, the transistors PM11, PM12 and NM7 are turned off, so that the transistors PM8, PM9, PM10, NM5 and NM6 are inactivated. As a result, the Paulette squared code amplifier has the structure shown in Fig.

In the high power mode, the control signals CS1 and CS3 of the low logic are input to the transistors PM11 and PM12 of the additional current portion, and the control signal CS2 having the high logic can be input to the transistor NM7.

In this case, the transistors PM11, PM12 and NM7 are turned on, and as a result, the transistors PM8, PM9, PM10, NM5 and NM6 are activated. As a result, the Paul de Dikas code amplifier has the structure shown in Fig.

If the transistors PM1 and PM8 have the same size and the transistors PM4, PM5, PM9 and PM10 have the same size and the transistors NM1, NM2, NM5 and NM6 have the same size, The same current i1 flows through the transistors PM1 and PM8 as shown and the same current i2 can flow through the transistors PM4, PM5, PM9, and PM10. As a result, (2 x i2) can flow through the transistors PM6 and PM7.

That is, in the low power mode, the current i2 flows through the transistors PM6 and PM7, whereas in the high power mode, twice the current (2 x i2) flows through the transistors PM6 and PM7 .

The characteristics of the folded cascode amplifier of FIG. 2 in the low power mode and the high power mode are shown in Table 1 below.

parameter Value at high power mode Value at low power mode Power supply voltage 2.7V 2.7V DC gain 72.6 dB 75.8 dB Phase margin 50 ° 60 ° Unity gain frequency 30 MHz 19 MHz Power consumption 87 ㎼ 43 ㎼

As can be seen in the above table 1, in the high power mode, the unit gain frequency and the slew-rate of the cascode amplifier are increased. In the low power mode, half of the power of the high power mode can be operated. Therefore, the folded cascode amplifier of the present invention can be usefully used in devices requiring dynamic power.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. Should be regarded as belonging to the following claims.

200: input unit 202: current source
204: mirror circuit part

Claims (9)

A mirror circuit portion having first transistors of a mirror structure;
A current source having second transistors connected to the first transistors; And
And an additional current portion for providing an additional current to the current path through the mirror circuit portion and the current source portion according to a mode,
Wherein the additional current unit includes third transistors connected in parallel to the first transistors based on a power supply voltage and fourth transistors connected in parallel to the second transistors based on a ground voltage,
In the low power mode, the third transistors and the fourth transistors are deactivated, and in the high power mode, the third transistors and the fourth transistors are activated,
Wherein a current flowing to the first transistors and an additional current flowing to the third transistors in the high power mode are the same and a current flowing to the second transistors and a current flowing to the fourth transistors are equal to each other, Deep cascode amplifier. The folded cascade amplifier of claim 1, wherein the additional current portion provides the additional current in the current path in the high power mode without providing the additional current in the current path in the low power mode. . 3. The method of claim 2, wherein the gates of the third transistors are connected to the node between the gates of the first transistors, and the gates of the fourth transistors are connected to the node between the gates of the second transistors A folded cascode amplifier. The method of claim 3,
Further comprising an input section having a pair of fifth transistors to which input voltages are applied and a sixth transistor commonly connected to the sources of the fifth transistors,
The fifth transistors are connected to the second transistors, and the additional current unit further includes a seventh transistor connected in parallel to the sixth transistor based on the voltage voltage,
And the seventh transistor is deactivated in the low power mode and activated in the high power mode. The method of claim 4, wherein a first control signal is input to the switches for controlling activation of the third transistors and the seventh transistor, and a second control signal is applied to a switch for controlling activation of the fourth transistors &Quot;
And the second control signal is an inverting signal of the first control signal. 5. The folded cascade amplifier of claim 4, wherein the current flowing from the high power mode to the sixth transistor is equal to the current flowing from the seventh transistor.
















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